Methods Of Fabricating Integrated Circuitry
A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.
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Embodiments disclosed herein pertain to methods of fabricating integrated circuitry.
BACKGROUNDIntegrated circuitry fabrication continues to make ever smaller features to minimize the size of individual device components and thereby increase density of the components within an integrated circuit. One common component in integrated circuitry is a longitudinally elongated electrically conductive line, for example a global or local interconnect line. Such lines may be formed by subtractive patterning and etch of conductive material. Alternately, a trench having a desired longitudinal outline of the conductive line may be formed in semiconductive or other material. Then, the trench may be wholly or partially filled with conductive material. The conductive material received laterally outward of the trench is then removed. Elemental metals, metal alloys, and conductive metal compounds are commonly used as materials of conductive interconnect lines.
Conductive interconnect lines may be formed at different levels or elevations relative to a substrate. Additionally, those lines at different levels may need to be conductively interconnected. One manner of doing so includes forming dielectric material over lower or inner fabricated interconnect lines. Via openings are then formed there-through to the underlying line or lines, and are subsequently filled with conductive material. Conductive lines are then formed outward of the dielectric material and which electrically couple with the conductive material that is within the via openings.
Example embodiments of methods of fabricating integrated circuitry in accordance with the invention are described with reference to
A first conductive line 14 has been formed relative to substrate 10. Multiple such lines would likely be fabricated, with only a single line being shown. First conductive line 14 may be formed by any existing or yet-to-be-developed manner, configuration, and/or orientation, with a longitudinally elongated and horizontal orientation and construction being shown. In this document, horizontal refers to a general direction along a primary surface relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another independent of orientation of the substrate in three-dimensional space. Further in this document, “elevational” and “elevationally” are with reference to the vertical direction relative to a base substrate upon which the circuitry has been fabricated.
Conductive line 14 may be fabricated of any suitable conductive material(s). In one embodiment, at least a majority of conductive line 14 comprises, consists essentially of, or consists of one or more of elemental metal(s), alloys of two or more elemental metals, and/or conductive metal compounds. In one embodiment and as shown, first conductive line 14 comprises an exterior lining 16 (e.g., elemental tantalum) surrounding a different composition central and majority material 18 (e.g., elemental copper). As used herein, “different composition” only requires those portions of two stated materials that may be directly against one another to be chemically and/or physically different, for example if such materials are not homogenous. If the two stated materials are not directly against one another, “different composition” only requires that those portions of the two stated materials that are closest to one another be chemically and/or physically different if such materials are not homogenous. In this document, a material or structure is “directly against” another when there is at least some physical touching contact of the stated materials or structures relative one another. In contrast, “over”, “on”, and “against” not preceded by “directly”, encompass “directly against” as well as construction where intervening material(s) or structure(s) result(s) in no physical touching contact of the stated materials or structures relative one another.
Regardless, first conductive line 14 comprises an elevationally outermost surface 20 which in one embodiment comprises copper, and in one embodiment comprises elemental copper. In one embodiment, outermost surface 20 is planar. In one embodiment, dielectric material 12 comprises exposed non-conductive material that is provided laterally of first conductive line 14. In one embodiment, non-conductive material 12 has a planar elevationally outermost surface 22 which in one embodiment is coplanar with planar outermost surface 20 of first conductive line 14.
Referring to
In one embodiment, the selective depositing of the first elemental tungsten is by chemical vapor deposition within a deposition chamber using gaseous WF6 and SiH4 as deposition precursors which are fed to the chamber during the deposition. Inert and/or other gases may be fed to the chamber during the deposition. In one embodiment during the deposition, substrate temperature is from about 250° C. to about 350° C., chamber pressure is from about 1 mTorr to about 100 mTorr, WF6 flow rate to the chamber is from about 10 sccm to about 1,000 sccm, and SiH4 flow rate to the chamber is from about 5 sccm to about 50 sccm. An example inert gas flow rate (e.g., Ar) is from 0 sccm to about 1,000 sccm. Flow rates provided herein are ideally to or at the substrate independent of chamber volume.
In one embodiment, the selective depositing of the first elemental tungsten is by chemical vapor deposition within a deposition chamber using gaseous WF6 and H2 as deposition precursors which are fed to the chamber during the deposition. Inert and/or other gases may be fed to the chamber during the deposition. In one embodiment during the deposition, substrate temperature is from about 300° C. to about 450° C., chamber pressure is from about 20 Torr to about 250 Torr, WF6 flow rate to the chamber is from about 100 sccm to about 500 sccm, and H2 flow rate to the chamber is from about 1,000 sccm to about 30,000 sccm. An example inert gas flow rate (e.g., Ar) is from 0 sccm to about 1,000 sccm.
Referring to
Referring to
Referring to
Referring to
A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via. Such may occur by a number of manners. For example, conductive materials 34 and 40 of
An embodiment of the invention encompasses forming a first conductive line and depositing first elemental tungsten directly against an elevationally outer surface thereof selectively relative to any exposed non-conductive material. In other words, exposed non-conductive material need not be present during the depositing of the first elemental tungsten directly against an elevationally outer surface of first conductive line. Yet if exposed non-conductive material is present, deposition of the first elemental tungsten occurs selectively to the line in comparison to the exposed non-conductive material. Further and regardless, the first elemental tungsten may or may not deposit all along the first conductive line, for example depending on whether all or a portion of elevationally or other outer surfaces thereof are exposed. Regardless, dielectric material is formed elevationally over the first conductive line and regardless of presence of non-conductive material laterally thereof. A via is formed through the dielectric material to conductive material of the first conductive line at a location where the first tungsten was deposited. Such via formation may occur regardless of whether the first tungsten remains as initially deposited, has been wholly or partially removed, or has been replaced or transformed into another conductive material which may or may not comprise tungsten. Regardless, second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line independent of whether another conductive material has been provided between the second tungsten and the first conductive line. A second conductive line is formed elevationally outward of and electrically couples to the second tungsten which is within the via.
A predecessor process to those in accordance with the invention sputter-deposited (i.e., physical vapor deposited) elemental titanium into a via formed in dielectric material and that extended to a conductive elemental copper-comprising line. That titanium was deposited as a liner, and titanium nitride was sputter-deposited thereover as an additional conductive liner. The titanium enhances interface properties between the titanium nitride and copper, such as improving adhesion between titanium nitride and copper than would otherwise occur in the absence of titanium. Physical vapor deposition of each of titanium and titanium nitride may not achieve desirable step coverage particularly in very small openings and/or in those having high aspect ratios. Further, titanium and titanium nitride are typically physical vapor deposited using elemental titanium targets. An inert gas (e.g., Ar) is typically used as the sputtering source for depositing elemental titanium, and nitrogen gas is used as the sputter source for TiN. If sputter depositing elemental titanium in the same chamber in which titanium nitride is sputter-deposited, the target typically needs to be cleaned after sputter depositing titanium nitride to return the target surface to pure titanium to avoid a subsequent titanium nitride layer from being deposited before sputter depositing titanium. Alternately, two different chambers may be used for depositing titanium and titanium nitride. Regardless, in accordance with one embodiment of the invention, a method of fabricating integrated circuitry relative to a substrate is devoid of depositing elemental titanium directly against elemental copper of the first conductive line.
Physical, chemical, or atomic layer deposition may be used in deposition of conductive materials in accordance with embodiments of the invention, with chemical vapor deposition or atomic layer deposition being ideal.
ConclusionIn some embodiments, a method of fabricating integrated circuitry comprises forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.
In some embodiments, a method of fabricating integrated circuitry comprises forming a first conductive line having an elevationally outermost surface comprising copper. An exposed non-conductive material is provided laterally of the first conductive line. First elemental tungsten is deposited directly against the copper-comprising surface along at least a majority of longitudinal length of the first conductive line. The first tungsten is deposited selectively to the first conductive line relative to the exposed non-conductive material. Dielectric material is formed elevationally over and directly against the first tungsten and a via is formed through the dielectric material to the first tungsten. A conductive material is formed directly against the first tungsten after forming the via. Second elemental tungsten is non-selectively deposited to within the via directly against the conductive material. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.
In some embodiments, a method of fabricating integrated circuitry comprises forming a first conductive line having a planar elevationally outermost surface at least a majority of which comprises elemental copper. Non-conductive material is provided laterally of the first conductive line. The non-conductive material has a planar elevationally outermost surface that is coplanar with the planar outermost surface of the first conductive line. First elemental tungsten is deposited directly against the copper-comprising surface along at least a majority of longitudinal length of the first conductive line. The first tungsten is deposited selectively to the first conductive line relative to the coplanar outermost surface of the non-conductive material. Dielectric material is formed elevationally over and directly against the first tungsten and the non-conductive material. A via is formed through the dielectric material to the first tungsten. A conductive material liner is formed within the via over sidewalls of the via, within the via directly against the first tungsten, and elevationally over the dielectric material. Second elemental tungsten is non-selectively deposited to within the via directly against the conductive material liner and elevationally over that portion of the conductive material liner that is elevationally over the dielectric material. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
Claims
1. A method of fabricating integrated circuitry, comprising:
- forming a first conductive line;
- depositing first elemental tungsten directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material;
- forming dielectric material elevationally over the first conductive line and forming a via there-through to conductive material of the first conductive line at a location where the first tungsten was deposited;
- non-selectively depositing second elemental tungsten to within the via and which electrically couples to the first conductive line; and
- forming a second conductive line elevationally outward of and electrically coupled to the second tungsten that is within the via.
2. The method of claim 1 wherein at least a majority of the first conductive line is elemental copper.
3. The method of claim 1 wherein the second elemental tungsten is deposited at a deposition rate of about 1:1 within the via versus laterally outward of the via.
4. The method of claim 1 wherein the fabricating is relative to a substrate, and comprising providing exposed non-conductive material on the substrate during the selective depositing.
5. The method of claim 4 wherein no tungsten deposits on the exposed non-conductive material during the selective depositing.
6. The method of claim 5 wherein the second elemental tungsten is deposited at a deposition rate of about 1:1 within the via versus laterally outward of the via.
7. The method of claim 1 wherein the first tungsten is deposited to a total elevational thickness from about 50 Angstroms to about 500 Angstroms.
8. The method of claim 1 wherein the second tungsten is not deposited directly against the first tungsten.
9. The method of claim 1 comprising forming a conductive material liner within the via over sidewalls of the via and elevationally over the first tungsten before the non-selectively depositing of the second tungsten.
10. The method of claim 9 comprising forming the conductive material liner to comprise TiN.
11. The method of claim 10 comprising forming the TiN by at least one of chemical vapor deposition and atomic layer deposition.
12. The method of claim 9 comprising forming the conductive material liner to comprise WN.
13. The method of claim 12 comprising forming the WN by at least one of chemical vapor deposition and atomic layer deposition.
14. The method of claim 9 comprising forming the conductive material liner to comprise physical vapor deposited elemental tungsten.
15. The method of claim 1 wherein at least a majority of the first conductive line is elemental copper, the method being devoid of depositing elemental titanium directly against elemental copper of the first conductive line.
16. The method of claim 1 wherein the selectively depositing is by chemical vapor deposition within a deposition chamber, gaseous WF6 and SiH4 comprising deposition precursors fed to the chamber during said selectively depositing.
17. The method of claim 16 wherein the fabricating is relative to a substrate, and comprising substrate temperature from about 250° C. to about 350° C., chamber pressure from about 1 mTorr to about 100 mTorr, WF6 flow rate to the chamber from about 10 sccm to about 1,000 sccm, and SiH4 flow rate to the chamber from about 5 sccm to about 50 sccm during said selectively depositing.
18. The method of claim 1 wherein the selectively depositing is by chemical vapor deposition within a deposition chamber, gaseous WF6 and H2 comprising deposition precursors fed to the chamber during said selectively depositing.
19. The method of claim 18 wherein the fabricating is relative to a substrate, and comprising substrate temperature from about 250° C. to about 350° C., chamber pressure from about 1 mTorr to about 100 mTorr, WF6 flow rate to the chamber from about 10 sccm to about 1,000 sccm, and H2 flow rate to the chamber from about 5 sccm to about 50 sccm during said selectively depositing.
20. The method of claim 1 wherein the fabricating is relative to a substrate, and wherein the non-selective depositing is by chemical vapor deposition within a deposition chamber; gaseous WF6 and H2 comprising deposition precursors fed to the chamber during said non-selectively depositing; substrate temperature from about 300° C. to about 450° C., chamber pressure from about 20 Torr to about 250 Torr, WF6 flow rate to the chamber from about 100 sccm to about 500 sccm, and H2 flow rate to the chamber from about 1,000 sccm to about 30,000 sccm during said non-selectively depositing.
21. A method of fabricating integrated circuitry, comprising:
- forming a first conductive line having an elevationally outermost surface comprising copper;
- providing exposed non-conductive material laterally of the first conductive line;
- depositing first elemental tungsten directly against the copper-comprising surface along at least a majority of longitudinal length of the first conductive line, the first tungsten being deposited selectively to the first conductive line relative to the exposed non-conductive material;
- forming dielectric material elevationally over and directly against the first tungsten and forming a via through the dielectric material to the first tungsten;
- forming a conductive material directly against the first tungsten after forming the via;
- non-selectively depositing second elemental tungsten to within the via directly against the conductive material; and
- forming a second conductive line elevationally outward of and electrically coupled to the second tungsten that is within the via.
22. The method of claim 21 wherein the conductive material is formed by chemical vapor deposition of at least one of TiN and WN.
23. The method of claim 22 wherein the conductive material consists essentially of at least one of TiN and WN.
24. The method of claim 21 wherein the conductive material is formed by physical vapor deposition of elemental tungsten.
25. The method of claim 24 wherein the conductive material consists essentially of said physical vapor deposited elemental tungsten.
26. A method of fabricating integrated circuitry, comprising:
- forming a first conductive line having a planar elevationally outermost surface at least a majority of which comprises elemental copper;
- providing non-conductive material laterally of the first conductive line, the non-conductive material having a planar elevationally outermost surface that is coplanar with the planar outermost surface of the first conductive line;
- depositing first elemental tungsten directly against the copper-comprising surface along at least a majority of longitudinal length of the first conductive line, the first tungsten being deposited selectively to the first conductive line relative to the coplanar outermost surface of the non-conductive material;
- forming dielectric material elevationally over and directly against the first tungsten and the non-conductive material;
- forming a via through the dielectric material to the first tungsten;
- forming a conductive material liner within the via over sidewalls of the via, within the via directly against the first tungsten, and elevationally over the dielectric material;
- non-selectively depositing second elemental tungsten to within the via directly against the conductive material liner and elevationally over that portion of the conductive material liner that is elevationally over the dielectric material; and
- forming a second conductive line elevationally outward of and electrically coupled to the second tungsten that is within the via.
27. The method of claim 26 wherein forming the second conductive line comprises:
- removing the second tungsten and the conductive material liner back at least to expose the dielectric material; and
- depositing conductive metal material directly against the second tungsten and the liner after said removing.
Type: Application
Filed: Mar 1, 2013
Publication Date: Sep 4, 2014
Applicant: Micron Technology, Inc. (Boise, ID)
Inventor: Zailong Bian (Boise, ID)
Application Number: 13/782,213
International Classification: H01L 21/768 (20060101);