COPPER-FILLED TRENCH CONTACT FOR TRANSISTOR PERFORMANCE IMPROVEMENT
Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
The present application is a Continuation of U.S. patent application Ser. No. 13/569,150, filed on Aug. 7, 2012, which is a Divisional of U.S. patent application Ser. No. 11/396,201, filed on Mar. 30, 2006, Issued as U.S. Pat. No. 8,258,057 on Sep. 4, 2012.BACKGROUND
Embodiments of the present invention relate to the fabrication of interconnect structures in microelectronic devices. In particular, embodiments of the present invention relate to utilizing copper to form contact immediately to device formed on a semiconductor substrate.
2. State of the Art
The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the electrical components to form integrated circuits. The metallization patterns are generally referred to as “interconnects.”
One of the main issues confronting the semiconductor processing industry is that of the resistance problem in metallization layers. An industry-wide effort has undertaken to address the problem. Since the beginning, the semiconductor processing industry has relied on aluminum and aluminum alloys to serve as metallization layers. Silicon dioxide was selected as the insulator of choice although polyimide, a polymer, was used in a number of products by IBM for a number of years. With each succeeding generation of technology, the resistance problem grows. Because each generation requires that the dimensions of the semiconductor structure be reduced, the minimum line-space combination must also decrease. As the line-space combination decreases, the resistance of the semiconductor structure increases.
Copper metallurgy has been proposed as a substitute for aluminum metallurgy as a material for the metallization layers since copper exhibits greater conductivity than aluminum. Yet several problems have been encountered in the development of copper metallurgy. The main issue is the fast diffusion of copper through an insulator, such as silicon dioxide, to form an undesired copper oxide compound. Another issue is the known junction-poisoning effect of copper. These issues have led to the development of a liner to separate the copper metallization layer from the insulator.
Suitable liners include titanium nitride, tantalum nitride, tungsten silicon nitride, zirconium, hafnium, titanium, tantalum, and the like.
Because of the undesirable characteristics of copper, copper has not been used in forming the first contact that is immediate to the device. However, as devices are scaled smaller and smaller, the high resistivity characteristic of the conductive material such as tungsten that is typically used in the first contact layer is becoming more undesirable. Tungsten causes parasitic resistance in the device by introducing high resistivity and low conductivity at the first contact level, at the junction from the first contact level to other interconnection levels in the devices. Thus, there is a need for a first layer of contact directly to the device that will lower resistivity overall.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
FIGS. 3A-1-3A-3 illustrates a top view of a first contacts made to source/drains regions for the device shown in
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Certain known processes are not described or discussed in details in order to not obscure the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
Embodiments of the present invention relate to the fabrication of interconnect structures in microelectronic devices. More particularly, embodiments of the present invention disclose the use of copper (Cu) in the Front-End-Of-Line (FEOL) processing for a semiconductor device such as a transistor. As is known, a semiconductor device is typically formed buried in the semiconductor substrate. What end up being exposed are usually contact regions for interconnecting the devices to other metallization layers. Minimizing resistance from one interconnection level to the next is desired for an efficient and optimal device.
Currently, copper is not used in the FEOL processing due to the high tendency of copper to diffuse through an insulator even though copper has the desirable low resistivity and high conductivity characteristics. Copper can create copper oxide and disrupt the device. Copper can also migrate into the substrate, diffuse, and create both yield and reliability issues as it getters on dislocations or other interfaces. Because of such dangerous possibility, contacts immediately above the surface of the semiconductor substrate or the device have been formed with tungsten (W) to provide conductive interfaces or interconnection to the device while preventing the diffusion of copper into the device areas. Copper is used in many metal layers in the Back-End-Of-Line processing (e.g., dual damascene processing) to form metallization layers.
Fabrication of a semiconductor device includes two main process flows, FEOL and BEOL processes. In the FEOL process, wafer substrates are marked, STI regions are formed, e.g., by implantation, P- and N-wells are formed, e.g., by implantation, poly gate stacks are etched and formed, and source and drain regions are also formed by doping. Also, silicide layers or regions are also formed to enhance or establish conductive surfaces to the device. Also in the FEOL process, the first contact level is made to the device. The first contact levels typically include contacts to the source/drain regions and the gate electrode region (or the respective silicide surfaces). In the BEOL process, the device and the associated contacts are interconnected to metallization layers including forming the metallization and dielectric layers. Copper has been used in the BEOL process, e.g., dual damascene processing to form vias and trenches in the dielectric layers.
As mentioned, in conventional FEOL processing, tungsten is used for the first layer of contact. Embodiments of the present invention relate to forming the first layer of contact using copper. Additionally, the conventional FEOL processing has the first contacts being vertical thin lines (or pillars), referred to as “round contacts.” Embodiments of the present invention include forming the first contacts with “extended interconnect-style contacts” or “trench contacts” that have rectangular/square configurations. In one embodiment, a first contact extends the entire length of the contact region. In one embodiment, the first contact extends the entire length of the contact region and replace a a set of conventional contact pillars. For example, the first contact to a source region would extend the entire length of the source region. In other embodiments, the contact would extend only partially down the length of the contact region.
Embodiments of the present invention also pertain to using barrier layers to encapsulate the first contact that is made of copper. Embodiments of the present invention also include forming a silicide layer that can also act as a barrier layer and in some embodiments, the silicide layer is a copper silicide layer. Embodiments of the present invention also reduce contact resistance from the first contact to the device, between the first contact and the silicide layer, and between the first contact and other metallization layer above the first contact.
Embodiments of the present invention may enable better density scaling and cross-technology scaling by enabling optimal placement and alignment flexibility in interconnection positioning. Additionally, with the trench contact configuration, one device can be connected to another without going up to another metallization layer as is currently done in the art. More importantly, the copper contacts provide reduction in parasitic resistance in the device by eliminating the conventional copper-to-tungsten junction and replacing it with copper-t-copper junction from the device to the metallization layers. The resistivity reduction in the contacts and interconnection also enable more conductivity, thus, better drive current in a device. Furthermore, the extended interconnect-style contact in the first contact level improves drive current by enhancing not just vertical conductivity but also lateral conductivity since the contact extend more laterally compared to a conventional round-type contact. Thus, the conductivity to and from the device is increased, and in many cases, an increase of 30-45% drive current have been observed with devices made in according to embodiments of the present invention.
Contacts are made to the device. As referred herein, the first layer of contact refers to the contact that is made immediate to the device 200 or on the top surface of the substrate 202 or as illustrated in
In more particular, the terms wafer and substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure and layer formed above, and the terms wafer or substrate include the underlying layers containing such regions/junctions and layers that may have been formed above. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
The silicide layer 212 can be formed using a conventional method such as depositing a conductive material (e.g., using chemical vapor deposition) on the top surface of the source/drain regions 206 or the gate electrode 208 and then anneal the structure to form the silicide material. In one embodiment, the silicide layer 212 comprises any metal that is capable of reacting with silicon to form metal silicide. Examples of such metals include Ti, Ta, W, Co, Ni, Pt, Pd and alloys thereof. The silicide layer 212 may be deposited using a conventional deposition process including chemical vapor deposition, physical vapor deposition, sputtering, evaporation, chemical solution deposition, plating, and the like. To complete the silicide layer formation, the structure is annealed to convert the silicide metal layer 212 into a metal silicide. The annealing is typically done at a temperature from about 600-3000° C. An inert gas (e.g., helium, argon, and nitrogen) may be presence during the silicide annealing.
The dielectric layer 216 includes a substance that comprises a material selected from a group consisting of a polymer, a foamed polymer, a fluorinated polymer, a fluorinated-foamed polymer, an aerogel, and an insulator oxide compound. The polymer includes polyimide. The insulator oxide compound may include silicon dioxide, silicon nitride, carbon doped oxide, fluorinated silicon oxide, boron/phosphorous doped oxide, and the like. The dielectric layer 216 can be formed using a conventional method such as chemical vapor deposition, evaporation, atomic layer deposition, or chemical solution deposition.
Vias 201 may be formed into the dielectric layer 216 using methods known in the art, e.g., etching, photolithography, lithography, ion milling, laser ablation, damascene, dual damascene, and the like. The vias 201 are opening formed in the dielectric layer 216 and extending into the dielectric layer. In one embodiment, the vias 201 have a trench-like configuration or an extended interconnect-style configuration as opposed to the conventional thin vertical line via.
The barrier layer 214 is formed to prevent diffusion of the copper atoms into the dielectric layer 216. This diffusion changes the microstructure of a portion of the device 200 and causes undesired effects. The barrier layer 214 can be formed using conventional methods. The barrier layer 214 can be thin and in one embodiment, less than 100 Å. In other embodiments, barrier layer 214 is less than 20 Å, less than 15 Å, and even less than 10 Å along the sidewalls of the opening 201 and optionally, along all surfaces of the opening 201. In one embodiment, the barrier layer 214 is made of a material that can both act as a diffusion barrier for the interconnect material (such as acting as a diffusion barrier for copper and copper alloys) and act as an activation/nucleation layer for the interconnect material to form thereon (such as acting as a seed layer for the copper to form).
Materials that can be used as a barrier layer include but are not limited to ruthenium (Ru), paladium (Pd), rhodium (Rh), nickel (Ni), cobalt (Co), and platinum (Pt), titanium (Ti), tantalum (Ta), titanium nitride (TiN), TaN, WsiN, Zr, hafnium (Hf), tungsten (W), etc. A portion of the barrier layer 214 may also extend over and abut the surface of dielectric layer 216.
In one embodiment, a seed layer (not shown) is deposited on the barrier layer 214 prior to the deposition of the copper to form the first contact 220. A low-energy ion implantation can be used to form the seed layer. In one embodiment, depositing the seed layer includes depositing a copper seed layer. In one embodiment, depositing the seed layer includes depositing copper seed layer having a thickness of less than 100 Angstroms. This can be achieved using an 8×1016 ion implantation of copper. In one embodiment, the energy of implantation includes about 100 electron-volts. Additionally, the copper seed layer can also be implanted at an angle normal to the planarized surface.
The seed material may be deposited in a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process, such as magnetron sputtering, but is not so limited. The seed material provides a nucleation site for a subsequent electroless plating process for the copper. The seed material may include, but is not limited to, copper (Cu), palladium (Pd), cobalt (Co), nickel (Ni), ruthenium (Ru), platinum (Pt), alloys thereof, and the like.
In one embodiment, copper is electrolessly deposited into the via 201 to form the first contact 220. The electroless deposition process may include any autocatalytic (e.g., no external power supply is applied) deposition of the conductive material layer through the interaction of a metal salt and a chemical reducing agent. As is known in the art, preparing or treating a surface, may be necessary in order to produce an activated surface so that the surface that is receptive to the electroless deposition process.
In one embodiment, during the electroless deposition, the seed material serves as the activated surface upon which the electroless deposition forms. The seed material also acts as a region which controls the placement of the deposited copper from the electroless deposition solution only deposits on the prepared or treated surface (e.g., the seed material).
In one embodiment, the electroless plating bath or deposition solution may comprise cobalt and alloys thereof (such as cobalt alloyed with tungsten, boron, phosphorus, molybdenum, and/or the like), nickel and alloys thereof (such as nickel alloyed with tungsten, boron, phosphorus, molybdenum, and/or the like), copper, palladium, silver, gold, platinum metals and their selective alloys to fill narrow and high aspect ratio trenches and via holes. It is, of course, understood that the electroless deposition solution may also include additives (such as suppressors, polyethylene glycol, and anti-suppressors, di-sulfide) and complexing agents (such as thiosulfate and peroxodisulfate). Although a few examples of materials that may comprise the electroless deposition solution are described here, the solution may comprise other materials that serve to deposit the conductive material electroles sly. The technique of electroles sly depositing a metal or metal alloy is known to those skilled in the art, and may be performed either by immersing the substrate in an electroless deposition solution, by semi-immersion, or by spraying the electroless deposition solution onto the substrate or target (e.g., the dielectric material layer 216). It is well known to those skilled in the art that the seed material may be subsumed during the electroless deposition process, such that the seed material may become continuous with the conductive material.
In one embodiment, the contact 220 is planarized after the copper fills the vias 201, usually by a technique called chemical mechanical polish (CMP) or by an etching process, which removes the copper, which is not within the opening 201.
In one embodiment, via connector 222 are formed to electrically interconnect to the first contact 220. A conventional BEOL process can be used to form the via connector 222. For example, a dual damascene method can be used to form the via connector 222. The via connector 222 connects to the metallization layers 226, which can also be formed using similar methods. In an alternative embodiment, the copper deposited in the opening to form the first contact 220 is etched or otherwise removed in a way to leave the via connector 222 extending from the first contact 220. In one embodiment, the first contact 220 and the via connector 222 are filled simultaneously with copper. It is to be noted that dual damascene process is not the only technique that can be used to form the first contact 220 and the via connector 222. Conventional metal etching methods can be used to form the first contact 220 and the via connector 222, sequentially or simultaneously.
The via connector 222 needs not be placed entirely over the first contact 220. As shown in
The extended configuration or trench contact configuration for the first contact 220 enables flexibility in circuit design and placement of the interconnecting elements. For example, the trench contact need not run the entire length of the source drain region, and (because of the high conductivity of the contact due the Cu fill) can also extend significantly beyond the edge of the source drain region. The via connector 222 needs not be placed directly over the region of the substrate 202 where the device is formed (“field region”) but instead, can be placed toward the side where space is available and still able to interconnect to the first contact 220. Additionally, filling the trench contact with copper may be easier than filling a round via contact with copper. Furthermore, the extended first contact filled with copper reduces vertical resistivity as well as lateral resistivity; and, being filled with copper, the first contact further optimizes drive current by providing optimal vertical and lateral conductivity. In one embodiment, a device built using the extended-interconnect style first contact has a 10-15% conductivity improvement over the conventional round style first contact.
In one embodiment, (
Alternatively, the dielectric layer 418 is formed over the substrate 402 (over the top surface 410) prior to the silicide layer 416 formation. The dielectric layer 418 is then etched to form the opening 420. Then, the silicide layer 416 is formed inside each of the opening 420.
Copper is then deposited into the opening 420 to form the first contact 424. In one embodiment a seed layer is not used. In such embodiment, the barrier layer 422 is made of a material that is capable of being activated to be a nucleated site for the copper to form thereon. In one embodiment, electroless plating is used to deposit the copper. In another embodiment, electroplating is used to deposit the copper. When the device 400 is completed, at this point, the FEOL may be considered finished and the BEOL begins to form other interconnection layers to the device 400. For example, via connectors and metallization layers are formed to connect to the first contact 424 using methods known in the art.
In one embodiment, (
Embodiments of the present invention permit more flexibility in the placement of via connector and/or metalizations to a device while providing superior performance over conventional configuration of interconnection to a device. For instance, in one embodiment, (as the state of the art or conventional devices with round contacts does not even permit this configuration) a via connector such as the via connector 222 is located adjacent to the device on the adjacent field and connects to the device through the extension of a first contact such as the contact 220 onto the field. In this configuration the high conductivity of the trench contact style for the first contact provides significant performance improvement. Experimental results from devices fabricated with copper-contacts in this exemplary configuration show for NMOS up to 35% Idsat and 50% IDlin improvement, and for PMOS up to 30% Idsat and 50% IDlin improvement; when compared to conventional W processing in the same geometry. If the W processing is enhanced to the limit of the state of the art (i.e. configurations unrealistic for mass production), improvements are still seen for NMOS up to 15% Idsat and 25% IDlin improvement, and for PMOS up to 10% Idsat and 20% IDlin improvement; when compared to conventional W processing in the same geometry.
Although embodiments above focus mainly on FEOL processing, the same can be applied to BEOL processing without exceeding the scope of the embodiments of the present invention.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
1. A semiconductor device comprising:
- a semiconductor substrate having a contact region;
- a dielectric layer on a top surface of the semiconductor substrate having an opening exposing at least a portion of the contact region;
- a conductive material in the opening forming a contact to the contact region; and
- a via connector on a portion of the first contact and on a portion of the dielectric layer.
2. The semiconductor device of claim 1, further comprising a metallization layer connected to the via connector.
3. The semiconductor device of claim 2, wherein the metallization layer is over the entire via connector.
4. The semiconductor device of claim 1, wherein the opening has an opening length and an opening width wherein the opening length is greater than the opening width.
5. The semiconductor device of claim 4, wherein the opening length extends one of an entire length of the contact region, partially across the entire length of the contact region, or from the contact region onto an adjacent field of the contact region.
6. The semiconductor device of claim 1, wherein the contact region is a conductive surface on the semiconductor substrate.
7. The semiconductor device of claim 6, wherein the contact region is formed of a silicide material.
8. The semiconductor device of claim 6, wherein the contact region is a doped region of the semiconductor substrate.
9. The semiconductor device of claim 1, wherein the conductive material comprises copper.
10. The semiconductor device of claim 1, further comprising a barrier layer lining surfaces of the opening, the barrier layer comprising copper silicide.
11. A method of forming a semiconductor device, comprising:
- forming a contact region on a semiconductor substrate;
- forming a dielectric layer on a top surface of the semiconductor substrate;
- forming an opening in the dielectric layer exposing at least a portion of the contact region;
- filling the opening with a conductive material to form a first contact to the semiconductor device; and
- forming a via connector on a portion of the first contact and on a portion of the dielectric layer.
12. The method of claim 11, wherein forming the via connector comprises a dual damascene process.
13. The method of claim 12, wherein the first contact and the via connector are filled simultaneously with the conductive material.
14. The method of claim 11, wherein the conductive material is copper.
15. The method of claim 11, further comprising forming a metallization layer on a top surface of the via connector.
16. The method of claim 15, wherein forming the metallization layer and the via connector comprises a dual damascene process.
17. The method of claim 11, further comprising forming a barrier layer within the opening, wherein the barrier layer performs as a silicide layer, a diffusion barrier for copper, and a nucleation layer for copper.
18. The method of claim 17, further comprising forming a copper containing material on the barrier layer within the opening.
19. The method of claim 11, wherein filling the opening comprises an electroless deposition process.
20. The method of claim 19, further comprising performing a surface treatment to produce an activated surface.
International Classification: H01L 29/45 (20060101);