Patents by Inventor Mark Bohr

Mark Bohr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373987
    Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mark Bohr, Glenn J. Hinton, Rajesh Kumar
  • Patent number: 11373999
    Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Yih Wang, Rishabh Mehandru, Mauro J. Kobrinsky, Tahir Ghani, Mark Bohr, Marni Nabors
  • Publication number: 20220115505
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Inventors: Kelin J. KUHN, Kaizad MISTRY, Mark BOHR, Chris AUTH
  • Publication number: 20220059484
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventors: Valery M. DUBIN, Sridhar BALAKRISHNAN, Mark BOHR
  • Patent number: 11249113
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Patent number: 11201129
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Publication number: 20210210385
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: March 24, 2021
    Publication date: July 8, 2021
    Inventors: Abhijit Jayant PETHE, Tahir GHANI, Mark BOHR, Clair WEBB, Harry GOMEZ, Annalisa CAPPELLANI
  • Patent number: 11004739
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Publication number: 20210088554
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Application
    Filed: December 3, 2020
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Publication number: 20210074695
    Abstract: Techniques and mechanisms for providing interconnected circuitry of an integrated circuit (IC) die stack. In an embodiment, first integrated circuitry of a first IC die is configured to couple, via a first interconnects of the first IC die, to second integrated circuitry of a second IC die. When the first IC die and the second IC die are coupled to one another, second interconnects of the first IC die are further coupled to the second integrated circuitry, wherein the second interconnects are coupled to each of two opposite sides of the first IC die. In another embodiment, the second integrated circuitry includes processor logic, and the first integrated circuitry is configured to cache data for access by the processor logic. In another embodiment, the first integrated circuitry includes a power delivery circuit and an on-package input-output interface to cache data for access by the processor logic at higher bandwidth with lower power consumption.
    Type: Application
    Filed: December 28, 2017
    Publication date: March 11, 2021
    Inventors: Wilfred GOMES, Mark BOHR, Glenn J. HINTON, Rajesh KUMAR
  • Publication number: 20210013188
    Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Sanka Ganesan, DOUG INGERLY, ROBERT SANKMAN, MARK BOHR, DEBENDRA MALLIK
  • Patent number: 10877068
    Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Pooya Tadayon, Mark Bohr, Joe Walczyk
  • Publication number: 20200403007
    Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Nicholas THOMSON, Ayan KAR, Kalyan KOLLURU, Nathan JACK, Rui MA, Mark BOHR, Rishabh MEHANDRU, Halady Arpit RAO
  • Publication number: 20200388675
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Milton Clair WEBB, Mark BOHR, Tahir GHANI, Szuya S. LIAO
  • Patent number: 10790354
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • Publication number: 20200258852
    Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 13, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Doug INGERLY, Rajesh KUMAR, Harish KRISHNAMURTHY, Nachiket Venkappayya DESAI
  • Publication number: 20200211970
    Abstract: A method is disclosed. The method includes a plurality of semiconductor sections and an interconnection structure connecting the plurality of semiconductor sections to provide a functionally monolithic base die. The interconnection structure includes one or more bridge die to connect one or more of the plurality of semiconductor sections to one or more other semiconductor sections or a top layer interconnect structure that connects the plurality of semiconductor sections or both the one or more bridge die and the top layer interconnect structure.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Wilfred GOMES, Mark BOHR, Rajabali KODURI, Leonard NEIBERG, Altug KOKER, Swaminathan SIVAKUMAR
  • Publication number: 20200135266
    Abstract: A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Applicant: INTEL CORPORATION
    Inventors: Raghavan Kumar, Sasikanth Manipatruni, Gregory Chen, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Ian Young, Mark Bohr, Amrita Mathuriya
  • Publication number: 20200105759
    Abstract: Integrated circuit structures having asymmetric source and drain structures, and methods of fabricating integrated circuit structures having asymmetric source and drain structures, are described. For example, an integrated circuit structure includes a fin, and a gate stack over the fin. A first epitaxial source or drain structure is in a first trench in the fin at a first side of the gate stack. A second epitaxial source or drain structure is in a second trench in the fin at a second side of the gate stack, the second epitaxial source or drain structure deeper into the fin than the first epitaxial source or drain structure.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Anupama BOWONDER, Rishabh MEHANDRU, Mark BOHR, Tahir GHANI
  • Publication number: 20200058646
    Abstract: Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mark Bohr, Brian S. Doyle