At Least One Layer Of Silicide Or Polycrystalline Silicon Patents (Class 257/754)
  • Patent number: 11043414
    Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
  • Patent number: 11011467
    Abstract: A method includes depositing an etch stop layer over a non-insulator structure and a dielectric layer over the etch stop layer; etching the dielectric layer to form a first hole in the dielectric layer; deepening the first hole into the etch stop layer such that the non-insulator structure is exposed at a bottom of the deepened hole; after the non-insulator structure is exposed, performing a cleaning operation to remove etch byproducts from the deepened first hole, wherein the cleaning operation results in lateral recesses laterally extending from a bottom portion of the deepened first hole into the etch stop layer; depositing a first diffusion barrier layer into the deepened first hole until the lateral recesses are overfilled; depositing a second diffusion barrier layer over the first diffusion barrier layer; and depositing one or more conductive layers over the second diffusion barrier layer.
    Type: Grant
    Filed: August 8, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 11004804
    Abstract: In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 11, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Atsuko Sakata
  • Patent number: 10998270
    Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Glenn A. Glass, Van H. Le, Ashish Agrawal, Benjamin Chu-Kung, Anand S. Murthy, Jack T. Kavalieros
  • Patent number: 10971601
    Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10930562
    Abstract: A connection structure for microelectronic device with superposed semi-conductor layers including a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, the connection structure further including a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Fabrice Nemouchi, Maud Vinet
  • Patent number: 10665498
    Abstract: A semiconductor device, including an active region defined in a semiconductor substrate; a first contact plug on the semiconductor substrate, the first contact plug being connected to the active region; a bit line on the semiconductor substrate, the bit line being adjacent to the first contact plug; a first air gap spacer between the first contact plug and the bit line; a landing pad on the first contact plug; a blocking insulating layer on the bit line; and an air gap capping layer on the first air gap spacer, the air gap capping layer vertically overlapping the first air gap spacer, the air gap capping layer being between the blocking insulating layer and the landing pad, an upper surface of the blocking insulating layer being at a height equal to or higher than an upper surface of the landing pad.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Jung Kim, Bong-Soo Kim, Yong-Kwan Kim, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 10615252
    Abstract: A device fabricated on a wafer is disclosed. The device includes a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI. The second block includes a first vertical section coupled to a first ground, a second vertical section, a third vertical section coupled to a second ground. The second vertical section is doped lightly compared to the first vertical section and the second vertical section.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: April 7, 2020
    Assignee: NXP USA, INC.
    Inventor: Radu Mircea Secareanu
  • Patent number: 10594271
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 17, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: 10580876
    Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-hyeok Ahn, Eun-jung Kim, Hui-jung Kim, Ki-seok Lee, Bong-soo Kim, Myeong-dong Lee, Sung-hee Han, Yoo-sang Hwang
  • Patent number: 10535527
    Abstract: A method for forming a film on a substrate in a semiconductor process chamber includes forming a first layer on the substrate using a plasma enhanced process and a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas. The process chamber is then purged and the first layer is thermally soaked with a hydrogen-based precursor gas. The process chamber is then purged again and the process may be repeated with or without the plasma enhanced process until a certain film thickness is achieved on the substrate.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: January 14, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi Xu, Takashi Kuratomi, Avgerinos V. Gelatos, Vikash Banthia, Mei Chang, Kazuya Daito
  • Patent number: 10381305
    Abstract: Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one another by a first pitch. Protective knobs are formed over the conductive lines and are arranged in rows. The protective knobs within each row are spaced along a second pitch which is greater than the first pitch. The protective knobs protect regions of the conductive lines while leaving other regions of the conductive lines unprotected. The unprotected regions are recessed so that the protected regions become tall regions and the unprotected regions become short regions. The protective knobs are removed. Conductive structures are formed over the conductive lines. The conductive structures are spaced along the second pitch. Each of the conductive lines is uniquely coupled to only one of the conductive structures. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10381450
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Xiaolong Hu, Junichi Ariyoshi
  • Patent number: 10361666
    Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 23, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
  • Patent number: 10305000
    Abstract: A sacrificial layer is formed on a region for forming the reflective electrode later on the p-type layer, Subsequently, a part of the p-type layer is dry etched to expose an n-type layer. Then, a resist layer having an opening is formed through photolithography on the p-type layer and the n-type layer exposed in the previous step. The opening has a pattern to enclose the sacrificial layer in a plan view. Next, the sacrificial layer is wet etched using a buffered hydrofluoric acid to remove the entire sacrifice layer. Subsequently, a reflective film is formed by sputtering on the p-type layer and the resist layer. Next, the resist layer is removed using a resist stripper, and only the reflective film on the p-type layer is left to form the reflective electrode.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 28, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Shingo Totani
  • Patent number: 9997567
    Abstract: A semiconductor structure includes a memory structure. The memory structure includes a memory element, a first barrier layer and a second barrier layer. The memory element includes titanium oxynitride. The first barrier layer includes at least one of silicon and silicon oxide. The first barrier layer is disposed on the memory element. The second barrier layer includes at least one of titanium and titanium oxide. The second barrier layer is disposed on the first barrier layer.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: June 12, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Dai-Ying Lee, Chao-I Wu, Yu-Hsuan Lin
  • Patent number: 9972620
    Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charan V. Surisetty, Dominic J. Schepis, Kangguo Cheng, Alexander Reznicek
  • Patent number: 9882015
    Abstract: A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder between sidewall spacers of the transistor gate until after high temperature processes, such as the fabrication of raised source and drain regions, have been completed. In addition, semiconductor devices (e.g., DRAM devices and NAND flash memory devices) with transistor gates that include cobalt silicide in their conductive elements are also disclosed, as are transistors with raised source and drain regions and cobalt silicide in the transistor gates thereof. Intermediate semiconductor device structures that include transistor gates with sacrificial material or a gap between upper portions of sidewall spacers are also disclosed.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 9831183
    Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
  • Patent number: 9735204
    Abstract: Each imaging pixel provided in a solid-state imaging device includes a charge accumulation part which is a diffusion region formed in a substrate, a gate electrode formed lateral to the charge accumulation part on the substrate, an insulating film formed on the charge accumulation part, and a contact plug connected to the charge accumulation part so as to penetrate the insulating film and made of semiconductor. The contact plug is, at a lower part thereof, embedded in the insulating film, and is, at an upper part thereof, exposed through the insulating film. Silicide is formed on the upper part of the contact plug, and the charge accumulation part and the gate electrode are covered by the insulating film.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: August 15, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryota Sakaida, Nobuyoshi Takahashi, Kosaku Saeki
  • Patent number: 9691781
    Abstract: A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 27, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Kota Funayama, Toru Miwa, Hiroyuki Ogawa
  • Patent number: 9691804
    Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: June 27, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Chang Huang, Chi-Ming Lu, Jian-Ming Chen, Jung-Chih Tsao, Yao-Hsiang Liang
  • Patent number: 9449921
    Abstract: Voidless contact metal structures are provided. In one embodiment, a voidless contact metal structure is provided by first providing a first contact metal that contains a void within a contact opening. The void is then opened to provide a divot in the first contact metal. After forming a dielectric spacer atop a portion of first contact metal, a second contact metal is then formed that lacks any void. The second contact metal fills the entirety of the divot within the first contact metal. In another embodiment, two diffusion barrier structures are provided within a contact opening, followed by the formation of a contact metal structure that lacks any void.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9159652
    Abstract: An electronic device is described comprising at least one chip enclosed in a package, in turn provided with a metallic structure or leadframe having a plurality of connection pins, this chip having at least one first contact realized on a first face and at least one second contact realized on a second and opposite face of this chip. The chip comprises at least one through via crossing the whole section of the chip as well as a metallic layer extending from the second contact arranged on the first face, along walls of the at least one through via up to the second and opposite face in correspondence with an additional pad. The electronic device comprises at least one interconnection layer for the electrical and mechanical connection between the chip and the metallic structure having at least one portion realized in correspondence with the at least one through via so as to bring the second contact placed on the second face of the chip back on its first face.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: October 13, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Concetto Privitera
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 8999842
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Patent number: 8994177
    Abstract: A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Robert L. Bruce, Swetha Kamlapurkar
  • Patent number: 8987906
    Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Scott Sills
  • Patent number: 8952536
    Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: February 10, 2015
    Assignee: Spansion LLC
    Inventors: Masahiko Higashi, Hiroyuki Nansei
  • Publication number: 20150021776
    Abstract: A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Patent number: 8933566
    Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 13, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Lo Yueh Lin
  • Publication number: 20150001724
    Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Manish CHANDHOK, Hui Jae Yoo, Yan A. Borodovsky, Florian Gstrein, David N. Shykind, Kevin L. Lin
  • Patent number: 8895435
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Publication number: 20140339702
    Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Pezhman Monadgemi, Terrence Caskey
  • Patent number: 8872281
    Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Jeffrey B. Johnson, Peter J. Lindgren, Xuefeng Lie, James S. Nakos, Bradley A. Omer, Robert M. Rassel, David C. Sheridan
  • Patent number: 8866156
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Hideto Tamaso
  • Patent number: 8853862
    Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo Vega
  • Publication number: 20140284801
    Abstract: According to an embodiment, a semiconductor device, includes a substrate, an inter-layer insulating layer provided above the substrate, a first interconnect provided in a first trench, and a second interconnect provided in a second trench. The first interconnect is made of a first metal, and the first trench is provided in the inter-layer insulating layer on a side opposite to the substrate. The second interconnect is made of a second metal, and the second trench is provided in the inter-layer insulating layer toward the substrate. A width of the second trench is wider than a width of the first trench. A mean free path of electrons in the first metal is shorter than a mean free path of electrons in the second metal, and the first metal is a metal, an alloy or a metal compound, including at least one nonmagnetic element as a constituent element.
    Type: Application
    Filed: September 5, 2013
    Publication date: September 25, 2014
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI
  • Publication number: 20140264879
    Abstract: Methods of fabricating a first contact to a semiconductor device, which fundamentally comprises providing a semiconductor device formed on a substrate. The substrate further includes a conductive surface. A dielectric layer is formed over the substrate and has an opening exposing the conductive surface. The opening extends an entire length of the semiconductor device, partway down the entire length of the device, extending from the device onto adjacent field of the device, or and a combination thereof. A barrier layer is formed within the opening. A copper containing material fills the opening to form a first contact to the semiconductor device.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Inventors: Kelin J. Kuhn, Kaizad Mistry, Mark Bohr, Chris Auth
  • Patent number: 8822995
    Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chun-Gi You, Kap-Soo Yoon, Gug-Rae Jo, Sung-Hoon Yang, Ki-Hun Jeong, Seung-Hwan Shim, Jae-Ho Choi
  • Publication number: 20140225264
    Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.
    Type: Application
    Filed: April 22, 2014
    Publication date: August 14, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej Sandhu, Scott Sills
  • Patent number: 8796855
    Abstract: An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Michael B. McShane, Tab A. Stephens
  • Patent number: 8778795
    Abstract: In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: July 15, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ronny Pfuetzner, Jens Heinrich
  • Patent number: 8766236
    Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Tsutomu Tezuka
  • Publication number: 20140175653
    Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Nishant Sinha, John A. Smythe
  • Patent number: 8710553
    Abstract: An integrated circuit includes a substrate. The substrate includes diffusion lines. The diffusion lines include impurities diffused into the substrate. A signal line layer includes first signal lines. A first metal layer includes second signal lines. The second signal lines include a first metallic material. A second metal layer includes third signal lines. The third signal lines include a second metallic material. First contacts connect the diffusion lines to (i) a first set of the second signal lines, or (ii) a first set of the third signal lines. Second contacts connect a first set of the first signal lines to a second set of the third signal lines. Each signal line in a first set of the second signal lines includes first portions and second portions. The first portions extend towards and are not connected to the second contacts. The first portions are not parallel to the second portions.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Publication number: 20140097541
    Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Lo Yueh LIN
  • Patent number: 8692373
    Abstract: A method of forming a metal silicide region. The method comprises forming a metal material over and in contact with exposed surfaces of a dielectric material and silicon structures protruding from the dielectric material. A capping material is formed over and in contact with the metal material. The silicon structures are exposed to heat to effectuate a multidirectional diffusion of the metal material into the silicon structures to form a first metal silicide material. The capping material and unreacted portions of the metal material are removed. The silicon structures are exposed to heat to substantially convert the first metal silicide material into a second metal silicide material. A method of semiconductor device fabrication, an array of silicon structures, and a semiconductor device structure are also described.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Carla Maria Lazzari, Enrico Bellandi
  • Patent number: 8669608
    Abstract: According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuru Sato, Megumi Ishiduki, Masaru Kidoh, Atsushi Konno, Yoshihiro Akutsu, Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata
  • Patent number: 8664761
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a plurality of stacked structures and a plurality of contact structures. Each of the stacked structures includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. Each of the contact structures is electrically connected to each of the stacked structures. The contact structure includes a first conductive pillar, a dielectric material layer, a metal silicide layer, and a second conductive pillar. The dielectric material layer surrounds the lateral surface of the first conductive pillar. The metal silicide layer is formed on an upper surface of the first conductive pillar. The second conductive pillar is formed on the metal silicide layer. The upper surfaces of the first conductive pillars are coplanar.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh