An Integrated Structure with a Silicon-Through Via
An integrated structure with a silicon-through via comprises a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.
The present invention relates to an integrated structure with a silicon-through via.
BACKGROUND OF THE INVENTIONTo save precious layout space or increase interconnection efficiency, multiple chips of integrated circuits (ICs) can be stacked together as a single IC package. To that end, a three-dimensional (3D) stack packaging technology is used to package the chips of integrated circuits. Through-silicon vias (TSVs) are widely used to accomplish the 3D stack packaging technology. A through-silicon via is a vertical conductive via completely passing through a silicon wafer, a silicon board, a substrate of any material or die. Nowadays, a 3D integrated circuit (3D IC) is applied to a lot of fields such as memory stacks, image sensors or the like.
Compared to a single transistor or a single interconnect metal line, a through-silicon via comes with a size of hundred fold or more. To share the same manufacturing process with integrated circuits would mean difficulties to control process uniformity and/or keep process window. Furthermore, the gigantic TSVs would produce mechanical stress and electrical interference affecting the devices around them. Hence, there is a need to completely eliminate or at least reduce this issue.
SUMMARY OF THE INVENTIONIn one embodiment of the present invention, an integrated structure with a silicon-through via is provided to comprise a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.
In another embodiment of the present invention, an integrated structure with a silicon-through via is provided to comprise a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second alignment marks with different shapes disposed between the through-silicon via and the conductive protective structure.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
The following is the detailed description of the preferred embodiments of this invention. All the elements, sub-elements, structures, materials, arrangements recited herein can be combined in any way and in any order into new embodiments, and these new embodiments should fall in the scope of this invention defined by the appended claims. A person skilled in the art, upon reading this invention, should be able to modify and change the elements, sub-elements, structures, materials, arrangements recited herein without being apart from the principle and spirit of this invention. Therefore, these modifications and changes should fall in the scope of this invention defined only by the following claims.
There are a lot of embodiments and figures in this application. To avoid confusions, similar components are represented by same or similar numerals. To avoid complexity and confusions, only one of the repetitive components is marked. Figures are meant to deliver the principle and spirits of this invention, so the distance, size, ratio, shape, connection relationship, etc. are examples instead of realities. Other distance, size, ratio, shape, connection relationship, etc. capable of achieving the same functions or results can be adopted as equivalents.
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Aside from the mechanical stress and electrical interference caused by the TSV 1000, its gigantic size would also induce non-uniformity in thickness, in critical dimension (CD) and in profile after some processes sensitive to pattern density/pattern distribution such as etching processes and chemical mechanical polishing (CMP) processes. For overcoming these process difficulties, dummy patterns 200 and 300 with different shapes are introduced between the empty space between the protective structure 200 and the TSV 1000. The size and shape of the dummy patterns 200 and 300 need not to be limited. Although only two kinds of dummy patterns (that is 200 and 300) are shown in
In most of the integrated circuit (IC) manufacturing processes, mass amount of alignment marks are needed for photolithography process, defect inspections . . . etc. These marks are usually space demanding and contributes nothings to the electrical functions. In the present invention, some of these marks such as alignment marks 500 and 600 may be disposed around the TSV 1000 and the protective structure 200 to save space. The shapes, sizes and functions of these marks are not limited as long as they can perform the functions they supposed to perform.
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The TSV 1000 shown in
Disposed around the TSV 1000 is the inter-layer dielectric layer 150. Inter-layer dielectric layer 150 may be a single-layered or multi-layered structure comprising one or more dielectric material selected from silicon dioxide, silicon nitride, SiC, SiON, SiCN, TEOS-based silicon dioxide, low-k dielectric materials . . . etc. As shown in
Disposed above the TSV 1000, inter-layer dielectric layer 150, protective structure 200, marks 500 and 600, and dummy patterns 300 and 400 is a interconnect layer 900. Interconnect layer 900 represents all the inter-metal dielectric layers and all the interconnect structures embedded within. It should be understood,
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In this way, the present invention manages to isolate the TSV from the active devices in order to reduce the impacts caused by TSV on the active devices. The present invention also manages to make good use of the space around TSV and keep good process uniformity by adding marks and dummy patterns around TSV.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims
1. An integrated structure with a silicon-through via, comprising:
- a substrate;
- a through-silicon via penetrating the substrate;
- a conductive protective structure surrounding the through-silicon via; and
- a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.
2. The integrated structure of claim 1, wherein the conductive protective structure, the first and the second conductive dummy patterns are disposed within the same dielectric layer.
3. The integrated structure of claim 1, wherein the conductive protective structure, the first and the second conductive dummy patterns are disposed within different dielectric layers.
4. The integrated structure of claim 1, wherein the conductive protective structure has a rectangle or square shape.
5. The integrated structure of claim 4, wherein the first and the second conductive dummy patterns are disposed at different corners of the conductive protective structure.
6. The integrated structure of claim 1, further comprising an alignment mark disposed between the conductive protective structure and the through-silicon via.
7. The integrated structure of claim 6, wherein the conductive protective structure and the alignment mark are disposed within the same dielectric layer.
8. The integrated structure of claim 6, wherein the conductive protective structure and the alignment mark are disposed within different dielectric layers.
9. The integrated structure of claim 6, wherein the conductive protective structure has a rectangle or square shape and the alignment mark is disposed at a corner of the conductive protective structure.
10. The integrated structure of claim 6, wherein the alignment mark is configured for photolithography or defect inspection.
11. An integrated structure with a silicon-through via, comprising:
- a substrate;
- a through-silicon via penetrating the substrate;
- a conductive protective structure surrounding the through-silicon via; and
- a first and a second alignment marks with different shapes disposed between the through-silicon via and the conductive protective structure.
12. The integrated structure of claim 11, wherein the conductive protective structure, the first and the second alignment marks are disposed within the same dielectric layer.
13. The integrated structure of claim 11, wherein the conductive protective structure, the first and the second alignment marks are disposed within different dielectric layers.
14. The integrated structure of claim 11, wherein the conductive protective structure has a rectangle or square shape.
15. The integrated structure of claim 14, wherein the first and the second alignment marks are disposed at different corners of the conductive protective structure.
16. The integrated structure of claim 11, further comprising a conductive dummy pattern disposed between the conductive protective structure and the through-silicon via.
17. The integrated structure of claim 16, wherein the conductive protective structure and the conductive dummy pattern are disposed within the same dielectric layer.
18. The integrated structure of claim 16, wherein the conductive protective structure and the conductive dummy pattern are disposed within different dielectric layers.
19. The integrated structure of claim 16, wherein the conductive protective structure has a rectangle or square shape and the conductive dummy pattern is disposed at a corner of the conductive protective structure.
20. The integrated structure of claim 11, wherein the alignment mark is configured for photolithography or defect inspection.
Type: Application
Filed: Mar 15, 2013
Publication Date: Sep 18, 2014
Patent Grant number: 8957504
Inventors: Huang Chao-Yuan (Hsinchu City), Ho Yueh-Feng (Hsinchu City), Yang Ming-Sheng (Hsinchu City), Chen Hwi-Huang (Hsinchu City)
Application Number: 13/833,786
International Classification: H01L 23/48 (20060101);