Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

Abstract: A semiconductor structure includes a gate structure over a substrate. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the source/drain epitaxial structure. The structure also includes a first via structure formed over the contact structure. The structure also includes a metal line electrically connected to the first via structure. The structure also includes a spacer layer formed over the sidewall and over a portion of a top surface of the metal line. The structure also includes a second via structure formed over the metal line through the spacer layer.

Abstract: Embodiments of the invention are directed to an integrated circuit. A non-limiting example of the integrated circuit includes a transistor formed over a substrate. A dielectric region is formed over the transistor and the substrate. A trench is positioned in the dielectric region and over a S/D region of the transistor. A first liner and a conductive plug are within the trench such that the first liner and the conductive plug are only present within a bottom portion of the trench. A substantially oxygen-free replacement liner and a S/D contact are within the top portion of the trench such that a bottom contact surface of the S/D contact directly couples to a top surface of the conductive plug.

Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes a functional circuit structure and a seal ring structure embedded in an insulating layer. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure, the seal ring structure includes a stack of alternating interconnect layers and via patterns, the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the insulating layer, and the first features are offset lengthwise relative to each other to overlap therewith, and the first features are spaced apart widthwise relative to each other.

Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip and a connection structure. The second semiconductor chip includes a first segment that protrudes outwardly beyond one side of the first semiconductor chip and a second connection pad on a bottom surface of the first segment of the second semiconductor chip. The connection structure includes a first structure between the substrate and the first segment of the second semiconductor chip and a first columnar conductor penetrating the first structure to be in contact with the substrate and being disposed between the second connection pad and the substrate, thereby electrically connecting the second semiconductor chip to the substrate.

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the at least one first bonding pad.

Abstract: Embodiments disclosed herein include edge placement error mitigation processes and structures fabricated with such processes. In an embodiment, a method of fabricating an interconnect layer over a semiconductor die comprises forming a patterned layer over a substrate, disposing a resist layer over the patterned layer and patterning the resist layer to expose portions of the patterned layer. In an embodiment, overlay misalignment during the patterning results in the formation of edge placement error openings. In an embodiment, the method further comprises correcting the edge placement error openings, and patterning an opening into the substrate after correcting edge placement error openings.

Abstract: A sensor unit includes a transducer element monitoring a measurand and generating an electrical output signal correlated with the measurand, a sensor substrate having a first surface and an opposite second surface, a recess extending from the first surface of the substrate through to the second surface of the substrate, and a circuit carrier. The transducer element and a first electrically conductive contact pad are arranged on the first surface and electrically connected. The circuit carrier has a second electrically conductive contact pad. The sensor substrate is mounted on the circuit carrier with the first surface facing the circuit carrier. The first electrically conductive contact pad and the second electrically conductive contact pad are interconnected by an electrically conductive material filled in from the second surface towards the first surface of the sensor substrate.

Abstract: A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.

Abstract: Curable material layer is coated on surface of first die. First die includes first substrate and first contact pad. Second die is bonded to first die. Second die includes second substrate and second contact pad. Second contact pad is located on second substrate, at an active surface of second die. Bonding the second die to the first die includes disposing second die with the active surface closer to the curable material layer and curing the curable material layer. A through die hole is etched in the second substrate from a backside surface of the second substrate opposite to the active surface. The through die hole further extends through the cured material layer, is encircled by the second contact pad, and exposes the first contact pad. A conductive material is disposed in the through die hole. The conductive material electrically connects the first contact pad to the second contact pad.

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

Abstract: According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.

Abstract: A semiconductor package includes a first sub-package and a second sub-package. The first sub-package is stacked atop the second sub-package. Each of the first sub-package and the second sub-package includes at least two first semiconductor dies, a second semiconductor die, a plurality of molding pieces, a bond-pad layer, a plurality of redistribution layers (RDLs) and a plurality of bumps. The bumps of the first sub-package are attached to the bond-pad layer of the second sub-package.

Abstract: A method of forming a semiconductor structure includes following steps. A first substrate and a second substrate are bonded together, in which the first substrate has a landing pad. The second substrate is etched to form an opening, in which the landing pad is exposed through the opening. A metal layer is formed over the landing pad and a sidewall of the second substrate that surrounds the opening. A buffer structure is formed over the metal layer. The buffer structure is etched such that a top surface of the buffer structure is below a top surface of the metal layer. A barrier structure is formed over metal layer and the buffer structure.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.

Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

Abstract: An antenna assembly includes an antenna and a heatsink. The antenna may be configured to support radio communications and generate heat, and may include a forward antenna surface configured to transmit or receive communications signals and a rear antenna surface that is affixed to a substrate. The heatsink structure may be positioned to be within a forward electromagnetic field that is emitted from the forward antenna surface and away from the rear antenna surface. The heatsink structure may be configured to perform a convection operation between the antenna and a fluid to perform thermal dissipation of the heat from the antenna.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Abstract: Some examples described herein relate to packet identification (ID) assignment for a routing network in a programmable integrated circuit (IC). In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to construct an interference graph based on routes of logical nets through switches in a routing network, and assign identifications to the routes comprising performing vertex coloring of vertices of the interference graph. The interference graph includes the vertices and interference edges. Each vertex represents one of the logical nets having a route. Each interference edge connects two vertices that represent corresponding two logical nets that have routes that share at least one port of a switch. The identifications correspond to values assigned to the vertices by the vertex coloring.

Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

Abstract: Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole.

Abstract: A method is provided and includes forming a first conductive pattern; forming a photosensitive layer on the first conductive pattern, the photosensitive layer having a first through hole exposing a portion of the first conductive pattern; forming a first via in the first through hole; removing the photosensitive layer; forming a dielectric layer encapsulating the first conductive pattern and the first via, the dielectric layer exposing a top surface of the first via; forming a second conductive pattern on the top surface of the first via, forming a dielectric layer covering the second conductive pattern; etching the dielectric layer to form a second through hole that exposes a portion of the second conductive pattern; forming a second via filling the second through hole and an under bump pad on the second via; and mounting a semiconductor chip on the under bump pad using a connection terminal.

Abstract: A vertical memory device is provided including a first structure on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of a respective one of the layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and electrically connects with a pad pattern of one of the layers. The first contact plug is electrically insulated from gate patterns of other layers. At least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A semiconductor package includes an interposer, a die, a protective layer, a plurality of first electrical connectors and a first molding material. The die includes a first surface and a second surface opposite to the first surface, and the die is bonded to the interposer through the first surface. The protective layer is disposed on the second surface of the die. The first electrical connectors are disposed aside the die. The first molding material is disposed aside the die, the protection layer and the first electrical connectors.

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

Abstract: A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.

Abstract: A semiconductor package provided herein includes a first semiconductor die, a second semiconductor die and an insulating encapsulation. The second semiconductor die is stacked on the first semiconductor die. The insulating encapsulation laterally surrounds the first semiconductor die and the second semiconductor die in a one-piece form, and has a first sidewall and a second sidewall respectively adjacent to the first semiconductor die and the second semiconductor die. The first sidewall keeps a lateral distance from the second sidewall.

Abstract: A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures.

Abstract: A method of manufacturing an integrated electronic device including a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A hole is formed extending into the frontal surface and through the frontal dielectric layer. A conductive region is formed in the hole. A barrier layer is formed in the hole and extends into the hole. A first coating layer covers a top and sides of a redistribution region of the conductive region and a second coating layer covers is formed covering the first coating layer. A capillary opening is formed extending into the first and second coating layers to the barrier layer. A cavity is formed between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure by passing an aqueous solution through the capillary opening.

Abstract: Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a first substrate, and a first circuit layer positioned on the first substrate, a first redistribution structure positioned on the first circuit layer, and a second semiconductor structure including a second circuit layer positioned on the first redistribution structure, and a second substrate positioned on the second circuit layer. A layout of the first circuit layer and a layout of the second circuit layer are substantially the same and the first redistribution structure is electrically coupled to the first semiconductor structure and the second semiconductor structure.

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

Abstract: A method includes providing a carrier, mounting a plurality of semiconductor dies on the carrier, forming a region of electrically insulating encapsulant material on the carrier that covers each of the semiconductor dies, removing sections of the encapsulant material to form gaps in the region of electrically insulating encapsulant material between each of the semiconductor dies, forming electrically conductive material within the gaps, and singulating the region of electrically insulating encapsulant material along each of the gaps to form a plurality of discrete encapsulant bodies. Each of the packaged semiconductor devices comprises a sidewall-facing terminal that is disposed on a sidewall of the encapsulant body. For each of the packaged semiconductor devices the sidewall-facing terminal is electrically connected to the semiconductor die of the respective packaged semiconductor device.

Abstract: A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

Abstract: An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.

Abstract: A substrate includes an etching target film as a target of etching and a first film. The first film is formed on the etching target film and is made of a material having an etching rate smaller than an etching rate of the etching target film. The first film has multiple first openings formed at a first distance therebetween in one direction of a surface of the first film. The first film has a second opening formed at an outside of the multiple first openings in the one direction while being spaced apart from an outermost one of the first openings by a second distance equivalent to the first distance. The second opening has a width larger than a width of the first openings and a depth smaller than a depth of the first openings.

Abstract: A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure laterally surrounding the first conductive structure; and an underfill material, partially surrounding the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the underfill material.