Via (interconnection Hole) Shape Patents (Class 257/774)
  • Patent number: 11362037
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11362018
    Abstract: Apparatuses and methods are disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Deepak C. Pandey, Haitao Liu, Chandra Mouli
  • Patent number: 11355380
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits in and on the first level, where the control circuits include first single crystal transistors, where the control circuits include at least two metal layers; forming at least one second level disposed on top of the first level; performing a first etch step within the second level; forming at least one third level disposed on top of the at least one second level; performing a second etch step within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the first memory cells include second transistors, and where the second memory cells include third transistors.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 7, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11355385
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: June 7, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11355461
    Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
  • Patent number: 11355421
    Abstract: A semiconductor device that includes a through hole forming region, an insulating wall, a semiconductor substrate, a side wall insulating film, and an electric conductor. The insulating wall has an inner peripheral surface surrounding the through hole forming region. The semiconductor substrate has the insulating wall buried in one of surfaces thereof. The semiconductor substrate has a through hole whose side wall is provided outwardly from the inner peripheral surface of the insulating wall. The side wall insulating film covers the side wall of the through hole and the inner peripheral surface of the insulating wall. The electric conductor is provided in the through hole of the semiconductor substrate via the side wall insulating film.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 7, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Toshiaki Shiraiwa
  • Patent number: 11348887
    Abstract: A radio-frequency module includes: a module substrate having first and second main surfaces; a semiconductor IC having third and fourth main surfaces and mounted on the first main surface with the third main surface between the module substrate and the fourth main surface; and first and second electrodes extending perpendicularly to the first main surface. The cross-sectional area of the second electrodes is smaller than the cross-sectional area of the first electrodes. The semiconductor IC viewed in plan has first and second sides parallel to each other and third and fourth sides parallel to each other. The first electrodes are distributed over a first region between the first side and a side facing the first side and a second region between the second side and a side facing the second side. The second electrodes are in a third region between the third side and a side facing the third side.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 31, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yusuke Naniwa, Hideki Muto
  • Patent number: 11348909
    Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Maruti Gupta Hyde, Nageen Himayat, Linda Hurd, Min Suet Lim, Van Le, Gayathri Jeganmohan, Ankitha Chandran
  • Patent number: 11348897
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
  • Patent number: 11348874
    Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chin-Liang Chen, Jiun-Yi Wu, Yen-Ping Wang
  • Patent number: 11348952
    Abstract: Embodiments of the present provide a connection structure and a manufacturing thereof, an array substrate and a manufacturing method thereof, the manufacturing method of the connection structure includes: forming a first insulating layer on a base substrate forming a mask layer having a first opening on a side of the first insulating layer away from the base substrate; forming a second insulating layer op a side of the mask layer away-from the first insulating layer; forming a second opening exposing the first opening in the second insulating layer by one patterning process, and forming a third opening in the first insulating layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 31, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Zhang, Pengyu Liao
  • Patent number: 11342224
    Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Han Chen, Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 11335665
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
  • Patent number: 11335593
    Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Jhih Shen, Yi-Wei Chiu, Hung Jui Chang
  • Patent number: 11329015
    Abstract: A semiconductor device package includes an emitting device and a first building-up circuit. The emitting device defines a cavity in the emitting device. The first building-up circuit is disposed on the emitting device.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Meng-Wei Hsieh
  • Patent number: 11329004
    Abstract: A semiconductor package includes a connection structure having including a plurality of insulating layers and redistribution layers on the plurality of insulating layers. A semiconductor chip has connection pads connected to the redistribution layers, and an encapsulant encapsulates the semiconductor chip. A passive component is embedded in the connection structure and has connection terminals connected to the redistribution layer. The redistribution layers include a plurality of redistribution patterns, each disposed on the plurality of insulating layers and a plurality of redistribution vias each penetrating through the plurality of insulating layers and connected to the plurality of redistribution patterns. The plurality of redistribution vias include a plurality of blocking vias arranged to surround the passive component, and the plurality of redistribution patterns include a blocking pattern connected to adjacent blocking vias.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jieun Park
  • Patent number: 11329149
    Abstract: There are provided a vertical semiconductor device, a method of manufacturing the same, and an electronic device including the same.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 10, 2022
    Assignee: Institute of Microelectronics, The Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11322480
    Abstract: A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 3, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Toshihiro Suzuki, Yuji Nagai
  • Patent number: 11322453
    Abstract: A semiconductor package includes a die, through insulator vias, an encapsulant, and a pair of metallization layers. The through insulator vias are disposed beside the die. The encapsulant wraps the die and the through insulator vias. The pair of metallization layers is disposed on opposite sides of the encapsulant. One end of each through insulator via contacts one of the metallization layers and the other end of each through insulator via contacts the other metallization layer. The through insulator vias form at least one photonic crystal structure. A pair of the through insulator vias is separated along a first direction by a channel filled by the encapsulant. A width of the channel along the first direction is larger than a pitch of the photonic crystal structure along the first direction.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sen-Kuei Hsu
  • Patent number: 11322477
    Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11322389
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 3, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11316003
    Abstract: Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: April 26, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xue Dong, Guangcai Yuan, Haixu Li, Zhanfeng Cao, Ke Wang, Zhijun Lv, Fei Wang, Huijuan Wang, Zhiwei Liang, Xinhong Lu
  • Patent number: 11309352
    Abstract: A radio frequency (RF) front-end (RFFE) device includes a die having a front-side dielectric layer on an active device. The active device is on a first substrate. The RFFE device also includes a microelectromechanical system (MEMS) device. The MEMS device is integrated on the die at a different layer than the active device. The MEMS device includes a cap layer composed of a cavity in the front-side dielectric layer of the die. The cavity in the front-side dielectric layer is between the first substrate and a second substrate. The cap is coupled to the front-side dielectric layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Stephen Alan Fanelli, Yun Han Chu
  • Patent number: 11310906
    Abstract: A printed circuit board and a display device are provided. A second wiring layer of the PCB includes a trace group, a system ground and an output pin group that includes power supply pins and a reference ground pin. One end of the power trace of the trace group is connected to one power supply pin, and another end of the power trace extends toward the system ground line. The insulating layer has a via hole corresponding to an overlapping portion of the power trace and the positive power supply signal line. The reference ground trace is disposed between the two power traces. The reference ground trace is between the reference ground pin and the system ground line. Voltage on the reference ground pin is stable to provide a stable power supply voltage. The ripple of the power supply voltage is reduced. The electromagnetic interference resistance is strong.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 19, 2022
    Assignee: TCL China Star Ovtoelectronics Technology Co., Ltd.
    Inventor: Jianfeng Xiao
  • Patent number: 11309225
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a conductive terminal. The RDL structure is disposed on and electrically connected to the die. The TIV is laterally aside the die and extends to contact a bottom surface and a sidewall of a redistribution layer of the RDL structure. The conductive terminal is electrically connected to the die through the RDL structure and the TIV.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Patent number: 11309242
    Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 11309285
    Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo, Mark E. Tuttle
  • Patent number: 11309255
    Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 19, 2022
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
  • Patent number: 11302673
    Abstract: A semiconductor device is disclosed including one or more stacks of semiconductor dies vertically molded together in an encapsulated block. The semiconductor dies may comprise memory dies, or memory dies and a controller die.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xuyi Yang, Cong Zhang, Chin-Tien Chiu
  • Patent number: 11302571
    Abstract: A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Somnath Ghosh, Hsueh-Chung Chen, Yongan Xu, Jr., Yann Mignot, Lawrence A. Clevenger
  • Patent number: 11296673
    Abstract: A component (B) comprising a carrier (TR), on which a functional structure (FS) is covered by a thin-layer covering (DSA) spanning across and resting on the carrier. On a planarization layer arranged above the thin-layer covering (DSA), a wiring level (M1, M2) is realized, which comprises structured conductor paths and which is connected via through-connections to the functional structure (FS).
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: April 5, 2022
    Assignee: SnapTrack, Inc.
    Inventors: Thomas Metzger, Akifumi Kamijima
  • Patent number: 11295998
    Abstract: Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Stephen Christianson, Stephen Hall, Emile Davies-Venn, Dong-Ho Han, Kemal Aygun, Konika Ganguly, Jun Liao, M. Reza Zamani, Cory Mason, Kirankumar Kamisetty
  • Patent number: 11295957
    Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, a RDL structure, an underfill layer, a protection layer, and a cap. The TIV is aside the die. The encapsulant laterally encapsulates the die and the TIV. The RDL structure is electrically connected to the die. The underfill layer is disposed between the die and the RDL structure and laterally encapsulated by the encapsulant. The protection layer is overlying the die and the encapsulant. The cap covers a top surface of the TIV and laterally aside the protection layer. A top surface of the cap is higher than a top surface of the encapsulant and lower than a top surface of the protection layer.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 11296020
    Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: April 5, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hitoshi Okano, Hiroyuki Kawashima
  • Patent number: 11296198
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Patent number: 11289492
    Abstract: A semiconductor structure includes a substrate and a bit line. The substrate has a plurality of active areas and isolation areas. Each isolation area is located between immediately-adjacent two of the active areas to isolate the active areas from each other. The first bit line is formed on a first active area of the active areas. A bottom portion of the first bit line extends within the first active area. The extending bottom portion is surrounded by the first active area.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 29, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Yu-Ting Lin
  • Patent number: 11289450
    Abstract: A semiconductor structure includes a substrate; a first die, disposed over the substrate, wherein the first die includes a first die dielectric layer, and a first die substrate disposed on the first die dielectric layer; a second die, disposed over the first die and vertically overlapping the first die; an inter-die structure, disposed between and separating the first die and the second die; and a first through via, penetrating the first die substrate and protruding from a top surface and a bottom surface of the first die substrate, wherein a top of the first through via is disposed in the inter-die structure and a bottom of the first through via is disposed in the first die dielectric layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Sung-Feng Yeh
  • Patent number: 11289407
    Abstract: A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 29, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Chun-Yi Wu
  • Patent number: 11289426
    Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
  • Patent number: 11289364
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 29, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11282859
    Abstract: The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T1, a second thickness T2, and t a third thickness T3, respectively. The second thickness is greater than the first thickness and the third thickness.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11282768
    Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth C. K. Cheng, Koichi Motoyama, Brent A. Anderson, Joseph F. Maniscalco
  • Patent number: 11282869
    Abstract: The preset disclosure provides a display panel and a display device. The display panel includes: a first substrate; a first bonding electrode which is located on a first surface of the first substrate facing a light-outgoing direction of the display panel and is located at an edge outside a display area of the display panel.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 22, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinhui Cheng, Wei Zhang, Zhankun Meng, Neng He, Xuecheng Huo, Hengyu Yan
  • Patent number: 11282761
    Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Yu-Min Liang
  • Patent number: 11276670
    Abstract: A semiconductor device includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a semiconductor substrate and a dielectric layer disposed on a top surface of the semiconductor substrate. The second integrated circuit is disposed on the dielectric layer of the first integrated circuit and includes a dummy opening extending through the second integrated circuit and having a metal layer covering the inner walls of the dummy opening and in contact with the dielectric layer, wherein the metal layer is electrically grounded or electrically floating.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chuan Teng, Victor Chiang Liang, Jung-Kuo Tu, Ching-Kai Shen
  • Patent number: 11271104
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a gate structure over a substrate and between a source region and a drain region. A composite etch stop structure is formed over the gate structure and a first inter-level dielectric (ILD) layer is formed over the composite etch stop structure. The composite etch stop structure has a plurality of stacked dielectric materials. The first ILD layer is etched to concurrently define contact openings extending to the substrate and a field plate opening extending to the composite etch stop structure. The contact openings and the field plate opening are concurrently filled with one or more conductive materials.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 11267076
    Abstract: A semiconductor device, including a semiconductor element, and a first wiring member and a second wiring member bonded to each other and being electrically connected to the semiconductor element. The first wiring member has an irradiation area for receiving irradiation of a laser beam. The semiconductor device also includes a protection member disposed on an area of the second wiring member opposite the irradiation area of the first wiring member, the protection member having a melting point higher than a melting point of at least one of the first wiring member and the second wiring member including the area on which the protection member is disposed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryoji Okumoto
  • Patent number: 11270910
    Abstract: An interconnect structure and techniques for fabrication thereof having a partial sidewall liner are provided. In one aspect, the interconnect structure includes: a substrate; a dielectric disposed on the substrate having at least one feature present therein; a barrier layer lining the at least one feature; a seed enhancement liner disposed over the barrier layer along sidewalls of the at least one feature, wherein the seed enhancement liner is present along only a middle portion of the sidewalls of the at least one feature; and at least one interconnect disposed within the at least one feature over the barrier layer and the seed enhancement liner.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten
  • Patent number: 11270943
    Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Flavio Griggio, Philip Yashar, Anthony V. Mule, Gopinath Trichy, Gokul Malyavanatham
  • Patent number: 11264236
    Abstract: A substrate processing method includes: providing a substrate having a pattern formed on a surface layer thereof; setting a temperature of the substrate such that a change in the pattern becomes a predetermined change amount; forming a reaction layer having a thickness corresponding to the temperature set in the setting on the surface layer of the substrate; and applying energy to the substrate formed with the reaction layer thereby removing the reaction layer from the surface layer of the substrate.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Takayuki Katsunuma, Shinya Ishikawa, Yoshihide Kihara, Masanobu Honda