Via (interconnection Hole) Shape Patents (Class 257/774)
  • Patent number: 11929563
    Abstract: A substrate-integrated dielectric resonator contains a substrate layer with a first dielectric constant, a plurality of dielectric vias, and a plurality of second vias. Each dielectric via includes a first via-hole extending through the substrate layer, and a dielectric material with a second dielectric constant contained within the first via-hole. Each second via has a second via-hole extending through the substrate layer and filled with gas. A dielectric resonator antenna containing a substrate-integrated dielectric resonator and a method of fabricating the same is also disclosed. By skillfully arranging second vias inside the DRA, the resonant frequencies of different modes can be controlled, and a wide impedance band-width with stable radiation performance can be achieved.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: March 12, 2024
    Assignee: City University of Hong Kong
    Inventors: Kwok Wa Leung, Hauke Ingolf Kremer, Wai Ki Lee
  • Patent number: 11923342
    Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanguk Han, Chajea Jo, Hyoeun Kim, Sunkyoung Seo
  • Patent number: 11911839
    Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: February 27, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Rahul Agarwal, Raja Swaminathan, Brett P. Wilkerson
  • Patent number: 11908798
    Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Kyu Han, Myeongsoo Lee, Rakhwan Kim, Woojin Jang
  • Patent number: 11910599
    Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: February 20, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhongwang Sun, Guangji Li, Kun Zhang, Ming Hu, Jiwei Cheng, Shijin Luo, Kun Bao, Zhiliang Xia
  • Patent number: 11910611
    Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hoon Jang, Woo Sung Yang, Joon Sung Lim, Sung Min Hwang
  • Patent number: 11908791
    Abstract: A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sagarika Mukesh, Nicholas Anthony Lanzillo
  • Patent number: 11901303
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11901336
    Abstract: A semiconductor package includes a first semiconductor chip including a first wiring layer including a first wiring structure and providing a first rear surface, and a first through via for first through via for power electrically connected to the first wiring structure; and a second semiconductor chip including a second wiring layer including a second wiring structure and providing a second rear surface, and a second through via for second through via for power electrically connected to the second wiring structure, wherein the first and second semiconductor chips have different widths, wherein the first semiconductor chip receives power through the first wiring structure and the first through via for first through via for power, wherein the second semiconductor chip receives power through the second wiring structure and the second through via for second through via for power.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuekjae Lee, Dae-woo Kim, Eunseok Song
  • Patent number: 11901318
    Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: February 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Aaron Chen, Chi Ren, Yi Hsin Liu
  • Patent number: 11901644
    Abstract: A ground plane, at least one composite antenna, and a power feeding line configured to supply power to the at least one composite antenna are provided in or on a substrate. The composite antenna includes a power feeding element configuring a patch antenna together with the ground plane, and at least one linear antenna configured to flow an electric current having a component in a vertical direction with respect to the ground plane. The power feeding line includes a main line connected to the power feeding element, and a branch line branched from the main line and connected to the linear antenna.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: February 13, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hideki Ueda
  • Patent number: 11901322
    Abstract: A semiconductor chip packaging method includes forming a bump on a wafer, forming a coating film covering the bump, laser grooving the wafer, plasma etching the wafer on which the laser grooving is performed, exposing the bump by removing the coating film covering the bump, fabricating a semiconductor die by performing mechanical sawing of the wafer, and packaging the semiconductor die.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 13, 2024
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jin Won Jeong, Jae Sik Choi, Byeung Soo Song
  • Patent number: 11901252
    Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Han Wang, Ian Hu
  • Patent number: 11894311
    Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Robert Alan May, Islam A. Salama, Sri Ranga Sai Boyapati, Sheng Li, Kristof Darmawikarta, Robert L. Sankman, Amruthavalli Pallavi Alur
  • Patent number: 11894293
    Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11887914
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: January 30, 2024
    Inventors: Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung
  • Patent number: 11887932
    Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Zhiguo Qian, Jianyong Xie
  • Patent number: 11887960
    Abstract: This member connection method includes a printing step. In the printing step, a coating film-formed region in which the coating film is formed, and a coating film non-formed region in which the coating film is not formed are formed in the print pattern, and the coating film-formed region is divided into a plurality of concentric regions and a plurality of radial regions by means of a plurality of line-shaped regions provided so as to connect various points, which are separated apart from one another in the marginal part of the connection region.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: January 30, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Motohiro Negishi, Hideo Nakako, Yuki Kawana, Dai Ishikawa, Chie Sugama, Yoshinori Ejiri
  • Patent number: 11887919
    Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yun Seok Choi
  • Patent number: 11887964
    Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: January 30, 2024
    Assignee: ZHEJIANG LAB
    Inventors: Shunbin Li, Weihao Wang, Ruyun Zhang, Qinrang Liu, Zhiquan Wan, Jianliang Shen
  • Patent number: 11887908
    Abstract: An electronic structure includes offset three-dimensional stacked chips; and a two-piece lid structure configured to extract heat from the bottom and top of the stacked chips.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kamal K. Sikka, Katsuyuki Sakuma, Hilton T. Toy, Shidong Li, Ravi K Bonam
  • Patent number: 11881451
    Abstract: The present disclosure provides a semiconductor device with an interconnect part and a method for preparing the semiconductor device. The semiconductor device comprises a device substrate and an interconnect part disposed over the device substrate. The interconnect part includes a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed over the lower redistribution layer. The interconnect part also includes an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect part further includes a passivation structure surrounding the interconnect frame.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: January 23, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ching-Cheng Chuang
  • Patent number: 11876037
    Abstract: A chip stacking and packaging structure includes a substrate, a first chip stacked on the substrate, a heat dissipation module, and a second chip stacked on the heat dissipation module. First bonding pads and second bonding pads are arranged on the substrate. First welding pins are arranged on the first chip. The first welding pins one-to-one cover and are one-to-one electrically connected to the first bonding pads. The heat dissipation module includes a first groove, a cooling liquid cavity, a liquid inlet, a liquid outlet, and first conductive columns. The first chip is embedded in the first groove. A side wall and a bottom wall of the first groove extend into the cooling liquid cavity. Each of the first conductive columns is electrically connected with a corresponding second bonding pad. Each of second welding pins of the second chip is electrically connected to a corresponding first conductive column.
    Type: Grant
    Filed: June 25, 2023
    Date of Patent: January 16, 2024
    Assignee: HOSIN GLOBAL ELECTRONICS CO., LTD
    Inventors: Chen-Nan Lai, Qingshui Liu
  • Patent number: 11876063
    Abstract: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11869808
    Abstract: An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: January 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Brent Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert Robison
  • Patent number: 11869877
    Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 9, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11869836
    Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghee Seo, Heonbok Lee, Tae-Yeol Kim, Daeyong Kim, Dohyun Lee
  • Patent number: 11860550
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11864320
    Abstract: An image display and a combined-type circuit carrying and controlling module thereof are provided. The combined-type circuit carrying and controlling module includes a first circuit substrate structure, a control substrate structure, a second circuit substrate structure, an insulative connection structure and a conductive connection structure. The first circuit substrate structure includes a first carrier substrate, a first circuit layout layer and a plurality of first conductive penetration bodies. The control substrate structure includes a circuit substrate and a circuit control chip. The second circuit substrate structure includes a second carrier substrate and a second circuit layout layer. The insulative connection structure is connected between the first carrier substrate and the second carrier substrate. The conductive connection structure is electrically connected between the first circuit layout layer and the second circuit layout layer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 2, 2024
    Assignee: ASTI GLOBAL INC., TAIWAN
    Inventor: Chien-Shou Liao
  • Patent number: 11862556
    Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taemok Gwon, Junhyoung Kim, Chadong Yeo, Youngbum Woo
  • Patent number: 11862604
    Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: January 2, 2024
    Assignee: Adeia Semiconductor Inc.
    Inventors: Javier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
  • Patent number: 11862503
    Abstract: A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: January 2, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11854976
    Abstract: A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghoon Baek, Seung Young Lee
  • Patent number: 11854993
    Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 11855130
    Abstract: A three-dimensional device structure includes a die including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, a through silicon via (TSV) structure that extends through the semiconductor substrate and electrically contacts a metal feature of the interconnect structure, and an integrated passive device (IPD) embedded in the semiconductor substrate and electrically connected to the TSV structure.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jen-Yuan Chang, Chien-Chang Lee, Chia-Ping Lai, Tzu-Chung Tsai
  • Patent number: 11851320
    Abstract: The present invention is directed to the synthesis of metallic nickel-molybdenum-tungsten films and coatings with direct current sputter deposition, which results in fully-dense crystallographically textured films that are filled with nano-scale faults and twins. The as-deposited films exhibit linear-elastic mechanical behavior and tensile strengths above 2.5 GPa, which is unprecedented for materials that are compatible with wafer-level device fabrication processes. The ultra-high strength is attributed to a combination of solid solution strengthening and the presence of the dense nano-scale faults and twins. These films also possess excellent thermal and mechanical stability, high density, low CTE, and electrical properties that are attractive for next generation metal MEMS applications. Deposited as coatings these films provide protection against friction and wear.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: December 26, 2023
    Assignee: The Johns Hopkins University
    Inventors: Gi-Dong Sim, Jessica Krogstad, Timothy P. Weihs, Kevin J. Hemker, Gianna Valentino
  • Patent number: 11855042
    Abstract: A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Sung-Feng Yeh
  • Patent number: 11854963
    Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.
    Type: Grant
    Filed: June 12, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Kuan Lee, Kuang-Wei Yang, Cherng-Shiaw Tsai, Cheng-Chin Lee, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Patent number: 11848266
    Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: December 19, 2023
    Assignee: SK HYNIX INC
    Inventors: Sung Lae Oh, Sang Woo Park, Dong Hyuk Chae
  • Patent number: 11848234
    Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11837586
    Abstract: A package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. The first die and a second die are disposed on the package substrate. The first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. The second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Yuan Chang, Sheng-Chih Wang
  • Patent number: 11834332
    Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
  • Patent number: 11837582
    Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: December 5, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
  • Patent number: 11837587
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Patent number: 11837526
    Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 11830817
    Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 28, 2023
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Rahul Agarwal, Raja Swaminathan, Michael S. Alfano, Gabriel H. Loh, Alan D. Smith, Gabriel Wong, Michael Mantor
  • Patent number: 11830823
    Abstract: In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 28, 2023
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Tae Ki Kim, Jae Beom Shim, Min Jae Yi, Yi Seul Han, Young Ju Lee, Kyeong Tae Kim
  • Patent number: 11823999
    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: November 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Jae Taek Kim
  • Patent number: 11823969
    Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
  • Patent number: 11817305
    Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: November 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Kunal R. Parekh