Via (interconnection Hole) Shape Patents (Class 257/774)
  • Patent number: 10711088
    Abstract: Provided is a resin composition that can provide a cured product of low dielectric tangent, high mechanical strength, and high adhesiveness. The resin composition contains (A) a resin having a thermosetting functional group FA, (B) a resin having a radical polymerizable functional group FB, and (C) a resin having a functional group FA? reacting with the thermosetting functional group FA and a functional group FB? reacting with the radical polymerizable functional group FB. A number na of the functional group FA? of the component (C) when the number of the thermosetting functional group FA of the component (A) is defined as 1 and a number nb of the functional group FB? of the component (C) when the number of the radical polymerizable functional group FB of the component (B) is defined as 1 satisfy 0.01?na?200 and 0.01?nb?400, respectively.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: July 14, 2020
    Assignee: AJINOMOTO CO., INC.
    Inventor: Kota Torii
  • Patent number: 10707159
    Abstract: Provided is a semiconductor device having a surface layer power supply path in a surface layer wiring layer, on which a chip module is mounted, of a main substrate that has a plurality of wiring layers and through holes, the surface layer power supply path supplying power to a semiconductor chip via an inner peripheral-side power supply terminal group and an outer peripheral-side power supply terminal group. The surface layer power supply path overlaps the inner peripheral-side power supply terminal group and the outer peripheral-side power supply terminal group as seen in the orthogonal direction, and is formed continuously so as to extend in a direction from a position at which the surface layer power supply path is connected to the inner peripheral-side power supply terminal group toward the outer peripheral side of the main substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 7, 2020
    Assignee: AISIN AW CO., LTD.
    Inventor: Takanobu Naruse
  • Patent number: 10692847
    Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Sobieski, Kristof Darmawikarta, Sri Ranga Sai Boyapati, Merve Celikkol, Kyu Oh Lee, Kemal Aygun, Zhiguo Qian
  • Patent number: 10692733
    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Wayne H. Huang
  • Patent number: 10692823
    Abstract: There is provided a semiconductor device that enables a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has reduced a wiring length to improve transmission quality of signals or the like so as to achieve miniaturization of the semiconductor module. The semiconductor device includes a wiring substrate, a semiconductor chip disposed on an upper surface of the wiring substrate, a resin portion formed between the wiring substrate and the semiconductor chip, and a circuit element embedded in the resin portion. The circuit element includes a first terminal connected to wiring formed on the upper surface of the wiring substrate, and a second terminal connected to a bump provided on a lower surface of the semiconductor chip.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 23, 2020
    Assignee: SONY CORPORATION
    Inventor: Kiyohisa Sakai
  • Patent number: 10688437
    Abstract: A filter structure for chemical solution used in manufacturing an integrated circuit includes: a first membrane structure comprising a plurality of membrane units, each comprising a cathode comprising a plurality of first openings, an anode comprising a plurality of second openings, and an insulating layer between the cathode and the anode; and a filter housing configured to receive the first membrane structure therein, the filter housing comprising an inlet through which the chemical solution is introduced and an outlet through which the chemical solution is discharged. The first membrane structure is configured such that when an electric field is applied between the cathode and the anode while the chemical solution introduced through the inlet passes through the first membrane structure, impurities having both positively charged particles and negatively charged particles in the chemical solution are trapped in the first membrane structure.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cha-won Koh, Oleg Feygenson, Jung-hyeon Kim, Hyun-woo Kim, Eun-sung Kim
  • Patent number: 10692805
    Abstract: A semiconductor package includes a semiconductor chip having a first surface on which connection pads are disposed and a second surface opposing the first surface; a connection member including a first insulating layer disposed on the first surface of the semiconductor chip, a wiring pattern disposed on the first insulating layer and having a top surface of which an edge is rounded, a via penetrating through the first insulating layer and electrically connecting the connection pads to the wiring pattern, and a second insulating layer disposed on the first insulating layer and covering the wiring pattern; and an encapsulant disposed on the connection member and encapsulating the semiconductor chip.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Da Hee Kim
  • Patent number: 10692809
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Patent number: 10685879
    Abstract: A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 16, 2020
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Ashim Dutta, Dominik Metzler, Takeshi Nogami
  • Patent number: 10685916
    Abstract: A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Wan Shin, Ho Jun Jung, Seung Chul Oh
  • Patent number: 10685976
    Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyasu Tanaka, Tomoaki Shino
  • Patent number: 10679915
    Abstract: A package structure includes a plurality of first dies, a first encapsulant, and a first redistribution structure. The first encapsulant encapsulates the first dies. The first redistribution structure is disposed on the first dies and the first encapsulant. The first redistribution structure includes a dielectric layer covering a top surface and sidewalls of the first encapsulant.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yin Hsieh, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 10679952
    Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 9, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Won Chul Do, Doo Hyun Park, Eun Ho Park, Sung Jae Oh
  • Patent number: 10679958
    Abstract: A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shih-Fan Kuan, Yi-Jen Lo
  • Patent number: 10672822
    Abstract: A semiconductor unit includes: a first device substrate including a first semiconductor substrate and a first wiring layer, in which the first wiring layer is provided on one surface side of the first semiconductor substrate; a second device substrate including a second semiconductor substrate and a second wiring layer, in which the second device substrate is bonded to the first device substrate, and the second wiring layer is provided on one surface side of the second semiconductor substrate; a through-electrode penetrating the first device substrate and a part or all of the second device substrate, and electrically connecting the first wiring layer and the second wiring layer to each other; and an insulating layer provided in opposition to the through-electrode, and penetrating one of the first semiconductor substrate and the second semiconductor substrate.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: June 2, 2020
    Assignee: SONY CORPORATION
    Inventors: Satoru Wakiyama, Hiroshi Ozaki
  • Patent number: 10672664
    Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Patent number: 10672624
    Abstract: A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, William Boyd Rogers, Craig Bishop
  • Patent number: 10672659
    Abstract: An electronic component manufacturing method includes preparing a structure including a conductive member, forming a seed metal layer including first and second portions electrically connected to the conductive member on a surface of the structure, forming a plating layer on the first portion of the seed metal layer in a state in which the second portion of the seed metal layer is covered by a first member, forming a conductive second member on the first portion of the seed metal layer via the plating layer, and etching the second portion of the seed metal layer in a state in which the plating layer is covered by the second member.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 2, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Kazue
  • Patent number: 10672650
    Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain, Mark T. Bohr
  • Patent number: 10672720
    Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 2, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Tomoharu Awaya, Koji Banno, Takayoshi Minami
  • Patent number: 10672698
    Abstract: A chip on film according to the present disclosure includes a base film, a plurality of signal wirings on an upper surface and a lower surface of the base film to transmit a signal in two signal paths, a driving unit on one surface of the upper surface and the lower surface of the base film, a first pad and a second pad on one surface of the upper surface and the lower surface of the base film, and a plurality of through holes between the first pad and the second pad and electrically connect to the signal wiring.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 2, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Daekyung Kim, Wansik Lim, Jaesung Jeon, Ri Yu, Cheolho Lee, Joohye Kang
  • Patent number: 10672705
    Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yongan Xu, Junli Wang, Yann Mignot, Joe Lee
  • Patent number: 10665456
    Abstract: A semiconductor structure comprises a substrate comprising an interlayer dielectric (ILD) and a silicon layer disposed over the ILD, wherein the ILD comprises a conductive structure disposed therein, a dielectric layer disposed over the silicon layer, and a conductive plug electrically connected with the conductive structure and extended from the dielectric layer through the silicon layer to the ILD, wherein the conductive plug has a length extending from the dielectric layer to the ILD and a width substantially consistent along the length.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Pei Chou, Chen-Fa Lu, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10665695
    Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 26, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10667382
    Abstract: Disclosed is an electromagnetic shielding structure of a solid state driver (SSD), and particularly an electromagnetic shielding structure of an SSD, in which an electromagnetic shielding structure of a closed shield can type is achieved based on an electromagnetic shielding structure that employs an electromagnetic shielding coating layer electrically connected to a ground via hole formed in a printed circuit board (PCB) and a lower electromagnetic shielding layer formed inside the PCB and electrically connected to the electromagnetic shielding coating layer through the ground via hole, thereby improving electromagnetic shielding performance.
    Type: Grant
    Filed: April 21, 2019
    Date of Patent: May 26, 2020
    Assignees: Mega electronics Co., Ltd., Sunsystem Co., Ltd.
    Inventor: Jong Myung Kim
  • Patent number: 10658322
    Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 19, 2020
    Assignee: Google LLC
    Inventors: Woon Seong Kwon, Nam Hoon Kim, Teckgyu Kang
  • Patent number: 10651148
    Abstract: An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10651158
    Abstract: In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 12, 2020
    Assignee: Longitude Licensing Limited
    Inventors: Ryohei Kitada, Masahiro Yamaguchi
  • Patent number: 10643934
    Abstract: A wiring substrate include a pad, an insulation layer having an opening arranged on the pad, a metal post including a seed layer and a metal plated layer, the seed layer arranged on the pad and an upper surface of the insulation layer, the metal plated layer arranged on the seed layer, and a connection metal layer formed on the metal plated layer. A side surface of the metal plated layer has a concave surface recessed inward from a lower end of the connection metal layer. A side surface of the seed layer is recessed inward from a lower end of the metal plated layer.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 5, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tomoyuki Shimodaira
  • Patent number: 10644232
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and at least one trench line formed within the substrate. The semiconductor device further includes a self-aligned landing pad in contact with the at least one trench line, and a magnetic tunnel junction stack formed on and in contact with the self-aligned landing pad. The method includes forming a conductive layer on and in contact with at least one trench line formed within a substrate. Magnetic tunnel junction stack layers are deposited on and in contact with the conductive layer. The magnetic tunnel junction stack layers are etched to form a magnetic tunnel junction stack, where the etching stops on the conductive layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Eugene J. O'Sullivan
  • Patent number: 10643960
    Abstract: A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Wataru Shiroi, Shinji Katayama, Keita Tsuchiya
  • Patent number: 10644261
    Abstract: A display device includes: an insulating substrate, where a through hole is defined through the insulating substrate; and an organic layer which covers the insulating substrate. In the display device, a barrier area surrounding the through hole is defined in the insulating substrate, and an interruption portion, at which the organic layer is interrupted, is defined in the barrier area.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG DISPLAY CO. LTD.
    Inventors: Kwang Soo Lee, Jong Hyun Yun
  • Patent number: 10629693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Patent number: 10629477
    Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Jing-Cheng Lin, Hung-Jui Kuo
  • Patent number: 10629643
    Abstract: An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-hyun Kim, Sang-il Jung, Byung-jun Park
  • Patent number: 10622322
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Doo Hwan Lee, Kyoung Moo Harr, Kyung Seob Oh
  • Patent number: 10622252
    Abstract: In one embodiment of the present disclosure, a microfeature workpiece includes at least two features of two different sizes disposed in a dielectric, wherein a width of a first feature is less than or equal to 17 nm and wherein the first feature is filled with cobalt or nickel, and wherein a width of a second feature is greater than 20 nm and wherein the second feature is filled with a stack layer of cobalt or nickel and copper.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: April 14, 2020
    Assignee: APPLIED Materials, Inc.
    Inventors: Roey Shaviv, Ismail T. Emesh
  • Patent number: 10622302
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh
  • Patent number: 10624206
    Abstract: To provide a circuit board that is capable of establishing electrical connection, that is thinner, and that has a higher maintainability. A circuit board includes a substrate including a hole portion that penetrates the substrate in a plate thickness direction, and a connector region including a first conductor layer that closes one side of the hole portion, liquid metal disposed in a recess formed by the hole portion and the first conductor layer, and a sealing layer that is the liquid metal cured on a liquid surface side. The liquid metal may be in contact with a second conductor layer formed in the recess.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: April 14, 2020
    Assignee: IRISO ELECTRONICS CO., LTD.
    Inventors: Yujiro Sugaya, Yuki Asanuma
  • Patent number: 10615154
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 10615117
    Abstract: There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Robert L. Bristol, Rami Hourani, James M. Blackwell
  • Patent number: 10608144
    Abstract: Provided is a light emitting diode (LED) mounted on a carrier substrate and including a semiconductor epitaxial structure and at least one electrode pad structure. The semiconductor epitaxial structure is electrically connected to the carrier substrate. The electrode pad structure includes a eutectic layer, a barrier layer and a ductility layer. The eutectic layer is adapted for eutectic bonding to the carrier substrate. The barrier layer is between the eutectic layer and the semiconductor epitaxial structure. The barrier layer blocks the diffusion of the material of the eutectic layer in the eutectic bonding process. The ductility layer is between the eutectic layer and the semiconductor epitaxial structure. The ductility layer reduces the stress on the LED produced by thermal expansion and contraction of the substrate during the eutectic bonding process, so as to prevent the electrode pad structure from cracking, and maintain the quality of the LED.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 31, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Chih-Ming Shen, Sheng-Tsung Hsu, Kuan-Chieh Huang, Jing-En Huang, Shao-Ying Ting
  • Patent number: 10600888
    Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.
    Type: Grant
    Filed: June 10, 2018
    Date of Patent: March 24, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10600683
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 24, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 10600770
    Abstract: A semiconductor device assembly, including an interposer comprising a glass material, a semiconductor die comprising a proximity coupling on a side of the interposer, and at least one other semiconductor die comprising a proximity coupling configured for communicating signals with the proximity coupling of the semiconductor die, on an opposing side of the interposer. The assembly may optionally be configured for optical signal communication with higher level packaging. Semiconductor device packages, systems and methods of operation are also disclosed.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Shiro Uchiyama
  • Patent number: 10593594
    Abstract: Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: March 17, 2020
    Assignee: Micromaterials LLC
    Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang, Uday Mitra, Regina Freed
  • Patent number: 10586756
    Abstract: A chip carrier for carrying an electronic chip, wherein the chip carrier comprises a mounting section configured for mounting an electronic chip by sintering, and an encapsulation section configured for being encapsulated by an encapsulant.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 10, 2020
    Assignee: Infineon Technologies AG
    Inventors: Alexander Roth, Andreas Grassmann, Juergen Hoegerl, Angela Kessler
  • Patent number: 10585152
    Abstract: In one aspect, an integrated circuit (IC) includes a sensor that includes a first magnetoresistive (MR) element and a second MR element less active to a presence of a magnetic field than the first MR element. The second MR element includes a metal layer diffused into other layers of the second MR element.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 10, 2020
    Assignee: ALLEGRO MICROSYSTEMS, LLC
    Inventors: Paul A. David, William P. Taylor
  • Patent number: 10580739
    Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device disposed in the molding compound body, the first circuit device having a first terminal at a top of the first circuit device; a first conductive via formed in the molding compound body and connected to the first terminal; a second circuit device disposed in the molding compound body, the second circuit device having a second terminal at a top of the second circuit device; a second conductive via formed in the molding compound body and connected to the second terminal; and a redistribution layer with a conductive wire formed on the molding compound body, the conductive wire connecting the first conductive via and the second conductive via; wherein the first and second terminals are respectively located at different depths of the molding compound body.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: March 3, 2020
    Assignee: PHOENIX & CORPORATION
    Inventors: Chu-Chin Hu, Shih-Ping Hsu
  • Patent number: 10580732
    Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a first conductive layer disposed on the second main surface; a second conductive layer passing through the semiconductor substrate from the first main surface to the second main surface so that the second conductive layer is connected to the first conductive layer; an organic insulation film disposed to contact with the first conductive layer; and a first insulation layer disposed to contact with the organic insulation film. The second conductive layer has a first portion passing through the semiconductor substrate so that the first portion contacts with the semiconductor substrate through the organic insulation film and the first insulation layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: March 3, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Akihiko Nomura