Via (interconnection Hole) Shape Patents (Class 257/774)
  • Patent number: 11031394
    Abstract: A 3D semiconductor device including: a first level, which includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a plurality of connection paths, where the paths provide connections from a plurality of the first transistors to a plurality of second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions and metal to metal bond regions, where the second level includes at least one memory array, and where the third layer includes crystalline silicon; and a heat removal path from the first layer or the third layer to an external surface of the device.
    Type: Grant
    Filed: February 7, 2021
    Date of Patent: June 8, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11032911
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: June 8, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Fan Chen, Chien-Hao Wang
  • Patent number: 11031285
    Abstract: Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 8, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Patent number: 11031274
    Abstract: A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 8, 2021
    Inventors: Yu-Lin Shih, Chih-Cheng Lee
  • Patent number: 11024607
    Abstract: A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventor: Junfeng Zhao
  • Patent number: 11024605
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 11018083
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die, a through via structure, a dipole structure and an encapsulant. The through via structure and the dipole structure are disposed aside the semiconductor die, and respectively includes an insulating core and a conductive layer. A front surface and a sidewall of the insulating core are covered by the conductive layer. The semiconductor die, the through via structure and the dipole structure are laterally encapsulated by the encapsulant. Surfaces of capping portions of the conductive layers covering the front surfaces of the insulating cores are substantially coplanar with a front surface of the encapsulant.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Ching-Feng Yang, Hung-Jui Kuo, Kai-Chiang Wu, Ming-Che Ho
  • Patent number: 11018120
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 25, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
  • Patent number: 11011482
    Abstract: A semiconductor package includes a semiconductor chip, an encapsulant, and an interconnection member. The semiconductor chip has connection pads. The encapsulant encapsulates a portion of the semiconductor chip. The interconnection member includes a first insulating layer disposed on the encapsulant and a portion of the semiconductor chip, a redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the redistribution layer. The redistribution layer is electrically connected to the connection pads of the semiconductor chip, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 11011412
    Abstract: A semiconductor structure and a method for forming same are provided.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Wei Shi, Youcun Hu, Xiamei Tang
  • Patent number: 11011470
    Abstract: Embodiments may relate to a microelectronic package that includes a substrate with an overmold material. The microelectronic package may include a die in the overmold material, and an inactive side of the die may be coupled with a face of the substrate. A through-mold via (TMV) may be present in the overmold material. The TMV may be communicatively coupled with the substrate, and an active side of the die may be communicatively coupled with the TMV by a trace in the overmold material. Other embodiments may be described or claimed.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Patent number: 11011463
    Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Richard E. Schenker, Jeffery D. Bielefeld, Rami Hourani, Manish Chandhok
  • Patent number: 11011501
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11011416
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 18, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Jin Jisong
  • Patent number: 11004733
    Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
  • Patent number: 11004827
    Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo Lung Pan, Tin-Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Patent number: 11004802
    Abstract: An integrated circuit chip includes a wide bandgap semiconductor substrate, a plurality of semiconductor electronic components disposed on the semiconductor substrate, an overlying insulating layer disposed on the plurality of semiconductor devices, and a crack barrier laterally displaced from all of the plurality of semiconductor components. The crack barrier is configured to prevent propagation of cracks in the overlying insulating layer. The crack barrier does not conductively connect to any of the plurality of semiconductor electronic components.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 11, 2021
    Assignee: United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventors: David J. Spry, Philip G. Neudeck
  • Patent number: 10998290
    Abstract: Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mitsuhisa Watanabe, Fumitomo Watanabe, Masanori Yoshida
  • Patent number: 10991621
    Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Connie Alagadan Esteron, Dolores Babaran Milo
  • Patent number: 10991685
    Abstract: A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 10985081
    Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: April 20, 2021
    Assignee: SONY CORPORATION
    Inventor: Yukihiro Ando
  • Patent number: 10985103
    Abstract: An integrated circuit (IC) apparatus and a method of forming a conductive material in a backside of an IC are provided. The IC apparatus includes a substrate including a frontside and a backside; at least one first insulating material deposited in the backside of the substrate in a form of a trench; a conductive material deposited in each of the at least one first insulating material; at least one second insulating material deposited on the conductive material to insulate the conductive material from the substrate; an epitaxial crystalline material grown on the frontside of the substrate; at least one semiconductor component formed in the epitaxial crystalline material; and at least one via formed in the substrate to connect the conductive material to the at least one semiconductor component.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 20, 2021
    Inventors: Joon Goo Hong, Rwik Sengupta
  • Patent number: 10978389
    Abstract: A device includes a first dielectric layer, a first conductor, a second dielectric layer, a second conductor, and an etch stop layer. The first conductor is in the first dielectric layer. The second dielectric layer is over the first dielectric layer. The second conductor is in the second dielectric layer and electrically connected to the first conductor. The second conductor has a first portion over a top surface of the first conductor and a second portion extending downwards from the first portion and around the first conductor. The etch stop layer has a first portion between the second portion of the second conductor and the first dielectric layer and a second portion between the first dielectric layer and the second dielectric layer. A top surface of the first portion of the etch stop layer is lower than a top surface of the second portion of the etch stop layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Sheng Zheng, Chih-Lin Wang
  • Patent number: 10978458
    Abstract: A semiconductor device includes a bit line structure including a bit line contact plug and a bit line on the bit line contact plug, a storage node contact plug, an ultra low-k spacer including a gap-fill spacer contacting a side wall of the bit line contact plug and a line-type spacer contacting a side wall of the bit line, and a low-k spacer formed on the line-type spacer of the ultra low-k spacer to contact the storage node contact plug, wherein the gap-fill spacer is thicker than the line-type spacer.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Yun-Hyuck Ji, Beom-Ho Mun, In-Sang Kim
  • Patent number: 10978346
    Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Hui Huang, Hung-Pin Chang, Sao-Ling Chiu, Shang-Yun Hou, Wan-Yu Lee
  • Patent number: 10967400
    Abstract: An ultrasonic transducer includes a membrane, a bottom electrode, and a plurality of cavities disposed between the membrane and the bottom electrode, each of the plurality of cavities corresponding to an individual transducer cell. Portions of the bottom electrode corresponding to each individual transducer cell are electrically isolated from one another. Each portion of the bottom electrode corresponds to each individual transducer that cell further includes a first bottom electrode portion and a second bottom electrode portion, the first and second bottom electrode portions electrically isolated from one another.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: April 6, 2021
    Assignee: Butterfly Network, Inc.
    Inventors: Susan A. Alie, Keith G. Fife, Joseph Lutsky, David Grosjean
  • Patent number: 10971518
    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including electrodes vertically stacked on the substrate and each having a pad portion, electrode separation structures penetrating the electrode structure and apart from each other in a second direction, and contact plugs coupled to the pad portions. The contact plugs comprise first contact plugs and second contact plugs apart in the second direction from the first contact plugs. The electrode separation structures comprise a first electrode separation between the first and second contact plugs. The first contact plugs are apart in the second direction at a first distance from the first electrode separation structure. The second contact plugs are apart in the second direction from the first electrode separation structure at a second distance, different from the first distance.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jibong Park, Soyeon Kim, Hanyoung Lee, Young-Bae Yoon, Dongseog Eun
  • Patent number: 10964588
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 30, 2021
    Assignee: Tessera, Inc.
    Inventors: Christopher J. Penny, Benjamin David Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10957649
    Abstract: A system in package device includes an overpass die on a package substrate and the overpass die includes a recess on the back side in order to straddle a landed die also on the package substrate. The recess is bounded by at least two overpass walls. Communication between the dice is done with a through-silicon via and communication between the overpass die and the package substrate is also done with a through-silicon via.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Min Suet Lim, Jackson Chung Peng Kong
  • Patent number: 10945647
    Abstract: Method and system for providing analyte sensor alignment and retention mechanism for improved connectivity with a transmitter unit for electrical connection, and further including transmitter unit contact pins with metal components to improve electrical conductivity with the analyte sensor in an analyte monitoring and management system is provided.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: March 16, 2021
    Assignee: ABBOTT DIABETES CARE INC.
    Inventors: John C. Mazza, Andrew H. Naegeli, Gary Ashley Stafford
  • Patent number: 10950540
    Abstract: Methods are disclosed herein for fabricating integrated circuit interconnects that can improve electromigration. An exemplary method includes forming a first metal layer of an integrated circuit and forming a second metal layer of the integrated circuit. The first metal layer includes a first conductor electrically coupled to a second conductor, and the second metal layer includes a third conductor electrically coupled to the first conductor. The first conductor, the second conductor, and the third conductor are configured, such that electrons flow from the second conductor to an area of the first conductor where electrons flow from the third conductor to the first conductor.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Ming-Hsien Lin
  • Patent number: 10949597
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • Patent number: 10943852
    Abstract: According to some embodiments, a semiconductor device includes a semiconductor substrate, a metal portion, a first insulating film, and a second insulating film. The semiconductor substrate has a through-hole extending from a first surface of the semiconductor substrate to a second surface thereof opposite to the first surface. The metal portion is formed in the through-hole. The first insulating film is provided on the second surface of the semiconductor substrate and on a side surface of the through-hole. The second insulating film has a dielectric constant of not more than 6.5 and is provided on a metal portion-side surface of the first insulating film on the side surface of the through-hole of the semiconductor substrate.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ippei Kume, Taketo Matsuda, Shinya Okuda, Masahiko Murano
  • Patent number: 10943817
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an inter-layer dielectric (ILD) layer above a substrate. Individual ones of the plurality of conductive interconnect lines have an upper surface below an upper surface of the ILD layer. An etch-stop layer is on and conformal with the ILD layer and the plurality of conductive interconnect lines, the etch-stop layer having a non-planar upper surface with an uppermost portion of the non-planar upper surface over the ILD layer and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Andrew W. Yeoh, Ruth Brain, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10943853
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In the device, the isolation layer is used to prevent the first metal layer and the second metal layer which are over-etched and back-splashed from diffusing to a first substrate; and the isolation layer serves as a barrier layer to prevent an interconnection layer from diffusing into the first substrate. Further, the isolation layer includes a silicon nitride layer, which is advantageous for preventing the metal layers from back-splashing and diffusing to the sidewall of the first substrate. The isolation layer further includes a first silicon oxide layer and a second silicon oxide layer, wherein the second silicon oxide layer is used to protect the silicon nitride layer from being etched and consumed and the first silicon oxide layer is used to improve the adhesion between the silicon nitride layer and the first substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 9, 2021
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xing Hu, Yu Zhou, Tianjian Liu, Sheng Hu, Changlin Zhao
  • Patent number: 10937749
    Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Neng-Tai Shih
  • Patent number: 10937849
    Abstract: An array substrate has a display area and a non-display area disposed at a periphery of the display area. The array substrate includes: a base substrate; at least one gate driver on array (GOA) circuit disposed on the base substrate and disposed in the non-display area; a planarization layer disposed on a side of the at least one GOA circuit facing away from the base substrate; and at least one electrostatic protection portion disposed on a surface of the planarization layer facing away from the base substrate and disposed in the non-display area. An orthographic projection of each GOA circuit on the base substrate is located within an outer boundary of an orthographic projection of a corresponding electrostatic protection portion on the base substrate.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 2, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hongfei Cheng
  • Patent number: 10937721
    Abstract: A semiconductor structure includes a first die, a molding at least partially surrounding the first die, a via extended through the molding, a second die disposed over the molding, a connector dispose between the second die and the via, and an underfill at least partially surrounding the connector. The first die includes a first surface and a second surface opposite to the first surface. The second die includes a third surface facing the first die, a fourth surface opposite to the third surface, and a sidewall between the third surface and the fourth surface. The connector is in contact with the third surface of the second die and the via. The second die is electrically connected to the via. The underfill covers a portion of the sidewall of the second die and a portion of the second surface of the first die.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Chien Hsun Lee
  • Patent number: 10937858
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a substrate including an electrical component; forming a capacitor structure in the substrate, proximal to a heterogeneous interface of the substrate, and physically and electrically isolated from the electrical component; forming a conductive terminal over and electrically connected with the capacitor structure; and contacting the conductive terminal with a probe to measure an electrical parameter of the capacitor structure, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Patent number: 10937732
    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer and a second dielectric layer that are sequentially stacked on the substrate, a contact that penetrates the first dielectric layer and extends toward the substrate, and a conductive line that is provided in the second dielectric layer and electrically connected to the contact, The conductive line extends in a first direction. The contact comprises a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. A width in a second direction of the conductive line decreases with decreasing distance from the substrate. The second direction intersects the first direction. A sidewall of the upper segment of the contact is in contact with the conductive line.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kiho Yang
  • Patent number: 10937755
    Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 2, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Milind S. Bhagavat
  • Patent number: 10935031
    Abstract: A booster system includes: a cooling temperature regulating unit configured to regulate a temperature of an intermediate supercritical pressure liquid cooled and generated by a main cooling unit on upstream of a pump unit according to a flow rate of a supplied cooling medium; and a pressure detection unit configured to detect inlet pressure of the intermediate supercritical pressure liquid on an inlet side of the pump unit and detect outlet pressure of a target supercritical fluid on an outlet side of the pump unit. The cooling temperature regulating unit controls the flow rate of the cooling medium based on a pressure difference between the inlet pressure and the outlet pressure or a pressure ratio between the inlet pressure and the outlet pressure.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 2, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES COMPRESSOR CORPORATION
    Inventors: Hiroyuki Takaki, Yosuke Nakagawa
  • Patent number: 10930618
    Abstract: A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Won-young Kim
  • Patent number: 10923415
    Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Shawna M. Liff, Feras Eid
  • Patent number: 10923394
    Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 16, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Robert Clark, Kandabara Tapily, Kai-Hung Yu
  • Patent number: 10923450
    Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Richard Fastow, Khaled Hasnat, Prashant Majhi, Owen W. Jungroth, Krishna Parat
  • Patent number: 10916494
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
  • Patent number: 10910327
    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Brandon C Marin, Vahidreza Parichehreh, Jeremy D Ecton
  • Patent number: 10910426
    Abstract: A semiconductor device is described which includes a substrate, an interlayer insulating layer provided below the substrate and including a via pad therein, a through via located at least partially within a via hole passing through the substrate and a portion of the interlayer insulating layer, a connection pad on the substrate, and a pad isolation pattern formed in the substrate to be located around the connection pad and the through via. The pad isolation pattern includes a plurality of bent portions having protrusions and recesses when viewed from a top view. As a result, cracks may be prevented from forming or growing in the semiconductor device.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byungjun Park, Jinju Jeon, Younghwan Choi
  • Patent number: 10910345
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: February 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Pei-Jhen Wu, Ching-Hung Chang, Hsih-Yang Chiu