FABRICATION OF NICKEL FREE SILICIDE FOR SEMICONDUCTOR CONTACT METALLIZATION
A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.
1. Technical Field
The present invention generally relates to semiconductor devices and methods of fabricating the semiconductor devices. More particularly, the present invention relates to semiconductor devices and methods of fabricating nickel-free silicide for contact metallization.
2. Background Information
Silicide processes have been widely used to form silicide contacts on the gate and source/drain during the semiconductor device fabrication processing to improve the performance of the semiconductor device. The silicide layer improves the operational speed of the semiconductor device by reducing the contact resistance between the metal contact and source and drain.
More recently, nickel monosilicide (NiSi) has been employed as the silicide material of choice, because of the several advantages associated with it, such as, for example, low resistance (10.5-18 μΩ cm) and low formation temperature (350° C.). However, nickel silicide is sensitive to oxygen contamination from the ambient air and from residual interfacial contaminants such as native oxides. Such contamination can lead to rough and/or insulating interfaces causing high contact resistance in the device. The diffusion characteristics of nickel into underlying silicon (Si), silicon germanium (SiGe) and germanium (Ge) substrates can create issues such as, piping/spiking defects during the silicidation process, which leads to leakage of current into the channel as well as the junction regions, resulting in degradation in device performance.
Hence, there exists a need to develop silicidation processes lacking nickel for improving the semiconductor device performance in scaled-down technologies.
SUMMARY OF THE INVENTIONThe shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a method of forming a bilayer liner in a semiconductor device. The method includes providing a semiconductor device with an n-type transistor and a p-type transistor and the n-type transistor and the p-type transistor include an active region, the active region including two adjacent gate structures thereon. The method further includes selectively removing a portion of a dielectric layer between two adjacent gate structures to form a contact opening, wherein the contact opening is defined by a bottom and sidewalls, and the contact opening further residing over the active region in each of the n-type transistor and the p-type transistor. The method further includes selectively providing a bilayer liner within the contact opening residing over the active region in the n-type transistor and providing a monolayer liner within the contact opening residing over the active region in the p-type transistor and filling the contact opening with contact material. The resultant contacts in the semiconductor device are metalized nickel free.
In accordance with another aspect, a semiconductor device is provided, including an intermediate structure of the semiconductor device having an n-type transistor and a p-type transistor, an active region of the semiconductor device and two adjacent gate structures over the active region of the semiconductor device in each of the n-type transistor and the p-type transistor. The semiconductor device further includes a contact opening in a dielectric layer between the two adjacent gate structures, the contact opening residing over the active region in each of the n-type transistor and the p-type transistor. Furthermore, a bilayer liner within the contact opening resides over the active region in the n-type transistor and a monolayer liner within the contact opening resides over the active region of the p-type transistor.
These and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings.
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
Reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers are used throughout different figures to designate the same or similar components.
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As one example, gate dielectric layer 109 may be formed of a material such as silicon dioxide or a high-k dielectric material with a dielectric constant k greater than about 3.9 (note that k=3.9 for SiO2), and may be deposited by performing a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. Examples of high-k dielectric materials which may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. As noted, one or more work-function layers 111 may be conformally deposited over gate dielectric layer 109, for example, via a deposition process such as ALD, MOCVD, CVD or PVD. The work-function layer(s) may include, for instance, one or more P-type metals or one or more N-type metals, depending on whether the gate structure is part of, for instance, a p-type transistor or an n-type transistor. Work-function layer(s) 111 may include an appropriate refractory metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), niobium nitride (NbN), vanadium nitride (VN), tungsten nitride (WN). In another specific example, work-function layer(s) 111 may include an appropriate refractory metal carbide, for example, titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum alimun carbide (TaAlC), niobium carbide (NbC), vanadium carbide (VC) etc,.
Gate structures 110, 112 may also include any of a variety of metal gate electrodes 113 such as, for example, tungsten (W), aluminum (Al) and may be conformally deposited over the one or more conformally deposited work function layers. Sidewall spacers 114 are disposed on the sides of respective adjacent gate structures 110 and 112 and may include, for example, silicon nitride. Sidewall spacers 114 may be deposited using conventional deposition processes, such as, for example, CVD or plasma assisted CVD.
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As will be subsequently explained, the present invention seeks to improve semiconductor device performance by eliminating the use of nickel during silicidation process, prior to the contact metallization. This may be accomplished by selectively providing a bilayer liner within the contact opening residing over the active region in the n-type transistor and providing a monolayer liner within the contact opening residing over the active region in the p-type transistor and filling the contact opening with contact material. The present invention may further be accomplished by selectively providing a protective mask over the contact opening residing over the active region in the p-type transistor. A first liner material is provided over the protective mask, the first liner material extending laterally over upper surface of the dielectric layer and further extending over the bottom and the sidewalls of the contact opening residing over the active region in the n-type transistor. The first liner is selectively removed over the protective mask and the upper surface of the dielectric layer, and leaving over the bottom and the sidewalls of the contact opening residing over the active region in the n-type transistor. The protective mask over the contact opening residing over the active region in the p-type transistor is selectively removed. A second liner material is provided over the contact opening residing over the active region in the p-type transistor and extending laterally over the upper surface of the dielectric layer and further extending over the first liner material residing in the bottom and the sidewalls of the contact opening residing over the active region in the n-type transistor.
In one aspect, the first liner material may include a first material and the second liner material may include a second material, and the first material being different from the second material. In one example, the first material may include one of metal-oxide-insulator semiconductor material, with the metal-oxide-insulator semiconductor material being compatible with n-type transistor. In another example, the second material may include one of a silicide precursor lacking nickel.
In a further aspect, the second liner material over the contact opening residing over the active region in each of the p-type transistor and n-type transistor is annealed to create a silicide in the bottom of the contact opening residing over the active region in the p-type transistor.
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While several aspects of the present invention have been described and depicted herein, alternative aspects may be affected by those skilled in the art to accomplish the same objectives. Accordingly, it is intended by the appended claims to cover all such alternative aspects as fall within the true spirit and scope of the invention.
Claims
1. A method comprising:
- fabricating a semiconductor device, the fabricating comprising; providing a semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor comprising an active region, the active region comprising two adjacent gate structures thereon; selectively removing a portion of a dielectric layer between two adjacent gate structures to form a contact opening, wherein the contact opening is defined by a bottom and sidewalls, and the contact opening further residing over the active region in each of the n-type transistor and the p-type transistor; selectively providing a bilayer liner within the contact opening residing over the active region in the n-type transistor and providing a monolayer liner within the contact opening residing over the active region in the p-type transistor; and
- filling the contact opening with contact material.
2. The method of claim 1, wherein the selectively providing the bilayer liner comprises selectively forming a first liner material within the contact opening residing over the active region in the n-type transistor.
3. The method of claim 1, wherein the selectively providing the bilayer liner comprises forming a second liner material over the first liner material within the contact opening residing over the active region in the n-type transistor.
4. The method of claim 3, wherein the first liner material comprises a first material and the second liner material comprises a second material.
5. The method of claim 4, wherein the first material being different from the second material.
6. The method of claim 4, wherein the first material comprises one of metal-oxide-insulator semiconductor material, and wherein the metal-oxide-insulator semiconductor material being compatible with n-type transistor.
7. The method of claim 4, wherein the second material comprises one of a silicide precursor lacking nickel.
8. The method of claim 2, wherein the selectively providing the bilayer liner further comprises:
- selectively providing a protective mask over the contact opening residing over the active region in the p-type transistor,
- providing the first liner material over the protective mask and extending laterally over upper surface of the dielectric layer and further extending over the bottom and the sidewalls of the contact opening residing over the active region in the n-type transistor;
- selectively removing the first liner material over the protective mask and the upper surface of the dielectric layer, and leaving the first liner material over the bottom and the sidewalls of the contact opening residing over the active region in the n-type transistor; and
- selectively removing the protective mask over the contact opening residing over the active region in the p-type transistor.
9. The method of claim 8, wherein the protective mask comprises a material different from the dielectric layer, and wherein the protective mask comprises an optical dispersive layer (ODL).
10. The method of claim 1, wherein the providing the monolayer liner further comprises providing the second liner material over the contact opening residing over the active region in the p-type transistor and extending laterally over the upper surface of the dielectric layer and further extending over the first liner material residing in the bottom and the sidewalls of the contact opening residing over the active region in the n-type transistor.
11. The method of claim 10, wherein the selectively providing the monolayer liner further comprises annealing the second liner material over the contact opening residing over the active region in each of the p-type transistor and n-type transistor.
12. The method of claim 10, wherein annealing comprises creating a silicide in the bottom of the contact opening residing over the active region in the p-type transistor.
13. A semiconductor device, comprising:
- an intermediate structure of the semiconductor device, comprising an n-type transistor and p-type transistor;
- an active region of the semiconductor device and two adjacent gate structures residing over the active region of the semiconductor device in each of the n-type transistor and the p-type transistor;
- a contact opening in a dielectric layer between the two adjacent gate structures, the contact opening residing over the active region in each of the n-type transistor and the p-type transistor;
- a bilayer liner within the contact opening residing over the active region in the n-type transistor and a monolayer liner within the contact opening residing over the active region in the p-type transistor.
14. The semiconductor device of claim 13, wherein the bilayer liner comprises a first liner material within the contact opening residing over the active region in the n-type transistor.
15. The semiconductor device of claim 13, wherein the bilayer liner comprises a second liner material over the first liner material within the contact opening residing over the active region in the n-type transistor.
16. The semiconductor device of claim 15, wherein first liner material comprises a first material and the second liner material comprises a second material, and wherein the first material being different from the second material.
17. The semiconductor device of claim 16, wherein the first material comprises one of metal-oxide-insulator semiconductor material, and wherein the metal-oxide-insulator material being compatible with n-type transistor.
18. The semiconductor device of claim 16, wherein the second material comprises one of a silicide precursor lacking nickel.
19. The semiconductor device of claim 15, wherein the monolayer liner material comprises the second liner material within the contact opening residing over the active region in the p-type transistor.
20. The semiconductor device of claim 19, wherein the monolayer liner is treated to form a silicide.
Type: Application
Filed: Jun 5, 2013
Publication Date: Dec 11, 2014
Inventor: Derya DENIZ (Troy, NY)
Application Number: 13/910,370
International Classification: H01L 21/283 (20060101); H01L 29/45 (20060101);