SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a semiconductor pillar provided on the substrate to extend in a vertical direction, a plurality of first electrode films provided sideward of the semiconductor pillar to extend in a first direction. The plurality of first electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a plurality of second electrode films provided between the semiconductor pillar and the first electrode films. The plurality of second electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a first insulating film provided between the semiconductor pillar and the second electrode films, and a second insulating film provided between the second electrode film and the first electrode film.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-003793, filed on Jan. 10, 2014; the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

BACKGROUND

Although conventionally the planar structure of NAND flash memory has been shrunk to increase the bit density and reduce the bit cost, such shrink is approaching a limit. Therefore, in recent years, technology has been proposed to stack the memory cells in the vertical direction. The data retention characteristics of the memory cells are problematic in such a stacked memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view showing a semiconductor memory device according to a first embodiment;

FIG. 2 is a cross-sectional view showing the semiconductor memory device according to the first embodiment;

FIG. 3 is a cross-sectional view showing region A shown in FIG. 2;

FIG. 4 is a cross-sectional view along line B-B′ shown in FIG. 2;

FIG. 5A to FIG. 17B are plan views and cross-sectional views showing a method for manufacturing the semiconductor memory device according to the first embodiment;

FIG. 18 is a cross-sectional view showing a semiconductor memory device according to a modification of the first embodiment;

FIG. 19 is a cross-sectional view showing a semiconductor memory device according to a second embodiment;

FIG. 20A to FIG. 30C are plan views and cross-sectional views showing a method for manufacturing the semiconductor memory device according to the second embodiment;

FIG. 31 is a cross-sectional view showing a semiconductor memory device according to a first modification of the second embodiment;

FIG. 32 is a cross-sectional view showing a semiconductor memory device according to a second modification of the second embodiment;

FIG. 33 is a cross-sectional view showing a semiconductor memory device according to a third modification of the second embodiment;

FIG. 34 is a cross-sectional view showing a semiconductor memory device according to a third embodiment;

FIGS. 35A to 37C are plan views and cross-sectional views showing the method for manufacturing the semiconductor memory device according to the third embodiment;

FIGS. 38A to 38C are cross-sectional views showing a semiconductor memory device according to a modification of the third embodiment;

FIGS. 39A to 39C are cross-sectional views showing a method for manufacturing the semiconductor memory device according to the modification of the third embodiment;

FIG. 40 is a cross-sectional view showing a semiconductor memory device according to a forth embodiment;

FIG. 41 is a cross-sectional view showing region E shown in FIG. 40;

FIG. 42A is a cross-sectional view showing a method for manufacturing the semiconductor memory device according to the forth embodiment; and FIG. 42B is a plan view;

FIG. 43 and FIG. 44 are cross-sectional views showing a semiconductor memory device according to a fifth embodiment;

FIG. 45 to FIG. 53 are cross-sectional views showing a method for manufacturing the semiconductor memory device according to the fifth embodiment;

FIG. 54 is a cross-sectional view showing a semiconductor memory device according to a modification of the fifth embodiment; and

FIG. 55 to FIG. 57 are cross-sectional views showing the method for manufacturing the semiconductor memory device according to the modification of the fifth embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memory device includes a substrate, a semiconductor pillar provided on the substrate to extend in a vertical direction, a plurality of first electrode films provided sideward of the semiconductor pillar to extend in a first direction. The plurality of first electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a plurality of second electrode films provided between the semiconductor pillar and the first electrode films. The plurality of second electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a first insulating film provided between the semiconductor pillar and the second electrode films, and a second insulating film provided between the second electrode film and the first electrode film.

First Embodiment

Embodiments of the invention will now be described with reference to the drawings.

First, a first embodiment will be described.

FIG. 1 is a perspective view showing a semiconductor memory device according to the embodiment.

FIG. 2 is a cross-sectional view showing the semiconductor memory device according to the embodiment.

FIG. 3 is a cross-sectional view showing region A shown in FIG. 2.

FIG. 4 is a cross-sectional view along line B-B′ shown in FIG. 2.

As shown in FIG. 1 and FIG. 2, a silicon substrate 10 is provided in the semiconductor memory device 1 according to the embodiment. A memory cell region Rm and a peripheral circuit region Rc are set in the silicon substrate 10. Hereinbelow, an XYZ orthogonal coordinate system is employed in the specification for convenience of description. Two mutually-orthogonal directions parallel to an upper surface 10a of the silicon substrate 10 are taken as an X-direction and a Y-direction; and a direction perpendicular to the upper surface 10a is taken as a Z-direction.

In the memory cell region Rm, an insulating film 11 (a third insulating film) that is made of, for example, silicon oxide, a conductive layer 12 that is made of, for example, polysilicon, an interconnect layer 13 that is made of, for example, tungsten, and a conductive layer 14 that is made of, for example, polysilicon are stacked in this order on the silicon substrate 10. A cell source line 15 is formed of the conductive layer 12, the interconnect layer 13, and the conductive layer 14. An insulating film 17 that is made of, for example, silicon oxide is provided on the cell source line 15. Multiple silicon pillars 20 that extend in the Z-direction are provided on the cell source line 15. The silicon pillars 20 are made of, for example, polysilicon; and the lower ends of the silicon pillars 20 pierce the insulating film 17 to be connected to the cell source line 15. The silicon pillars 20 are arranged in a matrix configuration along the X-direction and the Y-direction as viewed from the Z-direction and have a common connection with a single cell source line 15.

Multiple control gate electrode films (the first electrode films) 21 are provided sideward of the silicon pillar 20 to be separated from each other along the Z-direction. Each of the control gate electrode films 21 is made of, for example, tungsten and extends in the Y-direction. Therefore, the control gate electrode films 21 are not disposed between the silicon pillars 20 arranged along the Y-direction. Also, in the X-direction, two of the silicon pillars 20 are arranged alternately with two of the control gate electrode films 21. In other words, when the silicon pillars 20 arranged along the X-direction are organized into multiple sets 22 every two mutually-adjacent silicon pillars 20 and when two of the control gate electrode films 21 are arranged to be positioned between the sets 22, the control gate electrode films 21 are not disposed between the two silicon pillars 20 belonging to each set 22.

An inter-layer insulating film 23 is provided between the silicon pillars 20. An inter-layer insulating film 24 that is made of, for example, silicon oxide is provided between the control gate electrode films 21, below the control gate electrode film 21 of the lowermost layer, and above the control gate electrode film 21 of the uppermost layer. A hard mask 26 is provided on a stacked body 25 that is made of the multiple control gate electrode films 21, the inter-layer insulating film 23, and the inter-layer insulating film 24.

The silicon pillar 20 is drawn out onto the hard mask 26 to be a single body with an interconnect 27 extending in the X-direction. Thereby, the silicon pillars 20 that are arranged along the X-direction are connected to a common interconnect 27. A via 28 is provided on the interconnect 27; and a bit line 29 that extends in the X-direction is provided on the via 28. The bit line 29 is connected to the interconnect 27 by the via 28. Thus, each of the silicon pillars 20 is connected between the bit line 29 and the cell source line 15. In other words, the semiconductor memory device 1 is an I-shaped pillar type stacked memory device.

The Y-direction end portion of the stacked body 25 is patterned into a stairstep configuration; and at the end portion of the stairstep configuration, the multiple control gate electrode films 21 that have the same position in the Z-direction are bundled together. A via 38 is provided on the end portion of the bundled control gate electrode films 21. A word line 39 that extends in the Y-direction is provided on the via 38. In the Z-direction, the position of the word line 39 is the same as the position of the bit line 29. The word line 39 is connected to the control gate electrode film 21 by the via 38.

As shown in FIG. 3 and FIG. 4, floating gate electrode films 31 (second electrode films) that are made of, for example, polysilicon are provided between the silicon pillars 20 and the control gate electrode films 21. Because the floating gate electrode films 31 are provided at each intersection between the silicon pillars 20 and the control gate electrode films 21, the floating gate electrode films 31 are arranged in a matrix configuration to be separated from each other along the Y-direction and the Z-direction. When viewed from the Z-direction, the configuration of the floating gate electrode film 31 is a fan-like shape that is wider on the control gate electrode film 21 side. Therefore, a length L1 in the Y-direction of the end portion of the floating gate electrode film 31 on the silicon pillar 20 side is shorter than a length L2 in the Y-direction of the end portion of the floating gate electrode film 31 on the control gate electrode film 21 side.

A tunneling insulating film 33 that is made of, for example, silicon oxide is provided between the silicon pillar 20 and the floating gate electrode films 31. The tunneling insulating film 33 is provided at each silicon pillar 20; and the configuration of the tunneling insulating film 33 is a band configuration that extends in the Z-direction and has the X-direction as the thickness direction and the Y-direction as the width direction.

On the other hand, a blocking insulating film 34 is provided between the floating gate electrode film 31 and the control gate electrode film 21. The blocking insulating film 34 is, for example, a three-layer film in which a silicon nitride layer 35, a silicon oxide layer 36, and a silicon nitride layer 37 are stacked in this order from the floating gate electrode film 31 side toward the control gate electrode film 21 side. The silicon nitride layer 35 is formed around the floating gate electrode film 31 to cover an upper surface 31a and a lower surface 31b of the floating gate electrode film 31. The silicon oxide layer 36 and the silicon nitride layer 37 are formed around the control gate electrode film 21 to cover an upper surface 21a and a lower surface 21b of the control gate electrode film 21.

Although the tunneling insulating film 33 normally is insulative, the tunneling insulating film 33 is a film in which a tunneling current flows when a voltage within the range of the drive voltage of the semiconductor memory device 1 is applied. The blocking insulating film 34 is a film in which a current substantially does not flow even when a voltage within the range of the drive voltage of the semiconductor memory device 1 is applied. The equivalent oxide thickness (EOT) of the tunneling insulating film 33 is thicker than the equivalent oxide thickness of the blocking insulating film 34; and the dielectric constant of the tunneling insulating film 33 is lower than the dielectric constant of the blocking insulating film.

In the peripheral circuit region Rc as shown in FIG. 2, a source region 40s and a drain region 40d are formed in the silicon substrate 10 to be separated from each other. The region between the source region 40s and the drain region 40d is a channel region 40c. A gate insulating film 41 (a fourth insulating film) that is made of, for example, silicon oxide is provided on the silicon substrate 10 in the region directly above the channel region 40c; and a conductive layer 42 that is made of, for example, polysilicon and an interconnect layer 43 that is made of, for example, tungsten are stacked in this order on the gate insulating film 41. A gate electrode 45 is formed of the conductive layer 42 and the interconnect layer 43. A transistor 46 includes the source region 40s, the drain region 40d, the channel region 40c, the gate insulating film 41, and the gate electrode 45. The transistor 46 is included in the peripheral circuit.

As described below, the insulating film 11 that is in the memory cell region Rm and the gate insulating film 41 that is in the peripheral circuit region Rc are formed by dividing the same silicon oxide film; the conductive layer 12 that is in the memory cell region Rm and the conductive layer 42 that is in the peripheral circuit region Rc are formed by dividing the same polysilicon layer; and the interconnect layer 13 that is in the memory cell region Rm and the interconnect layer 43 that is in the peripheral circuit region Rc are formed by dividing the same tungsten layer.

A method for manufacturing the semiconductor memory device according to the embodiment will now be described.

FIG. 5A to FIG. 17B are plan views and cross-sectional views showing the method for manufacturing the semiconductor memory device according to the embodiment.

Only the memory cell region Rm is shown in FIG. 5A to FIG. 17B.

First, as shown in FIG. 1 and FIG. 2, the channel region 40c, the source region 40s, and the drain region 40d are formed in the upper layer portion of the silicon substrate 10 in the peripheral circuit region Rc. Then, a silicon oxide film is formed on the silicon substrate 10 in both the memory cell region Rm and the peripheral circuit region Rc. Therefore, in the peripheral circuit region Rc, a relatively thin silicon oxide film is formed in the low breakdown voltage transistor (LV Tr) region; and a relatively thick silicon oxide film is formed in the high breakdown voltage transistor (HV Tr) region. Also, a relatively thick silicon oxide film is formed in the memory cell region Rm.

Then, a polysilicon layer is formed on the entire surface. STI (Shallow Trench Isolation) is formed in the upper layer portion of the silicon substrate 10 in the peripheral circuit region Rc using an appropriate mask (not shown). Then, a tungsten layer is formed. Then, a polysilicon layer and a silicon oxide film are formed only in the memory cell region Rm. Then, these layers are patterned by RIE (Reactive Ion Etching).

Thereby, the insulating film 11, the conductive layer 12, the interconnect layer 13, the conductive layer 14, and the insulating film 17 are formed for each block in the memory cell region Rm. The cell source line 15 is formed of the stacked body made of the conductive layer 12, the interconnect layer 13, and the conductive layer 14. Erasing is possible by block unit by forming the cell source line 15 to be divided for each block. On the other hand, the gate insulating film 41, the conductive layer 42, and the interconnect layer 43 are formed in the peripheral circuit region Rc. The gate electrode 45 is formed of the stacked body made of the conductive layer 42 and the interconnect layer 43. Thereby, the transistor 46 is formed in the peripheral circuit region Rc.

Then, as shown in FIGS. 5A and 5B, a silicon oxide film 51 and a silicon nitride film 52 are stacked alternately on the insulating film 17 (referring to FIG. 2) in the memory cell region Rm. Thereby, the stacked body 25 is formed. At this time, because the gate length (the total thickness of the control gate electrode film 21 and the blocking insulating film provided around the control gate electrode film 21) on the electrode side is longer than the gate length (the total thickness of the floating gate electrode film 31 and the blocking insulating film provided around the floating gate electrode film 31) on the channel side, the film thickness ratio of the silicon oxide film 51 and the silicon nitride film 52 that are stacked is adjusted according to the film thickness of the blocking films filled from both sides. FIG. 5A is a cross-sectional view; and FIG. 5B is a top view. This is similar for the following drawings as well.

Continuing as shown in FIGS. 6A and 6B, the hard mask 26 that is made of, for example, silicon nitride is formed on the stacked body 25. Then, the hard mask 26 is patterned; and anisotropic etching such as RIE, etc., of the stacked body 25 is performed using the patterned hard mask 26 as a mask. Thereby, multiple trenches 53 are made in the stacked body 25 to extend in the Y-direction. The trenches 53 pierce the stacked body 25.

Then, as shown in FIGS. 7A and 7B, the silicon nitride films 52 are recessed by performing wet etching via the trench 53. Thereby, the exposed surfaces of the silicon nitride films 52 recede at the inner surface of the trench 53 to make recesses 54 that extend in the Y-direction. Then, oxidation treatment is performed by SPA, etc. Thereby, the exposed surfaces of the silicon nitride films 52 at the inner surface of the trench 53 are covered with a thin silicon oxide layer 50.

Continuing as shown in FIGS. 8A and 8B, the silicon nitride layer 35 is formed on the entire surface. Then, a polysilicon film 55 is formed on the entire surface. The silicon nitride layer 35 and the polysilicon film 55 also are formed on the inner surface of the trench 53 to enter the recesses 54.

Then, as shown in FIGS. 9A and 9B, by performing anisotropic etching such as RIE, etc., along the trench 53, the polysilicon film 55 and the silicon nitride layer 35 are selectively removed to remain inside the recesses 54; and the polysilicon films 55 that remain inside the recesses 54 adjacent to each other in the Z-direction are separated from each other. Similarly, the silicon nitride layers 35 that remain inside the recesses 54 adjacent to each other in the Z-direction also are separated from each other.

Continuing as shown in FIGS. 10A and 10B, the tunneling insulating film 33, a polysilicon film 56, and an insulating film 57 are deposited in this order.

Then, as shown in FIGS. 11A and 11B, trenches 58 are made in the stacked body 25 and the stacked body stacked above the stacked body 25 to extend in the Y-direction between the trenches 53. Thereby, the trenches 53 and the trenches 58 are arranged alternately along the X-direction.

Continuing as shown in FIGS. 12A and 12B, the silicon nitride films 52 are recessed by performing wet etching using hot phosphoric acid via the trench 58. The recessing is stopped by the silicon oxide layer 50 that is exposed at the back surfaces of recesses 59. Thereby, the silicon nitride films 52 are removed; and the recesses 59 are made in the inner surface of the trench 58 to extend in the Y-direction. At this time, the silicon nitride layer 35 is not damaged because the silicon nitride layer 35 is protected by the silicon oxide layer 50.

Then, as shown in FIGS. 13A and 13B, the silicon oxide layer 50 that is exposed at the back surfaces of the recesses 59 is removed. Thereby, the silicon nitride layers 35 are exposed at the back surfaces of the recesses 59. Then, the silicon oxide layer 36 and the silicon nitride layer 37 are formed on the inner surface of the trench 58. As a result, as shown in FIG. 3, the blocking insulating film 34 is formed of the silicon nitride layer 35, the silicon oxide layer 36, and the silicon nitride layer 37. Then, a tungsten film 61 is formed on the entire surface by, for example, CVD (Chemical Vapor Deposition). The silicon oxide layer 36, the silicon nitride layer 37, and the tungsten film 61 also enter the recesses 59 via the trench 58.

Continuing as shown in FIGS. 14A and 14B, the tungsten film 61 is selectively removed by performing anisotropic etching such as RIE, etc. Thereby, the tungsten film 61 is caused to remain inside the recesses 59; and the tungsten films 61 that remain inside the recesses 59 adjacent to each other in the Z-direction are separated from each other. As a result, the control gate electrode films 21 that are made of the tungsten films 61 are formed inside the recesses 59. Subsequently, the inter-layer insulating film 24 is filled into the trench 58; and the upper surface of the inter-layer insulating film 24 is planarized. FIG. 14B is a cross-sectional view along line B-B′ shown in FIG. 14A.

Then, as shown in FIGS. 15A to 15C, a hard mask 62 is formed in which openings 62a are arranged in a matrix configuration along the X-direction and the Y-direction. The configuration of each of the openings 62a is a rectangle with the X-direction as the longitudinal direction; and the openings 62a are arranged intermittently along the Y-direction in the region directly above the polysilicon films 56 and the insulating film 57 between the polysilicon films 56 but are not disposed in the region directly above the inter-layer insulating film 24. Then, the polysilicon film 56 and the insulating film 57 are divided along the Y-direction by performing anisotropic etching such as RIE, etc., using the hard mask 62 and the hard mask 26 as a mask. Thereby, a through-hole 63 is made in the polysilicon film 56 and the insulating film 57 in the region directly under the opening 62a; the portion of the polysilicon film 56 that is formed on the hard mask 26 becomes the interconnect 27; and the portion of the polysilicon film 56 that is divided by the through-hole 63 becomes the silicon pillar 20. FIG. 15B is a plan view along line C-C′ shown in FIG. 15A; and FIG. 15C is a cross-sectional view along line B-B′ shown in FIG. 15A.

Continuing as shown in FIG. 16, the tunneling insulating film 33 and the polysilicon films 55 are selectively removed by performing isotropic etching such as CDE (Chemical Dry Etching), wet etching, etc., via the through-hole 63. Thereby, the tunneling insulating film 33 and the polysilicon films 55 are divided along the Y-direction. The insulating film 57 also is removed. As a result, the floating gate electrode films 31 are formed of the polysilicon films 55. At this time, because the polysilicon films 55 are etched from the silicon pillar 20 side, the length L1 in the Y-direction of the end portion of the floating gate electrode film 31 on the silicon pillar 20 side is shorter than the length L2 in the Y-direction of the end portion of the floating gate electrode film 31 on the control gate electrode film 21 side. On the other hand, at this time, the inter-layer insulating film 24 remains without being removed.

Then, as shown in FIGS. 17A and 17B, the inter-layer insulating film 23 is deposited on the entire surface. The inter-layer insulating film 23 is filled also inside the through-hole 63. The silicon oxide film 51 also becomes a portion of the inter-layer insulating film 23.

Continuing as shown in FIG. 1 and FIG. 2, the vias 28, the vias 38, the bit lines 29, and the word lines 39 are formed. Thus, the semiconductor memory device 1 according to the embodiment is manufactured.

Effects of the embodiment will now be described.

In the embodiment, the floating gate electrode films 31 that are made of polysilicon are provided as charge storage units. Therefore, the data retention characteristics of the memory cells are good; and the erasing operation is fast because the charge that is stored in the floating gate electrode films 31 can be erased by moving electrons instead of holes. The data retention characteristics are even better because the floating gate electrode films 31 are separated from each other.

In the embodiment, because the blocking insulating film 34 is a three-layer film made of the silicon nitride layer 35, the silicon oxide layer 36, and the silicon nitride layer 37, the coupling ratio can be ensured while suppressing the leakage current. Also, the silicon nitride layer 35 is formed from the silicon pillar 20 side in the process shown in FIGS. 8A and 8B; and the silicon oxide layer 36 and the silicon nitride layer 37 are formed from the control gate electrode film 21 side in the process shown in FIGS. 13A and 13B.

Thus, by dividing the three-layer film of the blocking insulating film 34 into two and forming the three-layer film from both sides, compared to the case of forming from only one side, the thickness of the blocking insulating film 34 can be distributed on the two X-direction sides of the floating gate electrode film 31; and the thickness in the Z-direction as an entirety can be reduced. Thereby, the height in the Z-direction of the recesses 54 (referring to FIGS. 8A and 8B) and the recesses 59 (referring to FIGS. 13A and 13B) can be reduced; the bit density of the memory cells in the Z-direction can be increased; and the aspect ratio can be reduced.

In the embodiment, the blocking insulating film 34 is divided for each of the control gate electrode films 21 along the Z-direction. Thereby, the electrons that are stored in the floating gate electrode film 31 can be prevented from propagating through the blocking insulating film 34 and leaking. As a result, the data retention characteristics of the memory cells are good.

In the embodiment, as shown in FIG. 4, the configuration of the floating gate electrode film 31 is a fan-like shape that is wider on the control gate electrode film 21 side. Thereby, the IPD capacitance between the floating gate electrode film 31 and the control gate electrode film 21 can be large; and the coupling ratio can be large.

Although an example is illustrated in the embodiment in which the blocking insulating film 34 is a three-layer film, this is not limited thereto. The layers of the blocking insulating film 34 are not limited to the silicon oxide layer (the SiO₂ layer) and the silicon nitride layers (the Si₃N₄ layers) and may be a high dielectric constant layer such as, for example, an Al₂O₃ layer, a MgO layer, a SrO layer, a SiN layer, a BaO layer, a TiO layer, a Ta₂O₅ layer, a BaTiO₃ layer, a BaZrO layer, a ZrO₂ layer, a Y₂O₃ layer, a ZrSiO layer, a HfAlO layer, a HfSiO layer, a La₂O₃ layer, a LaAlO layer, etc.

Although an example is illustrated in the embodiment in which the floating gate electrode film 31 is formed of polysilicon, the floating gate electrode film 31 is not limited thereto and may be formed of, for example, a metal silicide or a metal.

Although an example is illustrated in the embodiment in which the control gate electrode film 21 is formed of tungsten, the control gate electrode film 21 is not limited thereto and may be formed of, for example, a metal silicide by filling a polysilicon film and subsequently siliciding the polysilicon film.

In the process shown in FIGS. 5A and 5B, the silicon nitride films 52 of the lowermost layer and the uppermost layer may be formed to be thicker than the other silicon nitride films 52. Thereby, the film thicknesses of the selection gate electrode films that are formed below and above the control gate electrode films 21 can be thicker than those of the control gate electrode films 21. As a result, a selection transistor that has a gate length longer than that of the memory cell transistor can be formed.

Several layers of the control gate electrode films 21 provided at the upper portion of the stacked body 25 may be shorted to each other to be used as the selection gate electrode film; and several layers of the control gate electrode films 21 provided at the lower portion of the stacked body 25 may be shorted to each other to be used as the selection gate electrode film. Thereby, a selection transistor that has a gate length longer than that of the memory cell transistor can be formed.

Modification of First Embodiment

A modification of the embodiment will now be described.

FIG. 18 is a cross-sectional view showing a semiconductor memory device according to the modification.

In the semiconductor memory device is according to the modification as shown in FIG. 18, one wide silicon pillar 65 is provided between two floating gate electrode films 31 adjacent to each other in the X-direction. In other words, the inter-layer insulating film 24 is not provided between the two silicon pillars 20 belonging to each of the sets 22; and the two silicon pillars 20 are formed as one body.

In the semiconductor memory device is according to the modification, the two X-direction side portions of the wide silicon pillar 65 are used as distinct channels. Otherwise, the configuration, the manufacturing method, and the effects of the modification are similar to those of the first embodiment described above.

Second Embodiment

A second embodiment will now be described.

FIG. 19 is a cross-sectional view showing a semiconductor memory device according to the embodiment.

As shown in FIG. 19, the semiconductor memory device 2 according to the embodiment differs from the semiconductor memory device 1 (referring to FIG. 1 to FIG. 4) according to the first embodiment described above in that the disposition of the tunneling insulating film 33 and the blocking insulating film 34 is reversed.

In other words, in the semiconductor memory device 2, the blocking insulating film 34 is disposed between the silicon pillar 20 and the floating gate electrode films 31; and the tunneling insulating film 33 is disposed between the floating gate electrode films 31 and the control gate electrode films 21.

Therefore, the components included in the memory cell are arranged in the order of silicon pillar 20-blocking insulating film 34-floating gate electrode film 31-tunneling insulating film 33-control gate electrode film 21.

More specifically, in the semiconductor memory device 2, silicon oxide films 71 are arranged to be separated from each other along the Z-direction; and the floating gate electrode films 31 and the control gate electrode films 21 are provided in the spaces between the mutually-adjacent silicon oxide films 71. Also, the tunneling insulating film 33 is disposed to cover the upper surface and the lower surface of the control gate electrode film 21 and the side surface of the control gate electrode film 21 on the floating gate electrode film 31 side. On the other hand, the blocking insulating film 34 is disposed linearly along the side surface of the silicon pillar 20.

Similarly to the first embodiment, the blocking insulating film 34 may be a multilayered film, e.g., a three-layer film. However, the blocking insulating film 34 is not subdivided between the silicon pillar 20 side and the control gate electrode film 21 side; and the entire blocking insulating film 34 is disposed on the silicon pillar 20 side.

In the semiconductor memory device 2, the lower end portions of the two silicon pillars 20 belonging to the set 22 are connected to each other; and the cell source line 15 is not provided. A source line (not shown) is provided above the stacked body. In other words, the semiconductor memory device 2 is a U-shaped pillar type stacked memory device. Otherwise, the configuration of the embodiment is similar to that of the first embodiment described above.

The basic operations and the read-out method of the semiconductor memory device 2 are similar to those of a normal NAND flash memory; and the polarity of the voltage applied between the silicon pillar 20 and the control gate electrode film 21 in the programming operation and the erasing operation are the reverse of those of a normal NAND flash memory. Thereby, the charge is caused to move into and out of the silicon pillar 20 from the control gate electrode film 21.

A method for manufacturing the semiconductor memory device according to the embodiment will now be described.

FIG. 20A to FIG. 30C are plan views and cross-sectional views showing the method for manufacturing the semiconductor memory device according to the embodiment.

First, as shown in FIGS. 20A and 20B, the insulating film 17 that is made of silicon oxide is formed on the silicon substrate 10 (referring to FIG. 2); and subsequently, a stacked body 73 is formed by alternately stacking the silicon oxide film 71 and a polysilicon film 72. The polysilicon film 72 may be doped with boron (B), may be doped with phosphorus (P), or may not be doped. FIG. 20A is a cross-sectional view; and FIG. 20B is a top view. This is similar for the following drawings as well.

Then, as shown in FIGS. 21A and 21B, multiple trenches 75 are made in the stacked body 73 to extend in the Y-direction by forming a hard mask (not shown) on the stacked body 73, patterning by lithography, and performing anisotropic etching such as RIE, etc., using the patterned hard mask as a mask. The trenches 75 pierce the stacked body 73 in the Z-direction but do not pierce the insulating film 17.

Continuing as shown in FIGS. 22A and 22B, on the inner surface of the trench 75, the blocking insulating film 34 is formed; and subsequently, a polysilicon film 77 is formed. The blocking insulating film 34 and the polysilicon film 77 are formed on the side surface of the trench 75 and on the bottom surface of the trench 75 to be folded back into a U-shaped as viewed from the Y-direction. Accordingly, the relationship between the width of the trench 75 and the film thicknesses of the blocking insulating film 34 and the polysilicon film 77 is set such that such folding back is possible. Then, the inter-layer insulating film 24 is filled into the trench 75 by depositing silicon oxide.

Then, as shown in FIGS. 23A and 23B, trenches 78 are made in the portion of the stacked body 73 between the trenches 75 to extend in the Y-direction by forming a hard mask (not shown) on the stacked body 73, patterning by lithography, and performing anisotropic etching such as RIE, etc., using the patterned hard mask as a mask. The trenches 75 and the trenches 78 are arranged alternately along the X-direction.

Continuing as shown in FIGS. 24A and 24B, wet etching is performed using, for example, TMY (choline aqueous solution). Thereby, the polysilicon films 72 are etched isotropically via the trench 78; and the exposed surfaces of the polysilicon films 72 at the inner surface of the trench 78 are caused to recede. Thereby, recesses 79 are made at the inner surface of the trench 78.

Then, as shown in FIGS. 25A and 25B, the tunneling insulating film 33 is formed by depositing silicon oxide on the inner surface of the trench 78. At this time, the tunneling insulating film 33 is formed also on the inner surfaces of the recesses 79 to contact the polysilicon films 72. The tunneling insulating film 33 may be formed by thermal oxidation of the exposed surfaces of the polysilicon films 72.

Continuing as shown in FIGS. 26A and 26B, a tungsten film 81 is formed inside the trench 78 by, for example, depositing tungsten by CVD. At this time, the tungsten film 81 is filled also into the recesses 79.

Then, as shown in FIGS. 27A and 27B, the portion of the tungsten film 81 that is not filled into the recesses 79 is removed by etching the tungsten film 81. Thereby, the tungsten films 81 that remain inside the recesses 79 are separated from each other between the recesses 79 to become the control gate electrode films 21. Then, the inter-layer insulating film 24 is filled into the trench 78; and the upper surface of the inter-layer insulating film 24 is planarized. Instead of tungsten, silicon may be deposited in the process shown in FIGS. 26A and 26B; and the silicon may be silicided in this process. Thereby, the control gate electrode films 21 are formed of a metal silicide.

Continuing as shown in FIGS. 28A to 28C, through-holes 82 are made in the trench 75 by selectively removing the inter-layer insulating film 24, the polysilicon film 77, and the blocking insulating film 34 by performing anisotropic etching using an appropriate mask. The polysilicon film 77 is divided periodically along the Y-direction by the through-holes 82 to become the silicon pillars 20. FIG. 28A is a cross-sectional view; FIG. 28B is a cross-sectional view along line C-C′ shown in FIG. 28A; and FIG. 28C is a cross-sectional view along line B-B′ shown in FIG. 28A. This is similar for FIGS. 29A to 29C and FIGS. 30A to 30C.

Then, as shown in FIGS. 29A to 29C, the blocking insulating film 34, the polysilicon films 72, and the tunneling insulating film 33 are further removed via the through-holes 82 to be divided along the Y-direction by performing isotropic etching such as CDE, wet etching, etc. Thereby, the polysilicon films 72 that are divided along the Y-direction become the floating gate electrode films 31. At this time, the configuration of the floating gate electrode film 31 becomes a fan-like shape that is wider on the control gate electrode film 21 side according to the conditions of the isotropic etching.

Continuing as shown in FIGS. 30A to 30C, the inter-layer insulating film 24 is filled into the through-holes 82 by, for example, depositing silicon oxide and planarizing the upper surface of the silicon oxide. Then, the vias 28, the vias 38, the source lines, the bit lines 29, and the word lines 39 (referring to FIG. 1 and FIG. 2) are formed by normal methods. Thus, the semiconductor memory device 2 according to the embodiment is manufactured.

Effects of the embodiment will now be described.

In the programming operation and the erasing operation of a NAND memory device, it is necessary for the current to flow in the tunneling insulating film and for the current to not flow easily in the blocking insulating film. To this end, it is necessary for the physical film thickness of the blocking insulating film to be thicker than the physical film thickness of the tunneling insulating film. Accordingly, if the blocking insulating film 34 is to be formed to extend around into the gaps between the silicon oxide films 71, it is necessary to set the spacing between the silicon oxide films 71 to be long in the Z-direction, which obstructs higher integration of the memory cells in the Z-direction. Further, the aspect ratio of the trenches 75 and 78 undesirably increases; and patterning becomes difficult.

If the spacing of the silicon oxide films 71 nevertheless is set to be short, the thickness of the control gate electrode film 21, which is covered with the blocking insulating film 34 at the upper surface and the lower surface of the control gate electrode film 21, becomes shorter than the spacing of the silicon oxide films 71. Accordingly, the interconnect resistance of the control gate electrode film 21 increases; the gate length of the memory cell transistor becomes short; and the characteristics of the memory cell transistor undesirably degrade due to the short channel effect.

Conversely, in the embodiment, the blocking insulating film 34 is formed on the inner surface of the trench 75 in the process shown in FIGS. 22A and 22B. Thus, by forming the blocking insulating film 34 at an early stage, it is no longer necessary for the blocking insulating film 34 to extend around into the gaps between the silicon oxide films 71; and the spacing of the silicon oxide films 71 can be shorter. As shown in FIG. 19, in the embodiment, although the tunneling insulating film 33 extends around into the gaps between the silicon oxide films 71, there are few problems because the tunneling insulating film 33 is thinner than the blocking insulating film 34 as described above. Thus, according to the embodiment, the bit density of the memory cells in the Z-direction can be increased after ensuring the thickness of the control gate electrode film 21; and the aspect ratio can be reduced. Otherwise, the effects of the embodiment are similar to those of the first embodiment described above.

First Modification of Second Embodiment

A first modification of the embodiment will now be described.

FIG. 31 is a cross-sectional view showing a semiconductor memory device according to the modification. In the semiconductor memory device 2a according to the modification as shown in FIG. 31, a charge storage film 85 that is made of an insulative charge storage material is provided instead of the floating gate electrode film 31 that is made of a conductive material. The charge storage film 85 is formed of, for example, silicon nitride. Accordingly, the memory cell of the semiconductor memory device 2a has a MONOS structure. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the second embodiment described above.

Second Modification of Second Embodiment

A second modification of the embodiment will now be described.

FIG. 32 is a cross-sectional view showing a semiconductor memory device according to the modification.

In the semiconductor memory device 2b according to the modification as shown in FIG. 32, the cell source line 15 is provided; and the lower end of the silicon pillar 20 is connected to the cell source line 15. In other words, the semiconductor memory device 2b is an I-shaped pillar type stacked memory device.

To connect the lower end of the silicon pillar 20 to the cell source line 15 when manufacturing the semiconductor memory device 2b according to the modification, it is necessary for the portion of the blocking insulating film 34 formed on the bottom surface of the trench 75 to be removed by etching in the process shown in FIGS. 22A and 22B. However, the etching does not damage the tunneling insulating film 33 because the tunneling insulating film 33 is not yet formed at this time. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the second embodiment described above.

Third Modification of Second Embodiment

A third modification of the embodiment will now be described.

FIG. 33 is a cross-sectional view showing a semiconductor memory device according to the modification.

As shown in FIG. 33, the modification is an example in which the first modification and the second modification described above are combined. Namely, in the semiconductor memory device 2c according to the modification, the charge storage film 85 that is made of an insulative charge storage material is provided; and the lower end of the silicon pillar 20 is connected to the cell source line 15. Accordingly, the semiconductor memory device 2c has a MONOS structure and is the I-shaped pillar type. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the second embodiment and the first and second modifications of the second embodiment described above.

Third Embodiment

A third embodiment will now be described.

FIG. 34 is a cross-sectional view showing a semiconductor memory device according to the embodiment.

Compared to the semiconductor memory device 2 (referring to FIG. 19) according to the second embodiment described above, in the semiconductor memory device 3 according to the embodiment as shown in FIG. 34, an air gap 86 is made between the silicon pillars 20, the control gate electrode films 21, the floating gate electrode films 31, the tunneling insulating films 33, and the blocking insulating films 34. More specifically, the air gap 86 is made between the control gate electrode films 21 adjacent to each other in the Z-direction, between the floating gate electrode films 31 adjacent to each other in the Z-direction, between the silicon pillars 20 adjacent to each other in the Y-direction, between the blocking insulating films 34, between the floating gate electrode films 31, between the tunneling insulating films 33, and between the two silicon pillars 20 adjacent to each other in the X-direction and belonging to the same set 22.

A method for manufacturing the semiconductor memory device according to the embodiment will now be described.

FIGS. 35A and 35B to FIGS. 37A to 37C are plan views and cross-sectional views showing the method for manufacturing the semiconductor memory device according to the embodiment.

FIG. 35A is a cross-sectional view; and FIG. 35B is a plan view. FIG. 36A is a cross-sectional view; FIG. 36B is a cross-sectional view along line C-C′ shown in FIG. 36A; and FIG. 36C is a cross-sectional view along line B-B′ shown in FIG. 36A. This is similar for FIGS. 37A to 37C.

First, as shown in FIGS. 35A and 35B, a stacked body is formed by forming the insulating film 17 made of silicon oxide on the silicon substrate 10 (referring to FIG. 2) and subsequently stacking a silicon nitride film 87 alternately with the polysilicon film 72.

Then, the processes shown in FIGS. 21A and 21B to FIGS. 29A to 29C are implemented. However, in the processes shown in FIGS. 24A and 24B and FIGS. 27A and 27B, a silicon nitride film 88 is filled instead of the inter-layer insulating film 24 made of silicon oxide.

Thereby, as shown in FIGS. 36A to 36C, an intermediate structural body that is similar to the intermediate structural body shown in FIGS. 29A to 29C is made. However, in the intermediate structural body of the embodiment, the silicon nitride films 87 are provided instead of the silicon oxide films 71; and the silicon nitride film 88 is provided instead of the inter-layer insulating film 24.

Then, as shown in FIGS. 37A to 37C, the silicon nitride films 87 and the silicon nitride film 88 are removed by, for example, wet etching. Thereby, the air gap 86 is made in the space where the silicon nitride films 87 and the silicon nitride film 88 were disposed. Thus, the semiconductor memory device 3 according to the embodiment is manufactured.

According to the embodiment, because the air gap 86 is made between the silicon pillars 20, the control gate electrode films 21, the floating gate electrode films 31, the tunneling insulating films 33, and the blocking insulating films 34, the proximity effect can be suppressed; and the breakdown voltage can be increased.

Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the second embodiment described above.

It is possible for the air gap to be made only between the silicon pillars 20 by alternately stacking the silicon oxide film 71 and the polysilicon film 72 instead of the silicon nitride film 87 and the polysilicon film 72 in the process shown in FIGS. 35A and 35B.

Modification of Third Embodiment

A modification of the embodiment will now be described.

FIGS. 38A to 38C are cross-sectional views showing a semiconductor memory device according to the modification.

FIG. 38A is a cross-sectional view; FIG. 38B is a cross-sectional view along line C-C′ shown in FIG. 38A; and FIG. 38C is a cross-sectional view along line B-B′ shown in FIG. 38A.

FIG. 38A is a cross-sectional view along line D-D′ shown in FIG. 38C. This is similar for FIGS. 39A to 39C described below.

As shown in FIGS. 38A to 38C, the semiconductor memory device 3a according to the modification differs from the semiconductor memory device 3 (referring to FIG. 34) according to the third embodiment described above in that a reinforcing member 89 is formed in multiple regions by causing the silicon nitride films 87 and 88 to partially remain. The reinforcing member 89 extends in the Z-direction and is disposed intermittently along the Y-direction inside the semiconductor memory device 3a.

FIGS. 39A to 39C are cross-sectional views showing a method for manufacturing the semiconductor memory device according to the modification.

In the modification as shown in FIGS. 39A to 39C, the through-holes 82 are not made in the region where the reinforcing member 89 is to be formed. Thereby, in the process shown in FIGS. 37A to 37C, the silicon nitride films 87 and 88 remain locally to become the reinforcing member 89 when performing wet etching of the silicon nitride films 87 and 88 via the through-holes 82.

According to the modification, by providing the reinforcing member 89, the mechanical strength of the semiconductor memory device 3a can be ensured; and collapse can be prevented. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the third embodiment described above.

Fourth Embodiment

A fourth embodiment will now be described.

FIG. 40 is a cross-sectional view showing a semiconductor memory device according to the embodiment.

FIG. 41 is a cross-sectional view showing region E shown in FIG. 40.

As shown in FIG. 40 and FIG. 41, the semiconductor memory device 4 according to the embodiment differs from the semiconductor memory device 1 (referring to FIG. 1 to FIG. 4) according to the first embodiment described above in that the blocking insulating film 34 is not disposed between a control gate electrode film 21u of the uppermost level and a floating gate electrode film 31u of the uppermost level; and the control gate electrode film 21u of the uppermost level is connected to the floating gate electrode film 31u of the uppermost level.

The semiconductor memory device according to the embodiment will now be described.

FIG. 42A is a cross-sectional view showing a method for manufacturing the semiconductor memory device according to the embodiment; and FIG. 42B is a plan view.

First, the processes shown in FIGS. 5A and 5B to FIGS. 12A and 12B are implemented.

Then, as shown in FIGS. 42A and 42B, the silicon oxide layer 36 and the silicon nitride layer 37 are formed on the inner surface of the trench 58. Then, a resist material 90 is filled into the trench 58; and a recess 59u of the uppermost level is exposed by the upper surface of the resist material 90 being recessed. Then, the portions of the silicon nitride layer 37, the silicon oxide layer 36, and the silicon nitride layer 35 that are exposed from the resist material 90 are removed by, for example, wet etching. Thereby, the polysilicon film 55 is exposed at the back surface of the recess 59u of the uppermost level. Then, the resist material 90 is removed.

Continuing as shown in FIGS. 13A and 13B, the tungsten film 61 is formed on the inner surface of the trench 58. At this time, the tungsten film 61 contacts the polysilicon film 55 inside the recess 59u of the uppermost level. The subsequent processes are similar to those of the first embodiment described above.

According to the embodiment, the control gate electrode film 21u of the uppermost level and the floating gate electrode film 31u of the uppermost level can be electrically integrated to be used as the selection gate electrode film by causing the control gate electrode film 21u to connect the floating gate electrode film 31u. Thereby, a selection gate transistor can be formed in which the threshold does not fluctuate because charge is not stored.

Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above.

Fifth Embodiment

A fifth embodiment will now be described.

FIG. 43 and FIG. 44 are cross-sectional views showing a semiconductor memory device according to the embodiment.

In the semiconductor memory device 5 according to the embodiment as shown in FIG. 43 and FIG. 44, the multiple silicon pillars 20 are provided and arranged in a matrix configuration along the X-direction and the Y-direction. Each of the silicon pillars 20 has a circular columnar configuration extending in the Z-direction. The tunneling insulating films 33, the floating gate electrode films 31, and the blocking insulating film 34 are provided in circular ring configurations around each of the silicon pillars 20 in order from the inside, i.e., the silicon pillar 20 side. In other words, the floating gate electrode films 31 are provided around the silicon pillar 20 as viewed from the Z-direction.

The tunneling insulating films 33 and the floating gate electrode films 31 are divided in the Z-direction. The silicon oxide films 51 are provided between the stacked bodies having the circular ring configurations made of the tunneling insulating film 33 and the floating gate electrode film 31 in the Z-direction. In the floating gate electrode film 31, a polysilicon layer 91 is disposed on the inner side; and a metal silicide layer 92 is disposed on the outer side. The metal silicide layer 92 is formed of a metal silicide but may be formed of a metal.

In the blocking insulating film 34, a silicon oxide layer 93 is disposed on the inner side; and high dielectric constant layers 94 are disposed on the outer side. The high dielectric constant layers 94 are made of a material having a higher dielectric constant than silicon oxide, for example, hafnium (Hf), aluminum oxide (AlO), titanium nitride (TiN), tantalum nitride (TaN), or tantalum oxide (TaO). The silicon oxide layer 93 is provided continuously in a tubular configuration in the Z-direction. However, the diameter of the tube fluctuates periodically such that the diameter of the portions corresponding to the floating gate electrode films 31 is relatively small and the diameter of the portions corresponding to the silicon oxide films 51 is relatively large. Therefore, the silicon oxide layer 93 has a circular tubular bellows-like configuration. The high dielectric constant layers 94 are disposed inside recesses 93a at the outer surface of the circular tubular bellows-like configuration made of the silicon oxide layer and are divided for each of the recesses 93a. The configuration of the blocking insulating film 34 is not limited to the two-layer structure made of the silicon oxide layer 93 and the high dielectric constant layers 94. For example, the configuration may be a combination of any layer of a silicon oxide layer (a SiO₂ layer), a silicon nitride layer (a Si₃N₄ layer), an Al₂O₃ layer, a MgO layer, a SrO layer, a SiN layer, a BaO layer, a TiO layer, a Ta₂O₅ layer, a BaTiO₃ layer, a BaZrO layer, a ZrO₂ layer, a Y₂O₃ layer, a ZrSiO layer, a HfAlO layer, a HfSiO layer, a La₂O₃ layer, a LaAlO layer, etc.

In the semiconductor memory device 5, the multiple control gate electrode films 21 are provided to be arranged in a matrix configuration along the X-direction and the Z-direction. The control gate electrode films 21 have band configurations extending in the Y-direction. The control gate electrode film 21 is a conductive film, e.g., a two-layer film made of a titanium nitride layer (TiN) and a tungsten layer (W), a two-layer film made of a tungsten nitride layer (WN) and a tungsten layer (W), or a two-layer film made of a tantalum nitride layer (TaN) and a tungsten layer (W). However, the configuration of the control gate electrode film 21 is not limited thereto; and, for example, a metal silicide layer formed by siliciding a polysilicon film may be used.

The structural body that is made of the silicon pillar 20, the tunneling insulating film 33, the floating gate electrode films 31, and the blocking insulating film 34 pierces the control gate electrode films 21. The control gate electrode films 21 are disposed in the recesses 93a. In other words, the control gate electrode films 21 are provided around the floating gate electrode films 31 as viewed from the Z-direction. The inter-layer insulating film 24 is provided between the structural bodies made of the silicon pillar 20, the tunneling insulating film 33, the floating gate electrode films 31, the blocking insulating film 34, and the control gate electrode films 21.

A method for manufacturing the semiconductor memory device according to the embodiment will now be described.

FIG. 45 to FIG. 53 are cross-sectional views showing the method for manufacturing the semiconductor memory device according to the embodiment.

First, similarly to the first embodiment described above, the insulating film 11, the cell source line 15, and the insulating film 17 (referring to FIG. 1 and FIG. 2) are formed on the silicon substrate 10.

Then, as shown in FIG. 45, the stacked body 60 is formed by alternately stacking the silicon oxide film 51 and the silicon nitride film 52.

Continuing, multiple memory holes 95 are made in the stacked body 60. The memory holes 95 extend in the Z-direction and pierce the stacked body 60 and the insulating film 17 (referring to FIG. 2) to reach the cell source line 15.

Then, as shown in FIG. 46, the exposed surfaces of the silicon nitride films 52 at the inner surface of the memory hole 95 are caused to recede by performing wet etching. Thereby, recesses 96 having annular configurations are made in the inner surface of the memory hole 95.

Continuing as shown in FIG. 47, the polysilicon layers 91 are filled into the recess 96 by depositing polysilicon and selectively removing the polysilicon by performing isotropic etching. Then, the tunneling insulating films 33 are formed by oxidizing the exposed surfaces of the polysilicon layers 91.

Then, as shown in FIG. 48, the silicon pillar 20 is formed by filling polysilicon into the memory hole 95. The silicon pillar 20 is connected to the cell source line 15 (referring to FIG. 2).

Continuing as shown in FIG. 49, a trench 97 is made in the portion of the stacked body 60 between the memory holes 95. The trench 97 spreads in the Y-direction and the Z-direction, and pierces the stacked body 60 in the Z-direction but does not pierce the insulating film 17 (referring to FIG. 2).

Then, as shown in FIG. 50, the silicon nitride films 52 are removed by performing wet etching via the trench 97. Thereby, recesses 98 are made at the inner surface of the trench 97. The polysilicon layers 91 are exposed at the back surfaces of the recesses 98.

Continuing as shown in FIG. 51, the exposed surfaces of the polysilicon layers 91 inside the recesses 98 are silicided by siliciding via the trench 97 and the recesses 98. Thereby, the metal silicide layers 92 are formed. The floating gate electrode film 31 includes the polysilicon layer 91 and the metal silicide layer 92.

Then, as shown in FIG. 52, the silicon oxide layer 93 is formed on the inner surface of the trench 97. Then, the high dielectric constant layer 94 is formed on the silicon oxide layer 93. The silicon oxide layer 93 and the high dielectric constant layer 94 have circular tubular bellows-like configurations reflecting the recesses 98.

Continuing as shown in FIG. 53, a conductive film 99 is formed on the high dielectric constant layer 94 by depositing a conductive material by, for example, CVD. The conductive film 99 also is filled into the recesses 98 but is formed such that the trench 97 is not filled.

Then, as shown in FIG. 43 and FIG. 44, the conductive film 99 and the high dielectric constant layer 94 are recessed by performing isotropic etching such that the conductive film 99 and the high dielectric constant layer 94 remain only inside the recesses 93a of the silicon oxide layer 93. Thereby, the conductive films 99 that remain inside the recesses 93a become the control gate electrode films 21. Also, the blocking insulating film 34 is formed of the silicon oxide layer 93 and the remaining portion of the high dielectric constant layer 94. Thus, the semiconductor memory device 5 according to the embodiment is manufactured.

Effects of the embodiment will now be described.

According to the embodiment, memory cells having good controllability can be realized because the control gate electrode films 21 are provided around the floating gate electrode films 31 and the silicon pillar 20.

The programming characteristics are good because the floating gate electrode films 31 are formed of conductors. Also, because the floating gate electrode films 31 are separated from each other, the movement of the charge is suppressed; and the data retention characteristics are high. The erasing characteristics are good because the erasing operations can be implemented by FN erasing or assisted erasing from the floating gate electrode films 31.

In the embodiment, it is unnecessary to remove the tunneling insulating film 33 formed on the bottom surface of the memory hole 95 by etching because the silicon pillar 20 is connected to the cell source line 15 (referring to FIG. 2) because the tunneling insulating film 33 is formed in the process shown in FIG. 47 prior to forming the silicon pillar 20 in the process shown in FIG. 48. Therefore, the tunneling insulating films that are formed on the side surface of the memory hole 95 are not damaged by the etching.

Otherwise, the configuration, the manufacturing method, the operations, and the effects of the embodiment are similar to those of the first embodiment described above. Although an I-shaped pillar type device is illustrated in the embodiment, a U-shaped pillar type device may be used similarly to the first modification of the second embodiment described above.

Modification of Fifth Embodiment

A modification of the fifth embodiment will now be described.

FIG. 54 is a cross-sectional view showing a semiconductor memory device according to the modification.

As shown in FIG. 54, the modification is an example in which the fourth embodiment and the fifth embodiment described above are combined. Namely, the semiconductor memory device 5a according to the modification differs from the semiconductor memory device 5 (referring to FIG. 43) according to the fifth embodiment described above in that the blocking insulating film 34 is not disposed between the control gate electrode film 21u of the uppermost level and the floating gate electrode film 31u of the uppermost level; and the control gate electrode film 21u of the uppermost level is connected to the floating gate electrode film 31u of the uppermost level. However, the level at which the control gate electrode film 21 is connected to the floating gate electrode film 31 is not limited to the uppermost level and may be multiple levels including the uppermost level.

A method for manufacturing the semiconductor memory device according to the modification will now be described.

FIG. 55 to FIG. 57 are cross-sectional views showing the method for manufacturing the semiconductor memory device according to the modification.

First, the processes shown in FIG. 45 to FIG. 52 are implemented.

Then, as shown in FIG. 55, the resist material 90 is filled into the trench 97 and recessed from the upper surface side by exposing. Thereby, the recess 93a of the uppermost level is exposed from the resist material 90. Although the recesses 93a of multiple levels including the uppermost level may be exposed at this time, in the description hereinbelow, an example is described in which only the recess 93a of the uppermost level is exposed.

Continuing as shown in FIG. 56, the portions of the high dielectric constant layer 94 and the silicon oxide layer 93 exposed from the resist material 90 are removed by performing isotropic etching such as, for example, wet etching, etc. Thereby, the metal silicide layer 92 is exposed at the back surface of the recess 93a of the uppermost level.

Then, as shown in FIG. 57, the resist material 90 is removed.

Continuing, the process shown in FIG. 53 is implemented. Thus, the semiconductor memory device 5a according to the modification can be manufactured.

According to the modification, similarly to the fourth embodiment described above, the control gate electrode film 21u and the floating gate electrode film 31u of the uppermost level can be electrically integrated to be used as the selection gate electrode film. As a result, a selection gate transistor can be formed in which the threshold does not fluctuate. Otherwise, the configuration, the manufacturing method, the operations, and the effects of the modification are similar to those of the fifth embodiment described above.

According to the embodiments described above, a semiconductor memory device having good data retention characteristics and a method for manufacturing the semiconductor memory device can be realized.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. Additionally, the embodiments described above can be combined mutually.

Claims

1. A semiconductor memory device, comprising:

a substrate;

a semiconductor pillar provided on the substrate to extend in a vertical direction;

a plurality of first electrode films provided sideward of the semiconductor pillar to extend in a first direction, the plurality of first electrode films being disposed to be separated from each other along the vertical direction;

a plurality of second electrode films provided between the semiconductor pillar and the first electrode films, the plurality of second electrode films being disposed to be separated from each other along the vertical direction;

a first insulating film provided between the semiconductor pillar and the second electrode films; and

a second insulating film provided between the second electrode film and the first electrode film.

2. The device according to claim 1, wherein

an equivalent oxide thickness of the first insulating film is thicker than an equivalent oxide thickness of the second insulating film, and

a dielectric constant of the first insulating film is lower than a dielectric constant of the second insulating film.

3. The device according to claim 2, wherein the second insulating film includes:

a first layer provided on the first electrode film side to cover an upper surface and a lower surface of the first electrode film; and

a second layer provided on the second electrode film side to cover an upper surface and a lower surface of the second electrode film.

4. The device according to claim 1, wherein

an equivalent oxide thickness of the second insulating film is thicker than an equivalent oxide thickness of the first insulating film, and

a dielectric constant of the second insulating film is lower than a dielectric constant of the first insulating film.

5. The device according to claim 4, wherein the first insulating film is disposed along a side surface of the semiconductor pillar.

6. The device according to claim 1, wherein

a plurality of the semiconductor pillars are provided,

the plurality of semiconductor pillars is arranged in a matrix configuration along the first direction and a second direction intersecting the first direction as viewed from above,

the first electrode film is not disposed between the semiconductor pillars arranged along the first direction, and

when the semiconductor pillars arranged along the second direction are organized into sets every two mutually-adjacent semiconductor pillars and when two of the first electrode films are positioned between the sets, the first electrode films are not disposed between the two semiconductor pillars belonging to each set.

7. The device according to claim 6, wherein the two semiconductor pillars belonging to the set are formed as one body.

8. The device according to claim 6, wherein a length in the first direction of an end portion of the second electrode film on the semiconductor pillar side is shorter than a length in the first direction of an end portion of the second electrode film on the first electrode film side.

9. The device according to claim 6, wherein an air gap is made in at least one location between the semiconductor pillars, between the first electrode films adjacent to each other in the vertical direction, and/or between the second electrode films adjacent to each other in the vertical direction.

10. The device according to claim 1, wherein the second electrode films are provided around the semiconductor pillar as viewed from above, and the first electrode films are provided around the second electrode films as viewed from above.

11. The device according to claim 1, wherein the second insulating film is not disposed between the first electrode film and the second electrode film for the uppermost level or for a plurality of levels including the uppermost level, and the first electrode film is connected to the second electrode film for the uppermost level or for the plurality of levels including the uppermost level.

12. The device according to claim 1, wherein the second insulating film is divided along the vertical direction for each of the first electrode films.

13. The device according to claim 1, further comprising:

a cell source line provided between the substrate and the semiconductor pillar to be connected to a lower end of the semiconductor pillar;

a bit line provided on the semiconductor pillar to be connected to an upper end of the semiconductor pillar;

a third insulating film provided between the substrate and the cell source line;

a source region and a drain region formed to be separated from each other in a region of the substrate distal to a region directly under the semiconductor pillar;

a fourth insulating film provided in a region directly above a region of the substrate between the source region and the drain region; and

a gate electrode provided on the fourth insulating film.

14. A method for manufacturing a semiconductor memory device, comprising:

forming a stacked body on a substrate by alternately stacking an insulating film and a first film;

making a first trench in the stacked body to extend in a first direction;

making a first recess by causing an exposed surface of the first film at an inner surface of the first trench to recede;

forming a first insulating layer on the inner surface of the first trench;

forming a first conductive film on the first insulating layer;

removing a part of the first conductive film and a part of the first insulating layer located outside the first recess by etching and remaining another part of the first conductive film and another part of the first insulating layer located inside the first recess;

forming a first insulating film on the inner surface of the first trench;

forming a semiconductor film on the first insulating film;

making a second trench in the stacked body between the first trenches to extend in the first direction;

making a second recess by removing the first film via the second trench;

forming a second insulating layer on an inner surface of the second recess;

forming a second conductive film inside the second recess; and

dividing the semiconductor film and the first conductive film along the first direction,

an equivalent oxide thickness of a second insulating film made of the first insulating layer and the second insulating layer being thinner than an equivalent oxide thickness of the first insulating film, a dielectric constant of the second insulating film being higher than a dielectric constant of the first insulating film.

15. The method according to claim 14, further comprising filling an inter-layer insulating film into the first trench after the forming of the semiconductor film and prior to the making of the second trench,

the making of the first trench including: forming a first mask on the stacked body in a line-and-space configuration extending in the first direction; and performing anisotropic etching using the first mask,

the dividing of the semiconductor film and the first conductive film along the first direction including: forming a second mask on the first mask in a line-and-space configuration extending in a second direction intersecting the first direction; making a through-hole by selectively removing the inter-layer insulating film and the semiconductor film by performing anisotropic etching using the second mask and the first mask; and performing isotropic etching of the first conductive film via the through-hole.

16. The method according to claim 14, further comprising forming a second film on a back surface of the first recess after the making of the first recess and prior to the forming of the first insulating layer, the second film being made of a material different from a material of the first film,

the making of the second recess including removing the first film using the second film as a stopper.

17. A method for manufacturing a semiconductor memory device, comprising:

forming a stacked body on a substrate by alternately stacking an insulating film and a first conductive film;

making a first trench in the stacked body to extend in a first direction;

forming a first insulating film on an inner surface of the first trench;

forming a semiconductor film on the first insulating film;

making a second trench in the stacked body between the first trenches to extend in the first direction;

making a recess by causing an exposed surface of the first conductive film at an inner surface of the second trench to recede;

forming a second insulating film on an inner surface of the recess, an equivalent oxide thickness of the second insulating film being thicker than an equivalent oxide thickness of the first insulating film, a dielectric constant of the second insulating film being lower than a dielectric constant of the first insulating film;

forming a second conductive film inside the recess; and

dividing the semiconductor film and the first conductive film along the first direction.