Patents by Inventor Tatsuya Kato

Tatsuya Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210221033
    Abstract: A manufacturing method of a structure by which a target member can be easily positioned with high accuracy. In a tilting step, at least one target member is positioned by tilting a positioning table and sliding the target member placed on the positioning table to bring the target member into contact with a locking portion.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 22, 2021
    Applicant: KYORAKU CO., LTD.
    Inventors: Hisanao HATO, Tadatoshi TANJI, Takeshi KATO, Tatsuya FUKUDA, Yuki HARASAWA
  • Patent number: 11049868
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Nagashima, Tatsuya Kato, Wataru Sakamoto
  • Patent number: 11018148
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: May 25, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Wataru Sakamoto, Tatsuya Kato
  • Publication number: 20210061860
    Abstract: An object of the present invention is to provide methods of discovering drugs effective for tough targets, which have conventionally been discovered only with difficulty. The present invention relates to novel methods for cyclizing peptide compounds, and novel peptide compounds and libraries comprising the same, to achieve the above object.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 4, 2021
    Applicant: Chugai Seiyaku Kabushiki Kaisha
    Inventors: Shiori KARIYUKI, Takeo Ilda, Miki Kojima, Ryuichi Takeyama, Mikimasa Tanada, Tetsuo Kojima, Hitoshi Ilkura, Atsushi Matsuo, Takuya Shiraishi, Takashi Emura, Kazuhiko Nakano, Koji Takano, Kousuke Asou, Takuya Torizawa, Ryusuke Takano, Nozomi Hisada, Naoaki Murao, Atsushi Ohta, Kaori Kimura, Yusuke Yamagishi, Tatsuya Kato
  • Patent number: 10910392
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Publication number: 20200357810
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru SAKAMOTO, Ryota SUZUKI, Tatsuya OKAMOTO, Tatsuya KATO, Fumitaka ARAI
  • Publication number: 20200319814
    Abstract: An integrated circuit for allowing a band of an external memory to be effectively used in processing a layer algorithm is disclosed. One aspect of the present disclosure relates to an integrated circuit including a first arithmetic part including a first arithmetic unit and a first memory, wherein the first arithmetic unit performs an operation and the first memory stores data for use in the first arithmetic unit and a first data transfer control unit that controls transfer of data between the first memory and a second memory of a second arithmetic part including a second arithmetic unit, wherein the second arithmetic part communicates with an external memory via the first arithmetic part.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 8, 2020
    Inventors: Tatsuya KATO, Ken NAMURA
  • Patent number: 10763272
    Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Ryota Suzuki, Tatsuya Okamoto, Tatsuya Kato, Fumitaka Arai
  • Patent number: 10686045
    Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto
  • Patent number: 10650900
    Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shimada, Fumitaka Arai, Tatsuya Kato
  • Patent number: 10650894
    Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer pr
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kato, Yusuke Shimada, Fumitaka Arai
  • Patent number: 10636803
    Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Kohei Sakaike, Satoshi Nagashima
  • Publication number: 20200090752
    Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer pr
    Type: Application
    Filed: March 7, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya KATO, Yusuke SHIMADA, Fumitaka ARAI
  • Publication number: 20200051991
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Patent number: 10541311
    Abstract: In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Katsuyuki Sekine, Tatsuya Kato, Fumitaka Arai, Toshiyuki Iwamoto, Yuta Watanabe, Atsushi Murakoshi
  • Patent number: 10497709
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Patent number: 10438959
    Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
  • Publication number: 20190294140
    Abstract: A work condition visualization apparatus includes an input unit that accepts an input of an instruction to specify whether to operate a machine in manual operation work or in accordance with a program, and an output unit that outputs time information on the manual operation work and time information on the program on the basis of an instruction accepted by the input unit.
    Type: Application
    Filed: November 16, 2016
    Publication date: September 26, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ken INUKAI, Tatsuya KATO
  • Publication number: 20190186929
    Abstract: Route search devices, systems, and programs obtain current traffic information indicating traffic conditions at a present time and obtain statistical traffic information, the statistical traffic information being statistical information obtained by collecting statistics of histories of traffic information. The devices, systems, and programs determine a degree of traffic congestion of a road at the present time, identify travel time for a road whose degree of traffic congestion is greater than or equal to a threshold, based on the current traffic information, and identify travel time for a road whose degree of traffic congestion is less than the threshold, based on the statistical traffic information. The devices, systems, and programs then search for a route to a destination, using the identified travel time.
    Type: Application
    Filed: September 1, 2017
    Publication date: June 20, 2019
    Applicants: AISIN AW CO., LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tominori IWATA, Daisuke TANIZAKI, Kenji NAGASE, Toyoji HIYOKAWA, Tatsuya KATO, Motohiro NAKAMURA, Kazunori WATANABE
  • Patent number: D864952
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoya Tsukamoto, Ken Inukai, Tatsuya Kato, Kiyohito Oda