FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE AND INTERFACE STATE DENSITY IN A MULTIGATE DEVICE
A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
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The present disclosure relates generally to multigate devices and relates more specifically to fabrication processes for lowering interface states of multigate devices.
BACKGROUND OF THE DISCLOSUREA multigate device or multiple gate field effect transistor (MuGFET) is a metal-oxide-semiconductor field effect transistor (MOSFET) that incorporates more than one gate into a single device.
One particular type of multigate device is the finFET, which refers to a nonplanar, multi-gate transistor built on a silicon-on-insulator (SOI) substrate and based on the earlier DELTA (single-gate) transistor design. A distinguishing characteristic of the finFET is a conducting channel in a thin silicon “fin,” which forms the body of the device.
Another type of multigate device is the tri-gate or three-dimensional (3D) transistor (not to be confused with a 3D microchip) fabrication used for the nonplanar transistor architecture used in certain processors (e.g., processors based on the 22 nanometer manufacturing process). Tri-gate transistors employ a single gate stacked on top of two vertical gates, creating additional surface area for carriers to travel.
The performance of finFET and tri-gate devices is severely limited by high external resistance (Rext) and interface state density (Dit). Rext is difficult to solve in III-V types of finFET and tri-gate devices, owing to the difficulty in forming high-quality contacts due to limited thermal budget of processing. Dit is also difficult to solve in III-V types of finFET and tri-gate devices, owing to a high concentration of interface states at the oxide/semiconductor interface.
SUMMARY OF THE DISCLOSUREA method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
In another embodiment, a method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin comprising a III-V compound, growing a first conformal epitaxial layer comprising a first semiconductor material directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped, growing a second conformal epitaxial layer comprising a second semiconductor material directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is doped more highly than the first conformal epitaxial layer and is thicker than the first conformal epitaxial layer, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
In another embodiment, a multigate device includes a fin formed on a substrate, the fin comprising a semiconductor material, a first conformal epitaxial layer grown directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped, a second conformal epitaxial layer grown directly on a portion of the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, a trench formed in the second conformal epitaxial layer, and a gate formed within the trench.
The teachings of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the Figures.
DETAILED DESCRIPTIONIn one embodiment, the present invention is a method and apparatus for fabricating a multigate device having a relatively low external resistance (Rext) and relatively low interface state density (Dit). Embodiments of the invention grow two different conformal epitaxial layers on the fins of a multigate device (e.g., a finFET or trigate device). One of the epitaxial layers is a highly doped layer, while the other epitaxial layer is a thin cap layer grown to mitigate interface state density. Subsequent processing steps leave the cap layer, but selectively remove the highly doped layer from the device channel areas. Portions of the highly doped layer remain in the source and drain regions of the device.
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The steps illustrated in 1A-1H, 2A-2G, and 3A-3H result in a conformal, highly doped epitaxial growth on the fins 104 of the multigate device 100. This lowers the contact resistance of the multigate device. Thus, the disclosed fabrication process, including the deposition and selective removal of at least one epitaxial layer, lowers the external resistance and interface state density of multigate devices with minimal processing complexity.
Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.
Claims
1. A method for fabricating a multigate device, the method comprising:
- forming a fin on a substrate of the multigate device, the fin comprising a semiconductor material;
- growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped;
- growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped;
- selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench; and
- forming a gate within the trench.
2. The method of claim 1, wherein the semiconductor material is a III-V compound.
3. The method of claim 2, wherein the III-V compound is indium gallium arsenide.
4. The method of claim 1, wherein the first conformal epitaxial layer is a cap layer.
5. The method of claim 4, wherein the first conformal epitaxial layer has a thickness of approximately two to five nanometers.
6. The method of claim 4, wherein the first conformal epitaxial layer comprises indium phosphide.
7. The method of claim 1, wherein the second conformal epitaxial layer has a thickness of at least approximately twenty nanometers.
8. The method of claim 1, wherein the second conformal epitaxial layer comprises indium gallium arsenide.
9. The method of claim 1, wherein the second conformal epitaxial layer is at least four times thicker than the first conformal epitaxial layer.
10. The method of claim 1, further comprising:
- depositing an insulator layer directly on the second conformal epitaxial layer, prior to the selectively removing, wherein at least a portion of the insulator layer is removed with the portion of the second epitaxial layer.
11. The method of claim 1, wherein the trench is formed along approximately a center axis of the multigate device and extends from a first end of the multigate device to a second end of the multigate device.
12. The method of claim 1, wherein the forming a gate comprises:
- depositing a dielectric layer on the multigate device;
- forming a dielectric spacer within the trench;
- depositing a gate metal layer directly on the dielectric layer and the dielectric spacer, including within the trench; and
- forming a source contact and a drain contact directly on the portion of the second conformal epitaxial layer.
13. A method for fabricating a multigate device, the method comprising:
- forming a fin on a substrate of the multigate device, the fin comprising a III-V compound;
- growing a first conformal epitaxial layer comprising a first semiconductor material directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped;
- growing a second conformal epitaxial layer comprising a second semiconductor material directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is doped more highly than the first conformal epitaxial layer and is thicker than the first conformal epitaxial layer;
- selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench; and
- forming a gate within the trench.
14. The method of claim 13, wherein the first semiconductor material comprises indium phosphide.
15. The method of claim 13, wherein the second semiconductor material comprises indium gallium arsenide.
16. The method of claim 13, wherein the second conformal epitaxial layer is at least four times thicker than the first conformal epitaxial layer.
17. The method of claim 13, wherein the trench is formed along approximately a center axis of the multigate device and extends from a first end of the multigate device to a second end of the multigate device.
18. A multigate device, comprising:
- a fin formed on a substrate, the fin comprising a semiconductor material;
- a first conformal epitaxial layer grown directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped;
- a second conformal epitaxial layer grown directly on a portion of the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped;
- a trench formed in the second conformal epitaxial layer; and
- a gate formed within the trench.
19. The multigate device of claim 18, wherein the semiconductor material is a III-V compound.
20. The multigate device of claim 18, wherein the second conformal epitaxial layer is at least four times thicker than the first conformal epitaxial layer.
Type: Application
Filed: Mar 5, 2014
Publication Date: Sep 10, 2015
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: ANIRBAN BASU (Elmsford, NY), Guy Cohen (Mohegan Lake, NY), Amlan Majumdar (White Plains, NY)
Application Number: 14/197,746