PIXELATED SILICON CELLS OR INTEGRATED CIRCUITS
A method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps.
This application is a Division of and claims priority to U.S. Non-Provisional patent application Ser. No. 14/158,931 filed on Jan. 20, 2014 and entitled “PIXELATED SILICON CELLS OR INTEGRATED CIRCUITS”, the entirety of which is incorporated herein by reference.
STATEMENT OF GOVERNMENT RIGHTSThis invention was developed under Contract DE-AC04-94AL85000 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.
FIELDPixelated silicon cells or integrated circuits.
BACKGROUNDThe adoption of photovoltaics for generating electricity from sunlight is largely driven by cost considerations. At present, photovoltaic systems are not competitive with fossil-fuel generated electricity. Thus, there is a need to reduce the overall photovoltaic system cost. This generally entails reducing the costs associated with photovoltaic solar cell fabrication.
One way to reduce costs is to reduce a size of the photovoltaic solar cells. In this aspect, small and thin photovoltaic cells have been developed that reduce photovoltaic material use dramatically. These thin photovoltaic cells are typically formed on top of a handle wafer. Once formed, the cells may be individually detached from the handle wafer by, for example, an etching process using a hydrofluoric acid (HF) solution to undercut the cells. These “free floating” cells may then be assembled into sheets by attracting the individual cells to a desired position on a sheet of material using self-assembly techniques. Finally, the cells may be embedded in a low-cost substrate with, for example, contacts and microlenses to form photovoltaic sheets.
SUMMARYA method, apparatus and system for flexible, ultra-thin, and high efficiency pixelated silicon or other semiconductor photovoltaic solar cell array fabrication is disclosed. A structure and method of creation for a pixelated silicon or other semiconductor photovoltaic solar cell array with interconnects is described using a manufacturing method that is simplified compared to previous versions of pixelated silicon photovoltaic cells that require more microfabrication steps. A method to create interconnected arrays of cells or integrated circuits with a stealth dicing operation used in a unique manner, a die saw, or a deep reactive ion etch (DRIE) for pixelating the die is also described. A structure operable for creating pixelated arrays of cells or integrated circuits using a germanium layer for either wet chemical (etch) release or for a laser lift-off approach when combined with silicon handle and device layers is further described. These techniques can be used to create either dense arrays of nearly 100% fill factor or sparse arrays of silicon cells or integrated circuits. The methods and structures described provide significant advantages over existing technologies for flexible or concentrated photovoltaic modules as well as for various applications of flexible electronics.
The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment of the invention in this disclosure are not necessarily to the same embodiment, and they mean at least one. In the drawings:
In this section we shall explain several preferred embodiments of this invention with reference to the appended drawings. Whenever the shapes, relative positions, and other aspects of the parts described in the embodiments are not clearly defined, the scope of the invention is not limited only to the parts shown, which are meant merely for the purpose of illustration. Also, while numerous details are set forth, it is understood that some embodiments of the invention may be practiced without these details. In other instances, well-known structures and techniques have not been shown in detail so as not to obscure the understanding of this description.
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In one embodiment, a second side 120 of a device layer 100 is rough so that the surface is less reflective and scatters light within the cell, increasing the surface incidence angles, thus leading to light trapping within the cell by total internal reflection. In addition, a second passivation layer 250 with anti-reflective properties may be used to help reduce light reflection away from the device cells 210. This is important because, in embodiments where the device cell 210 has photovoltaic properties, for example, a solar cell, it is desirable for light contacting the solar cell to enter the device and not be reflected away. A dielectric layer 150 or passivation layer 250 may be made of material that is transparent to the wavelength of light of interest. The thickness and index of the passivation layer 250 are selected to use optical interference effects to force light into the cell rather than be reflected by it. The passivation/anti-reflection layer 250 may be comprised of a single material. Silicon nitride is a commonly used anti-reflection and passivation material for silicon solar cells. The passivation/anti-reflection layer 250 can also be a multi-layer stack such as a thin amorphous silicon layer for passivation followed by a silicon nitride layer to provide anti-reflection capability. The passivation/anti-reflection layers 250 can be deposited by a variety of means such as sputtering, atomic layer deposition, electron beam evaporation, chemical vapor deposition, wet chemical reactions, thermal material growth, and others.
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In another embodiment, a polymer layer 230 may already have conductive elements 260 implanted onto the polymer layer 230 before the polymer layer 230 is transferred to the device cells 210 or a portion of the conductive elements 260 can be created before transferring polymer layer 230 to the device cells 210 with the final portions of the conductive elements 260 put into place subsequently. This embodiment may be more cost-effective in that it further simplifies the process.
In another embodiment, a passivation layer 270 may be deposited onto the exposed conductive elements 260 and polymer layer 230. The passivation layer 270 could be comprised of dielectric materials, semiconductor materials, and the like. It may be formed by spin coating, spray coating, sputtering, or chemical vapor deposition.
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On the first side 340 of the silicon handle wafer 320 there exists a first dielectric layer 380. The first dielectric layer 380 may be any suitable oxide, nitride, or combination thereof The first dielectric layer 380 is preferably 0.1-5 microns thick. The first dielectric layer 380 may also not exist. On top of the first dielectric layer 380 is a germanium layer 310, which may be crystalline, poly-crystalline, or amorphous. In one embodiment, the germanium layer 310 is preferably 0.1-5 microns thick. On top of the germanium layer 310 is a second dielectric layer 390 that may be any suitable oxide, nitride, or combination thereof In one embodiment, the second dielectric layer 390 may be 100 nm thick. In another embodiment, the second dielectric layer 390 may not exist. On top of the second dielectric layer 390 are device cells 400. The device cells or die 400 may be made of silicon. On top of each device cell 400 is a layer of metallized contacts 410 which in many instances would have electrically isolated regions defined in the metal layer (not indicated in
In one embodiment, individual device cells 400 may be released from the handle wafer 320 by directing electromagnetic radiation 420 from the second side 350 of the handle wafer 320, through the handle wafer 320 at the location of each device cell. In one embodiment, the electromagnetic radiation 420 has a wavelength selective for removing the germanium 310 relative to the silicon device cell 400 and the silicon handle wafer 320. Where the handle wafer 320 is silicon, the preferred wavelength of the electromagnetic radiation 420 is between 1100-1600 nanometers. This wavelength range is desirable due to the fact that these wavelengths are transparent to silicon but are absorbed by germanium. The electromagnetic radiation 420 is directed through the silicon handle wafer 320 into a germanium layer 310 near the location of the device cell 400. The light is absorbed by the germanium layer 310 and, if the light intensity is high enough, the germanium layer heats up and is converted to a plasma, thereby releasing the targeted device cell 400. A single device cell 400 can be selectively targeted for release. It is also possible to release multiple or all of the device cells 400 simultaneously. This method provides for an organized, controlled way to release the device cells 400. In another embodiment, peroxide can be used to etch away the germanium layer 310, thereby releasing the device cells 400.
In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the invention but to illustrate it. The scope of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated in the figure to indicate corresponding or analogous elements, which may optionally have similar characteristics.
It should also be appreciated that reference throughout this specification to “one embodiment”, “an embodiment”, “one or more embodiments”, or “different embodiments”, for example, means that a particular feature may be included in the practice of the invention. Similarly, it should be appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects may lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.
Claims
1. A method of releasing a device cell from a silicon handle wafer comprising:
- (a) providing a structure comprising a germanium layer between a silicon device cell and a silicon handle wafer or a polymer layer; and
- (b) directing electromagnetic radiation at the structure, wherein the electromagnetic radiation has a wavelength selective for removing germanium relative to the silicon device cell and the silicon handle wafer or polymer layer.
2. The method of claim 1, wherein the electromagnetic radiation has a wavelength in the range 1100-1600 nanometers.
3. The method of claim 2, wherein the electromagnetic radiation is directed through the silicon handle wafer or polymer layer into a germanium layer near the device cell.
4. The method of claim 3, wherein the germanium layer comprises crystalline, polycrystalline, or amorphous germanium.
5. The method of claim 3, wherein the silicon handle wafer has a thickness in the range 500-800 micrometers.
6. The method of claim 4, wherein the polymer layer has a thickness in the range 8-250 micrometers.
7. The method of claim 5, wherein the germanium layer has a thickness in the range 0.1-0.5 micrometers.
Type: Application
Filed: Jul 9, 2015
Publication Date: Nov 26, 2015
Inventors: Gregory N. Nielson (Lehi, UT), Murat Okandan (Edgewood, NM), Jose Luis Cruz-Campa (Albuquerque, NM), Jeffrey S. Nelson (Albuquerque, NM), Benjamin John Anderson (Eden Prairie, MN)
Application Number: 14/794,983