FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE
A FinFET device includes a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. A first layer of insulating material is positioned above a bottom surface of each of the plurality of spaced-apart trenches and an etch stop layer is positioned above an upper surface of the first layer of insulating material in each of the plurality of spaced-apart trenches. A metal silicide region is positioned on at least all sidewall surfaces of the fin that extend above the upper surface of the etch stop layer.
1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines the performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
In contrast to a FET, which has a planar structure, there are so-called 3D devices (3-dimensional structures), such as an illustrative FinFET device. More specifically, in one illustrative embodiment of a FinFET, a generally vertically positioned fin-shaped active area is formed, and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure with a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device may only have a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced relative to that of a planar FET device, which tends to reduce at least some short channel effects on a FinFET device.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. The gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and further scaling or reduction of the gate length is anticipated in the future. Device designers have employed a variety of techniques, other than device scaling, in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors), etc.
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by performance increases associated with the scaling of device features. Generally, while decreasing the channel length of a transistor may lead to superior performance characteristics, such as higher drive current capabilities and enhanced switching speeds, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
The use of so-called high-k/metal gate structures in replacement gate process flows to increase device electrical performance, while generally successful, has created some issues that need to be addressed. For example, after the deposition of a high-k insulating material, a post-deposition anneal is performed at a temperature that is typically greater than approximately 750° C. to insure adequate reliability of the gate stack materials. Metal silicide regions are typically formed on a transistor where contact is to be made to an underlying device, e.g., to the source/drain regions and/or the gate electrode, to reduce the contact resistance and hopefully improve the operating speed of the transistor. To the extent that metal silicide regions are formed prior to this post-deposition anneal process that is performed in a replacement gate process flow, the anneal process tends to cause the metal silicide regions to degrade, thereby increasing contact resistance and perhaps reducing the operating speed of the transistor.
The present disclosure is directed to various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices that may eliminate or at least reduce one or more of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various FinFET semiconductor devices having improved source/drain resistance. In one illustrative embodiment disclosed herein, a FinFET device includes, among other things, a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. The disclosed FinFET device further includes a first layer of insulating material positioned above a bottom surface of each of the plurality of spaced-apart trenches and an etch stop layer positioned above an upper surface of the first layer of insulating material in each of the plurality of spaced-apart trenches. Additionally, a metal silicide region is positioned on at least all sidewall surfaces of the fin that extend above the upper surface of the etch stop layer.
In another exemplary embodiment of the present disclosure, a FinFET device includes a plurality of spaced-apart trenches in a semiconducting substrate, the plurality of spaced-apart trenches at least partially defining a fin for the FinFET device, wherein the fin comprises a first semiconductor material. The exemplary FinFET device also includes, among other things, a second semiconductor material positioned on an upper portion of the fin, a first layer of insulating material positioned on a bottom surface of each of the plurality of spaced-apart trenches, and an etch stop layer positioned on the first layer of insulating material within each of the plurality of spaced-apart trenches. Furthermore, a gate structure is positioned on and around the fin and a metal silicide region is positioned on all surfaces of the second semiconductor material and on all sidewall surfaces of the fin between the upper surface of the etch stop layer and the second semiconductor material.
Also disclosed herein is yet another illustrative FinFET device that includes a plurality of spaced-apart trenches in a semiconducting substrate, wherein the plurality of spaced-apart trenches at least partially define a plurality of fins for the FinFET device, each of the plurality of fins comprising a first semiconductor material. Additionally, a second semiconductor material is positioned on an upper portion of each of the plurality of fins, and a first layer of insulating material is positioned above a bottom surface of each of the plurality of spaced-apart trenches and extends between adjacent sidewalls of each adjacent pair of the plurality of fins. The illustrative FinFET device further includes, among other things, an etch stop layer positioned on the first layer of insulating material in each of the plurality of spaced-apart trenches and extending between the respective adjacent sidewalls of each adjacent pair of the plurality of fins, wherein the etch stop layer positioned in each of the plurality of spaced-apart trenches has a substantially uniform thickness between the respective adjacent sidewalls in a direction that is normal to the bottom surface of the respective trench. Furthermore, a gate structure is positioned on and extends continuously over each of the plurality of fins, a sidewall spacer is positioned adjacent to the sidewalls of the gate structure, and a second layer of insulating material is positioned between a portion of the etch stop layer positioned in each of the plurality of spaced-apart trenches and the sidewall spacer. Moreover, a metal silicide region is positioned on all surfaces of the second semiconductor material positioned on the upper portion of each of the plurality of fins and on all sidewall surfaces of each of the plurality of fins between the upper surface of the etch stop layer and the second semiconductor material.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached drawings, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
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In the illustrative example where a “gate-first” approach is performed to form the gate structure for the device 100, a slightly different process flow may be employed if desired. For example, instead of using the dummy gate insulation layer 24 and the dummy gate electrode 26, those materials would not be sacrificial in nature. Rather, in a gate-first approach, the gate insulation layer 24 and the gate electrode 26 would be the final such structures for the device 100. Of course, the materials used for the gate insulation layer 24 and the gate electrode 26 in a “gate-first” application might be different as well. For example, the gate insulation layer 24 may be comprised of a high-k insulation material and the gate electrode 26 may be comprised of one or more layers of metal. In one illustrative process flow for a “gate-first” application, the steps employed may be substantially the same as those employed in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A FinFET device, comprising:
- a plurality of spaced-apart trenches in a semiconducting substrate, said plurality of spaced-apart trenches at least partially defining a fin for said FinFET device, wherein said fin comprises a first semiconductor material;
- a first layer of insulating material positioned above a bottom surface of each of said plurality of spaced-apart trenches;
- an etch stop layer positioned above an upper surface of said first layer of insulating material in each of said plurality of spaced-apart trenches; and
- a metal silicide region positioned on at least all sidewall surfaces of said fin that extend above an upper surface of said etch stop layer.
2. The FinFET device of claim 1, further comprising a gate structure positioned on and around said fin, wherein said gate structure extends across at least a portion of each of said plurality of spaced-apart trenches.
3. The FinFET device of claim 2, wherein said gate structure comprises a gate insulation layer comprising a high-k dielectric material and a work-function adjusting metal layer positioned above said gate insulation layer.
4. The FinFET device of claim 2, further comprising a second layer of insulating material positioned between a portion of said etch stop layer positioned in each of said plurality of spaced-apart trenches and a sidewall spacer positioned adjacent to sidewalls of said gate structure.
5. The FinFET device of claim 4, wherein said etch stop layer is comprised of silicon nitride and said first and second layers of insulating material are comprised of silicon dioxide.
6. The FinFET device of claim 1, wherein said etch stop layer is comprised of silicon nitride.
7. The FinFET device of claim 5, wherein said first layer of insulating material is comprised of silicon dioxide.
8. The FinFET device of claim 1, further comprising a second semiconductor material positioned on at least a portion of said fin, wherein said metal silicide region is further positioned on all surfaces of said second semiconductor material.
9. The FinFET device of claim 6, wherein at least a portion of a perimeter of said second semiconductor material has a substantially diamond-shaped configuration.
10. The FinFET device of claim 1, further comprising a conductive contact structure that is positioned above said etch stop layer in at least one of said plurality of spaced-apart trenches and conductively coupled to said fin.
11. The FinFET device of claim 1, wherein said fin is a first fin and said plurality of spaced-apart trenches at least partially define a second fin laterally adjacent to and spaced apart from said first fin, a first trench of said plurality of spaced-apart trenches being positioned between said first and second fins.
12. The FinFET device of claim 11, wherein said upper surface of said etch stop layer positioned in said first trench has a first edge defined by a first interface wherein said upper surface contacts a first sidewall of said first fin and a second edge defined by a second interface wherein said upper surface contacts a second sidewall of said second fin, said etch stop layer positioned in said first trench having a substantially uniform thickness between said first edge and said second edge in a direction that is normal to said bottom surface of said first trench.
13. A FinFET device, comprising:
- a plurality of spaced-apart trenches in a semiconducting substrate, said plurality of spaced-apart trenches at least partially defining a fin for said FinFET device, wherein said fin comprises a first semiconductor material;
- a second semiconductor material positioned on an upper portion of said fin;
- a first layer of insulating material positioned on a bottom surface of each of said plurality of spaced-apart trenches;
- an etch stop layer positioned on said first layer of insulating material within each of said plurality of spaced-apart trenches;
- a gate structure positioned on and around said fin; and
- a metal silicide region positioned on all surfaces of said second semiconductor material and on all sidewall surfaces of said fin between an upper surface of said etch stop layer and said second semiconductor material.
14. The FinFET device of claim 13, wherein said gate structure extends across at least one of said plurality of spaced-apart trenches, the FinFET device further comprising a second layer of insulating material positioned between a portion of said etch stop layer positioned within each of said plurality of spaced-apart trenches and a sidewall spacer positioned adjacent to sidewalls of said gate structure.
15. The FinFET device of claim 14, wherein said etch stop layer is comprised of silicon nitride and said first and second layers of insulating material are comprised of silicon dioxide.
16. The FinFET device of claim 13, wherein at least a portion of a perimeter of said second semiconductor material has a substantially diamond-shaped configuration.
17. The FinFET device of claim 13, further comprising a conductive contact structure that is positioned above said etch stop layer in each of said plurality of spaced-apart trenches and conductively coupled to said fin.
18. The FinFET device of claim 13, wherein said fin is a first fin and said plurality of spaced-apart trenches at least partially define a second fin laterally adjacent to and spaced apart from said first fin, wherein said gate structure is further positioned on and around said second fin and extends from said first fin to said second fin across a first trench of said plurality of spaced-apart trenches.
19. The FinFET device of claim 18, wherein substantially an entirety of said upper surface of said etch stop layer positioned in first trench is in a plane that is defined by a first edge wherein said upper surface terminates at a first sidewall of said first fin and a second edge wherein said upper surface terminates at a second sidewall of said second fin.
20. A FinFET device, comprising:
- a plurality of spaced-apart trenches in a semiconducting substrate, said plurality of spaced-apart trenches at least partially defining a plurality of fins for said FinFET device, each of said plurality of fins comprising a first semiconductor material;
- a second semiconductor material positioned on an upper portion of each of said plurality of fins;
- a first layer of insulating material positioned above a bottom surface of each of said plurality of spaced-apart trenches and extending between adjacent sidewalls of each adjacent pair of said plurality of fins;
- an etch stop layer positioned on said first layer of insulating material in each of said plurality of spaced-apart trenches and extending between said respective adjacent sidewalls of said each adjacent pair of said plurality of fins, wherein said etch stop layer positioned in each of said plurality of spaced-apart trenches has a substantially uniform thickness between said respective adjacent sidewalls in a direction that is normal to said bottom surface of said respective trench;
- a gate structure positioned on and extending continuously over each of said plurality of fins;
- a sidewall spacer positioned adjacent to sidewalls of said gate structure;
- a second layer of insulating material positioned between a portion of said etch stop layer positioned in each of said plurality of spaced-apart trenches and said sidewall spacer; and
- a metal silicide region positioned on all surfaces of said second semiconductor material positioned on said upper portion of each of said plurality of fins and on all sidewall surfaces of each of said plurality of fins between an upper surface of said etch stop layer and said second semiconductor material.
Type: Application
Filed: Aug 10, 2015
Publication Date: Dec 3, 2015
Inventors: Ruilong Xie (Niskayuna, NY), Mark Raymond (Schenectady, NY), Robert Miller (Yorktown Heights, NY)
Application Number: 14/822,167