FINFET SEMICONDUCTOR DEVICE WITH ISOLATED CHANNEL REGIONS
A FinFET device includes a fin structure positioned in the channel region of the device and a gate structure positioned above the fin structure, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Sidewall spacers are positioned adjacent the gate structure and a fin cavity is positioned in source/drain regions of the device, wherein the fin structure has edges in a gate width direction that are substantially self-aligned with the sidewall spacers and the semiconductor substrate defines the bottom of the fin cavity. A silicon etch stop layer is positioned on and in contact with the edges of the fin structure and within the fin cavity, and a stressed semiconductor material is positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity.
1. Field of the Disclosure
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming an isolated channel region for a FinFET semiconductor device and the resulting semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as FinFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a
PMOS transistor is considered, and irrespective of whether it is a planar or 3D FinFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epi semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3D) structure.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to significantly reduce short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins C, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width (for a tri-gate device). Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
For many early device technology generations, the gate structures of most transistor elements (planar or FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), titanium-aluminum-carbon (TiALC), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate-last” or “replacement gate” technique. The replacement gate process may be used when forming planar devices or 3D devices.
As shown in
Next, as shown in
Ultimately, as shown in
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation. Device designers are also contemplating ways to form isolation regions under the channel region of a 3D device to improve device performance. What is desired is a reliable and repeatable methodology for forming an isolation region under the channel region of a FinFET device.
The present disclosure is directed to various methods of forming an isolated channel region for a FinFET semiconductor device and the resulting semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.
SUMMARY OF THE DISCLOSUREThe following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the subject matter that is described in further detail below. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming an isolated channel region for a FinFET semiconductor device and the resulting semiconductor device. One exemplary embodiment of a FinFET device disclosed herein includes a fin structure positioned in a channel region of the FinFET device, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. The exemplary FinFET device also includes, among other things, a gate structure positioned above the fin structure in the channel region of the FinFET device and sidewall spacers positioned adjacent the gate structure, wherein the fin structure has edges in a gate width direction of the FinFET device that are substantially self-aligned with the sidewall spacers. Furthermore, a fin cavity is positioned in source/drain regions of the FinFET device, wherein the semiconductor substrate defines the bottom of the fin cavity. Additionally, the disclosed FinFET device includes a silicon etch stop layer positioned on and in contact with the edges of the fin structure and within the fin cavity, and a stressed semiconductor material positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity.
Another illustrative FinFET device of the present disclosure includes, among other things, a fin structure positioned in a channel region of the FinFET device, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. The disclosed FinFET device also includes a gate structure positioned above the fin structure in the channel region of the FinFET device, wherein the gate structure includes a gate insulation layer and a gate electrode, the gate insulation layer including a high-k insulating material and the gate electrode including at least one layer of metal. Additionally, sidewall spacers are positioned adjacent the gate structure, wherein the fin structure has edges in a gate width direction of the FinFET device that are substantially self-aligned with the sidewall spacers, and a fin cavity is positioned in source/drain regions of the FinFET device, wherein the semiconductor substrate defines a bottom of the fin cavity. Moreover, the illustrative FinFET device further includes a silicon etch stop layer positioned on and in contact with the edges of the fin structure, on the bottom of the fin cavity, and on sidewalls of the fin cavity, and a stressed semiconductor material is positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity.
In yet a further exemplary embodiment, a FinFET device is disclosed herein that includes a fin structure positioned in a channel region of the FinFET device, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Additionally, the exemplary FinFET device includes a gate structure positioned above the fin structure in the channel region of the FinFET device, and sidewall spacers positioned adjacent the gate structure, wherein the fin structure has edges in a gate width direction of the FinFET device that are substantially self-aligned with the sidewall spacers. Also included in the disclosed FinFET device is a fin cavity that is positioned in source/drain regions of the FinFET device, wherein the semiconductor substrate defines a bottom of the fin cavity. Furthermore, a silicon etch stop layer is positioned on and in contact with the edges of the fin structure, on the bottom of the fin cavity, and on sidewalls of the fin cavity, wherein the silicon etch stop layer covers the semiconductor substrate portion of the fin structure and the epi semiconductor material of the fin structure along at least the edges of the fin structure. Moreover, a stressed semiconductor material is positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity, wherein the stressed semiconductor material comprises silicon-germanium (SixGe1-x).
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
DETAILED DESCRIPTIONVarious illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various systems, structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure generally relates to various methods of forming an isolated channel region for a FinFET semiconductor device and the resulting semiconductor device. Moreover, as will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. The methods and devices disclosed herein may be employed in manufacturing products using a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory devices, logic devices, ASICs, etc. As will be appreciated by those skilled in the art after a complete reading of the present application, the inventions disclosed herein may be employed in forming integrated circuit products using a variety of so-called 3D devices, such as FinFETs. For purposes of disclosure, reference will be made to an illustrative process flow wherein a single FinFET device 100 is formed. Moreover, the inventions will be disclosed in the context of forming the gate structures using a replacement gate (“gate-last”) processing technique. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
In one embodiment, the illustrative device 100 will be formed in and above the semiconductor substrate 102, having a bulk configuration. The device 100 may be either an NMOS or a PMOS transistor. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. The substrate 102 may be made of silicon or it may be made of materials other than silicon.
In other embodiments, the device 100 may be formed on a so-called silicon-on-insulator (SOI) substrate, as described more fully below. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials.
The attached drawings present various views of one illustrative embodiment of a FinFET device 100 that may be formed using the methods disclosed herein. The drawings also include a simplistic plan view of the device 100 (in the upper right corner) that depicts the location where various cross-sectional views depicted in the following drawings will be taken. More specifically, the view “X-X” is a cross-sectional view that is taken through the source/drain (S/D) regions of the device (i.e., along the gate width direction of the device 100). The view “Y-Y” is a cross-sectional view that is taken through the gate structure of the device in the gate-width direction. The view Z-Z is a cross-sectional view that is taken through the long axis of the fins 106 of the device (i.e., in the current transport or gate-length direction of the device). The drawings also include a reduced-size plan view of the device 100.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A FinFET device, comprising:
- a fin structure positioned in a channel region of said FinFET device, wherein said fin structure comprises: a portion of a semiconductor substrate; and an epi semiconductor material positioned vertically above said portion of said semiconductor substrate;
- a gate structure positioned above said fin structure in said channel region of said FinFET device;
- sidewall spacers positioned adjacent said gate structure, wherein said fin structure has edges in a gate width direction of said FinFET device that are substantially self-aligned with said sidewall spacers;
- a fin cavity positioned in source/drain regions of said FinFET device, wherein said semiconductor substrate defines a bottom of said fin cavity;
- a silicon etch stop layer positioned on and in contact with said edges of said fin structure and within said fin cavity; and
- a stressed semiconductor material positioned on and in contact with said silicon etch stop layer and at least partially within said fin cavity.
2. The FinFET device of claim 1, wherein said silicon etch stop layer is positioned on said bottom of said fin cavity and on sidewalls of said fin cavity.
3. The FinFET device of claim 1, wherein said stressed semiconductor material is silicon-germanium (SixGe1-x).
4. The FinFET device of claim 1, wherein said gate structure comprises a gate insulation layer and a gate electrode positioned on said gate insulation layer, said gate insulation layer comprising a high-k insulating material and said gate electrode comprising at least one layer of metal.
5. The FinFET device of claim 1, further comprising a gate cap layer positioned above said gate structure.
6. The FinFET device of claim 5, wherein said sidewall spacers are positioned adjacent and laterally confine said gate cap layer.
7. The FinFET device of claim 1, wherein said silicon etch stop layer covers said semiconductor substrate portion of said fin structure and said epi semiconductor material of said fin structure along at least said edges of said fin structure.
8. A FinFET device, comprising:
- a fin structure positioned in a channel region of said FinFET device, wherein said fin structure comprises: a portion of a semiconductor substrate; and an epi semiconductor material positioned vertically above said portion of said semiconductor substrate;
- a gate structure positioned above said fin structure in said channel region of said FinFET device, wherein said gate structure comprises a gate insulation layer and a gate electrode, said gate insulation layer comprising a high-k insulating material and said gate electrode comprising at least one layer of metal;
- sidewall spacers positioned adjacent said gate structure, wherein said fin structure has edges in a gate width direction of said FinFET device that are substantially self-aligned with said sidewall spacers;
- a fin cavity positioned in source/drain regions of said FinFET device, wherein said semiconductor substrate defines a bottom of said fin cavity;
- a silicon etch stop layer positioned on and in contact with said edges of said fin structure, on said bottom of said fin cavity, and on sidewalls of said fin cavity; and
- a stressed semiconductor material positioned on and in contact with said silicon etch stop layer and at least partially within said fin cavity.
9. The FinFET device of claim 8, wherein said high-k insulating material has a dielectric constant of approximately 10 or greater and said at least one layer of metal comprises a plurality of metal layers.
10. The FinFET device of claim 8, wherein said gate electrode further comprises a layer of conductive material positioned above said at least one layer of metal.
11. The FinFET device of claim 8, further comprising a gate cap layer positioned above said gate structure, wherein said sidewall spacers are positioned adjacent and laterally confine said gate cap layer.
12. The FinFET device of claim 8, wherein said silicon etch stop layer covers said semiconductor substrate portion of said fin structure and said epi semiconductor material of said fin structure along sidewalls and said edges of said fin structure.
13. A FinFET device, comprising:
- a fin structure positioned in a channel region of said FinFET device, wherein said fin structure comprises: a portion of a semiconductor substrate; an epi semiconductor material positioned vertically above said portion of said semiconductor substrate;
- a gate structure positioned above said fin structure in said channel region of said FinFET device;
- sidewall spacers positioned adjacent said gate structure, wherein said fin structure has edges in a gate width direction of said FinFET device that are substantially self-aligned with said sidewall spacers;
- a fin cavity positioned in source/drain regions of said FinFET device, wherein said semiconductor substrate defines a bottom of said fin cavity;
- a silicon etch stop layer positioned on and in contact with said edges of said fin structure, on said bottom of said fin cavity, and on sidewalls of said fin cavity, said silicon etch stop layer covering said semiconductor substrate portion of said fin structure and said epi semiconductor material of said fin structure along at least said edges of said fin structure; and
- a stressed semiconductor material positioned on and in contact with said silicon etch stop layer and at least partially within said fin cavity, said stressed semiconductor material comprising silicon-germanium (SixGe1-x).
14. The FinFET device of claim 13, wherein said gate structure comprises a gate insulation layer and a gate electrode positioned on said gate insulation layer.
15. The FinFET device of claim 14, wherein said gate insulation layer comprises a high-k insulating material, and wherein said gate electrode comprises at least one layer of metal.
16. The FinFET device of claim 15, wherein said high-k insulating material has a dielectric constant of approximately 10 or greater.
17. The FinFET device of claim 15, wherein said at least one layer of metal comprises a plurality of metal layers.
18. The FinFET device of claim 15, wherein said gate electrode further comprises a layer of conductive material positioned above said at least one layer of metal.
19. The FinFET device of claim 13, further comprising a gate cap layer positioned above said gate structure, wherein said sidewall spacers are positioned adjacent and laterally confine said gate cap layer.
Type: Application
Filed: Dec 9, 2015
Publication Date: Mar 31, 2016
Inventors: Ajey Poovannummoottil Jacob (Watervliet, NY), Nicolas Loubet (Guilderland, NY)
Application Number: 14/963,683