Patents by Inventor Ajey Poovannummoottil Jacob

Ajey Poovannummoottil Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10665281
    Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 26, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Amogh Agrawal, Bipul C. Paul
  • Patent number: 10649245
    Abstract: Structures for an electro-optic modulator and methods of fabricating a structure for an electro-optic modulator. The electro-optic modulator is arranged over a portion of a first waveguide core. The electro-optic modulator may include an electrode, an active layer, a second waveguide core, and a dielectric layer that is arranged between the active layer and the second waveguide core. The active layer is composed of a material having a refractive index that is a function of a bias voltage applied between the electrode and the first waveguide core.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Abu Thomas
  • Patent number: 10649140
    Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. A back-end-of-line interconnect structure includes a cap layer, an interlayer dielectric layer, and one or more metal features embedded in the interlayer dielectric layer. The interlayer dielectric layer is stacked in a vertical direction with the cap layer. The one or more metal features have an overlapping arrangement in a lateral direction with the waveguide core, which is arranged under the back-end-of-line interconnect structure.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Abu Thomas
  • Patent number: 10641956
    Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. A back-end-of-line interconnect structure has an interlayer dielectric layer and a cap layer stacked over the interlayer dielectric layer. A waveguide core includes a section arranged beneath the cap layer. The waveguide core has a first index of refraction that varies as a function of width, and the cap layer has a second index of refraction. The section of the waveguide core has a width that is selected such that the first index of refraction is substantially equal to the second index of refraction to provide phase matching effective for coupling a portion of an optical signal from the waveguide core to the cap layer.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Abu Thomas
  • Publication number: 20200124796
    Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A first dielectric layer comprised of a first silicon nitride is formed. The waveguide is arranged over the first dielectric layer. A second dielectric layer is formed that is arranged over the waveguide. The second dielectric layer is composed of a second silicon nitride having a lower absorption of optical signals than the first silicon nitride.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Publication number: 20200088942
    Abstract: Structures with waveguides in multiple levels and methods of fabricating a structure that includes waveguides in multiple levels. A waveguide crossing has a first waveguide and a second waveguide arranged to intersect the first waveguide. A third waveguide is displaced vertically from the waveguide crossing, The third waveguide includes a portion having an overlapping arrangement with a portion of the first waveguide. The overlapping portions of the first and third waveguides are configured to transfer optical signals between the first waveguide and the third waveguide.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob, Abu Thomas
  • Patent number: 10585219
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with multiple configurations and methods of manufacture. A grating coupler structure includes: a polysilicon material with a first grating coupling pattern; a SiN material with second grating coupling pattern; a dielectric material covering the polysilicon material and the SiN material; and a back end of line (BEOL) multilayer stack over the dielectric material.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Yusheng Bian
  • Patent number: 10585245
    Abstract: Structures that include an optical component, such as a grating coupler, and methods of fabricating a structure that includes an optical component, such as a grating coupler. First and second layers are arranged over the optical component with the first layer arranged between the second layer and the optical component. The first and second layers are each composed of a tunable material having a refractive index that is a function of a bias voltage applied to the first layer and the second layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Abu Thomas, Ajey Poovannummoottil Jacob
  • Patent number: 10557989
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a slot assisted grating based transverse magnetic (TM) pass polarizer and methods of manufacture. The structure includes: a waveguide strip composed of a first type of material and having openings along its length which are positioned to reflect/scatter a propagating electromagnetic waves; and grating fin structures on one or both sides of the waveguide strip which are positioned and structured to reflect/scatter the propagating electromagnetic waves.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Marcus V. S. Dahlem, Humaira Zafar, Anatol Khilo, Sujith Chandran
  • Publication number: 20200026000
    Abstract: Structures including a waveguide arrangement and methods of fabricating a structure that includes a waveguide arrangement. A second waveguide spaced in a lateral direction from a first waveguide, a third waveguide spaced in a vertical direction from the first waveguide, and a fourth waveguide spaced in the vertical direction from the second waveguide. The third waveguide is arranged in the lateral direction to provide a first overlapping relationship with the first waveguide. The fourth waveguide is arranged in the lateral direction to provide a second overlapping relationship with the second waveguide.
    Type: Application
    Filed: July 20, 2018
    Publication date: January 23, 2020
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Publication number: 20200012045
    Abstract: Waveguide bends and methods of fabricating waveguide bends. A first waveguide bend is contiguous with a waveguide. A second waveguide bend is spaced from a surface at an inner radius of the first waveguide bend by a gap. The second waveguide bend may have a substantially concentric arrangement with the first waveguide bend.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob
  • Patent number: 10510392
    Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Bipul C. Paul, Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, William Taylor, Danny Pak-Chum Shum
  • Publication number: 20190369309
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with multiple configurations and methods of manufacture. A grating coupler structure includes: a polysilicon material with a first grating coupling pattern; a SiN material with second grating coupling pattern; a dielectric material covering the polysilicon material and the SiN material; and a back end of line (BEOL) multilayer stack over the dielectric material.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Inventors: Ajey Poovannummoottil JACOB, Yusheng BIAN
  • Patent number: 10468084
    Abstract: The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob
  • Patent number: 10468456
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Jaiswal Akhilesh
  • Patent number: 10468083
    Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Jaiswal, Ajey Poovannummoottil Jacob
  • Patent number: 10461173
    Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey Poovannummoottil Jacob, Xuan Anh Tran, Hui Zang, Bala Haran, Suryanarayana Kalaga
  • Patent number: 10444433
    Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A tapered feature composed of a dielectric material is arranged over the waveguide. The tapered feature includes a sidewall that is angled relative to a longitudinal axis of the waveguide.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Abu Thomas, Ajey Poovannummoottil Jacob, Kenneth J. Giewont, Karen Nummy, Andreas Stricker, Bo Peng
  • Publication number: 20190310399
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with structured cladding and methods of manufacture. A structure includes: a grating coupler in a dielectric material; a back end of line (BEOL) multilayer stack over the dielectric material; and a multi-layered cladding structure of alternating materials directly on the BEOL multilayer stack.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Ajey Poovannummoottil JACOB, Yusheng BIAN
  • Patent number: 10436982
    Abstract: Structures including waveguide bends, methods of fabricating a structure that includes waveguide bends, and systems that integrate optical components containing different materials. A first waveguide bend is contiguous with a waveguide, and a second waveguide bend is spaced in a vertical direction from the first waveguide bend. The second waveguide bend has an overlapping arrangement with the first waveguide bend in a lateral direction.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yusheng Bian, Ajey Poovannummoottil Jacob