Boundary Word Line Operation in Nonvolatile Memory
One or more word lines in a Multi Level Cell (MLC) block are identified as being at high risk of read disturb errors and data is selectively copied from such high risk word lines to a location outside the MLC block where the copy is maintained. Subsequent read requests for the data may be directed to the copy of the data outside the MLC block.
This application relates to the operation of re-programmable nonvolatile memory such as semiconductor flash memory.
Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM packaged as a small form factor card, has become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, and retains its stored data even after power is turned off Also, unlike ROM (read only memory), flash memory is rewritable similar to a disk storage device.
Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) to be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions. Flash memory such as Flash EEPROM allows entire blocks of memory cells to be erased at the same time.
The floating gate can hold a range of charges and therefore can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
Nonvolatile memory devices are also manufactured from memory cells with a dielectric layer for storing charge. Instead of the conductive floating gate elements described earlier, a dielectric layer is used. An ONO dielectric layer extends across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions within the dielectric.
Many nonvolatile memories are formed along a surface of a substrate (e.g. silicon substrate) as two dimensional (2D), or planar, memories. Other nonvolatile memories are three dimensional (3-D) memories that are monolithically formed in one or more physical levels of memory cells having active areas disposed above a substrate.
In some cases, errors occur in data when the data is read out after being stored in a nonvolatile memory. Small numbers of errors can generally be corrected by Error Correction Code (ECC). Large numbers of errors may be uncorrectable by ECC (UECC). Even when errors are correctable, such correction may require significant resources and may take significant time.
SUMMARYIn some memory systems, stored data may become disturbed by read operations so that the stored data develops a high error rate. Data in certain locations may be particularly susceptible to such read disturb errors. Where a word line is in close proximity to the boundary between written and unwritten word lines in an open block (e.g. last fully written MLC word line in a partially written MLC block) data may be particularly susceptible to read disturbs. A counter may maintain a count of the number of read operations affecting such a word line and the data may be copied to another location if the count exceeds a threshold. Such data may be copied from an MLC block to an SLC block so that subsequent reads are faster and the risk of read disturbance is low. Data stored in a word line at a physical edge of a block may also be susceptible to read disturb errors. Accordingly, such data may be copied to another location (e.g. from MLC to SLC) either immediately or when a certain read count is reached.
An example of a method of operating a nonvolatile memory includes: identifying one or more high risk word lines in a Multi Level Cell (MLC) block that contain data that is at high risk of read disturb errors; selectively copying the data from the one or more high risk word lines to a location outside the MLC block; maintaining a copy of the data outside the MLC block; and subsequently directing read requests for the data to the copy of the data outside the MLC block.
The location may be outside the MLC block in a Single Level Cell (SLC) block. Identifying one or more high risk word lines may be based on proximity to a boundary between written and unwritten word lines. Identifying one or more high risk word lines may be further based on counting a number of read operations performed on an individual written word line in close proximity to the boundary. The individual word line may be identified as a high risk word line in response to determining that the number of read operations directed to the individual written word line exceeds a threshold number. Identifying one or more high risk word lines may be based on physical locations of word lines within a block. A word line located at a physical edge of the MLC block may be identified as a high risk word line. The MLC block may be written in a predetermined word line order and the word line at the physical end may be the last written word line in the predetermined word line order. The nonvolatile memory may be a three-dimensional nonvolatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and wherein the one or more high risk word lines are in a highest or lowest physical level.
An example of a nonvolatile memory system includes: a plurality of Multi Level Cell (MLC) blocks that store more than one bit per cell; an identifying circuit that is configured to identify one or more high risk word lines in an individual MLC block that contains data that is at high risk of read disturb errors; a copying circuit that is configured to selectively copy the data from the one or more high risk word lines to a location outside the individual MLC block; and a read circuit that is configured to read the data from the location outside the individual MLC block.
The memory system may also include a plurality of Single Level Cell (SLC) blocks that store only one bit per cell, and the location may be in an SLC block. The identifying circuit may be configured to identify a boundary between written and unwritten word lines. A read count circuit may count the number of read operations performed on an individual written word line adjacent to the boundary between written and unwritten word lines. A comparison circuit may be in communication with the read count circuit, the comparison circuit configured to compare the number of read operations performed with a threshold number and to designate the individual written word line as a high risk word line if the number of read operations performed exceeds the threshold number. The identifying circuit may be configured to identify the one or more high risk word lines from their physical location at an end of the block. The MLC blocks may be formed in a three dimensional memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, the one or more high risk word lines located in a highest or lowest physical level.
An example of a method of operating a nonvolatile memory includes: writing Multi Level Cell (MLC) data in an MLC block in a plurality of word lines of a block, leaving additional word lines unwritten; subsequently maintaining a count of read operations performed on a last fully written word line of the block; comparing the count with a threshold number; in response to determining that the count exceeds the threshold number, copying the data from the last fully written word line to a Single Level Cell (SLC) block; maintaining a copy of the data in the SLC block; and subsequently directing read requests for the data to the copy of the data in the SLC block.
A partially written word line with only lower page data may be located between the last fully written word line and the additional word lines that are unwritten. The nonvolatile memory may be a three dimensional nonvolatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory system may maintain a number of open MLC blocks that are open for writing new data and individual counts may be maintained of read operations performed on last fully written word lines of each open MLC block. The method may also include: subsequently copying the MLC data from the MLC block to another MLC block and designating the copy of the data in the SLC block as obsolete. Prior to copying the MLC data from the MLC block to another block, additional MLC data may be written in the MLC block. The writing of the additional MLC data in the MLC block may substantially fill the MLC block.
Various aspects, advantages, features and embodiments are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings.
Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
Associated circuitry is typically required for operation of the memory elements and for communication with the memory elements. As non-limiting examples, memory devices may have circuitry used for controlling and driving memory elements to accomplish functions such as programming and reading. This associated circuitry may be on the same substrate as the memory elements and/or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and/or on the same substrate as the memory elements.
In other embodiments, types of memory other than the two dimensional and three dimensional exemplary structures described here may be used.
There are many commercially successful non-volatile solid-state memory devices being used today. These memory devices may employ different types of memory cells, each type having one or more charge storage element.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to set the threshold voltage for a given memory state under test at the control gate and detect if the conduction current is lower or higher than a threshold current (cell-read reference current). In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line.
As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold voltage window. For example, a memory device may have memory cells having a threshold voltage window that ranges from −1.5V to 5V. This provides a maximum width of 6.5V. If the memory cell is to store 16 states, each state may occupy from 200 mV to 300 mV in the threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.
NAND StructureWhen an addressed memory transistor 10 within a NAND string is read or is verified during programming, its control gate 30 is supplied with an appropriate voltage. At the same time, the rest of the non-addressed memory transistors in the NAND string 50 are fully turned on by application of sufficient voltage on their control gates. In this way, a conductive path is effectively created from the source of the individual memory transistor to the source terminal 54 of the NAND string and likewise for the drain of the individual memory transistor to the drain terminal 56 of the cell.
One difference between flash memory and other of types of memory is that a flash memory cell is generally programmed from the erased state. That is the floating gate is generally first emptied of charge. Programming then adds a desired amount of charge back to the floating gate. Flash memory does not generally support removing a portion of the charge from the floating gate to go from a more programmed state to a lesser one. This means that updated data cannot overwrite existing data and is instead written to a previous unwritten location.
Furthermore erasing is to empty all the charges from the floating gate and generally takes appreciable time. For that reason, it will be cumbersome and very slow to erase cell by cell or even page by page. In practice, the array of memory cells is divided into a large number of blocks of memory cells. As is common for flash EEPROM systems, the block is the unit of erase. That is, each block contains the minimum number of memory cells that are erased together. While aggregating a large number of cells in a block to be erased in parallel will improve erase performance, a large size block also entails dealing with a larger number of update and obsolete data.
Each block is typically divided into a number of physical pages. A logical page is a unit of programming or reading that contains a number of bits equal to the number of cells in a physical page. In a memory that stores one bit per cell, one physical page stores one logical page of data. In memories that store two bits per cell, a physical page stores two logical pages. The number of logical pages stored in a physical page thus reflects the number of bits stored per cell. In one embodiment, the individual pages may be divided into segments and the segments may contain the fewest number of cells that are written at one time as a basic programming operation. One or more logical pages of data are typically stored in one row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data.
MLC ProgrammingA 2-bit code having a lower bit and an upper bit can be used to represent each of the four memory states. For example, the “E”, “A”, “B” and “C” states are respectively represented by “11”, “01”, “00” and ‘10”. The 2-bit data may be read from the memory by sensing in “full-sequence” mode where the two bits are sensed together by sensing relative to the read demarcation threshold values rV1, rV2 and rV3 in three sub-passes respectively.
3-D NAND StructureAn alternative arrangement to a conventional two-dimensional (2-D) NAND array is a three-dimensional (3-D) array. In contrast to 2-D NAND arrays, which are formed along a planar surface of a semiconductor wafer, 3-D arrays extend up from the wafer surface and generally include stacks, or columns, of memory cells extending upwards. Various 3-D arrangements are possible. In one arrangement a NAND string is formed vertically with one end (e.g. source) at the wafer surface and the other end (e.g. drain) on top. In another arrangement a NAND string is formed in a U-shape so that both ends of the NAND string are accessible on top, thus facilitating connections between such strings.
As with planar NAND strings, select gates 705, 707, are located at either end of the string to allow the NAND string to be selectively connected to, or isolated from, external elements 709, 711. Such external elements are generally conductive lines such as common source lines or bit lines that serve large numbers of NAND strings. Vertical NAND strings may be operated in a similar manner to planar NAND strings and both SLC and MLC operation is possible. While
Vertical NAND strings may be arranged to form a 3-D NAND array in various ways.
Common source lines “SL” connect to one end of each NAND string (opposite to the end that connects to the bit line). This may be considered the source end of the NAND string, with the bit line end being considered as the drain end of the NAND string. Common source lines may be connected so that all source lines for a block may be controlled together by a peripheral circuit. Thus, NAND strings of a block extend in parallel between bit lines on one end, and common source lines on the other end.
NAND strings connected to a given bit line. NAND strings are grouped into sets of strings that share common select gates. Thus, for example, NAND strings that are selected by SGS0 and SGD0 may be considered a set and may be designated as String 0, while NAND strings that are selected by SGS1 and SGD1 may be considered as a set and may be designated as String 1 as shown. A block may consist of any suitable number of such sets of strings. It will be understood that the cross-section of
When data is stored in a nonvolatile memory (e.g. 2D or 3D charge storage memory) for a period of time and then read out, some errors may occur in the data. Errors may occur for a variety of reasons including read disturb (i.e. the effects of reading the data and/or reading nearby data) or data retention issues (e.g. charge leaking from floating gates). The root causes of errors may be some physical defects in the memory structure resulting from the manufacturing process, some environmental effect, data pattern effect, or some combination of causes. In many cases, such errors may be corrected by Error Correction Code (ECC). However, if there are many errors in a portion of data then it may require significant time and resources to perform ECC correction. If the number of errors exceeds the limit of the ECC scheme then the data may be uncorrectable by ECC (UECC) and some other approach may be used to recover the data (e.g. high resolution read). However, such approaches generally require significant time and resources. If alternative approaches fail then data may be lost. Accordingly, it is generally desirable to avoid high error rates in stored data.
One common source of errors is the effect of voltages applied during read operations. When memory cells are read the read voltages applied may affect the charge in the memory cells thereby causing disturbance. When other memory cells in the same block are read, read pass voltages may be applied to unselected word lines in the block so that unselected cells that are not read may be disturbed. The degree of read disturbance may depend on a number of factors including the format of the data (e.g. MLC data may be more susceptible to read disturb than SLC), the read scheme used (read voltages and read pass voltages), memory cell geometry (smaller cells may be more susceptible), and other factors. Generally errors caused by read disturb increase in proportion to the number of read operations so that data which is frequently updated and rewritten may have a low risk for read disturb errors while data that is left unchanged for a long period and is frequently read may have a high risk for read disturb errors.
One factor that may affect how data is affected by read disturbs is the location of the data within a block. It has been found that data along some word lines in a block may suffer higher read disturb errors than data along other word lines in the same block. One example of a word line that may suffer from higher read disturb errors is word line that is at or near a boundary between written and unwritten word lines. Generally, programming data along word lines of a block (whether 2D or 3D) proceeds in a predetermined order (i.e. word lines are not programmed at random). Programming may proceed sequentially starting with WL0. A boundary word line has unwritten and/or partially written memory cells on one side. Such unwritten or partially written memory cells in a charge storage memory do not contain as much charge as written memory cells. The proximity of such unwritten cells produces different electrostatic forces on the charge in boundary word lines compared with other word lines so that such charge may tend to move more easily. The absence of charge on one side may also affect threshold voltages of memory cells along boundary word lines. Charge in close proximity to a cell's channel affects the cell's threshold voltage and this effect is not limited to charge stored in the particular cell. Charge in neighboring cells (or the absence of such charge) may also affect a particular cell's threshold voltage.
In some cases, data may be programmed as shown in
An alternative programming scheme is illustrated in
Read disturbance may cause some charge to enter some memory cells (e.g. cells in the erased state) so that such cells undergo a change similar to light programming. Thus, the effects of read disturb tend to compound the problem of lower threshold voltages of cells in programmed states (A, B, and C) along boundary word lines shown in
Each programmed word line may be considered a boundary word line at some point during programming. However, this condition may only exist for a short period for many word lines (e.g. during a sequential write, the next word line may be programmed immediately). However, in some cases, programming of a block may stop with some unwritten space (unwritten and/or partially written word lines) in the block. A certain number of blocks may be maintained as open blocks that are available for storage of user data. Such blocks may maintained in an open condition (rather than being compacted or combined with other data to fill blocks) for an extended period. A boundary word line in such a block may remain as a boundary word line for a significant period of time and for a significant number of read operations. While other word lines in such an open block may not have a high error rate from read disturbs, a boundary word line in such a block may have a high error rate if it is exposed to a large number of reads because it is especially susceptible to read disturbs.
Boundary word lines may be monitored to determine if there is a high risk of read disturb errors and some action may be taken when there is a high risk. For example, when programming of an open block stops at a new location and a new word line becomes the boundary word line, a read count may be initiated for the boundary word line. The number of read operations directed to the boundary word line may be counted. In some examples, the number of read operations directed to neighboring word lines may be counted (e.g. if read disturbance is caused by read-pass voltages). In some cases, these numbers may be combined (i.e. the number of reads of the boundary word line, and the number of reads of other word lines of the same block may be aggregated in some manner with each number weighted according to its read disturb effect on memory cells). In general, read disturb errors increase with the number of read operations so that below a threshold number of read operations the number of read disturb errors may be acceptable (e.g. correctable by ECC in an acceptable time). When the number of read operations indicated by the count reaches a point where read disturb errors are unacceptable, or about to become unacceptable, steps may be taken to ensure that the data along the boundary word line remains available without unacceptable delay.
Data that is at risk of significant read disturb errors may be copied to another location where further read disturbance is reduced or eliminated. For example, data along a boundary word line in an MLC block may be copied to an SLC block. In general, data stored in SLC format has larger margins between memory states so that such data is less susceptible to read disturb errors. The data may be subject to ECC correction when it is copied so that the new copy is substantially error-free when written and read disturb errors (or other errors) from the MLC copy are not brought over to the SLC copy. Furthermore, such data may be considered to be frequently read as indicated by the counter and SLC data is generally faster to read than MLC data so that relocating such frequently read data to SLC generally improves read performance.
After data is copied to a location outside the open MLC block 501 subsequent read operations may be directed to the copy in SLC block 603 and not to the data near the boundary in the open MLC block 501. This stops further read disturb errors and improves read time for the copied data. A record, such as a table or other suitable form of record, may be maintained to track which data is copied and where the new copy is located. This allows the copy to be read and the data to be returned when the data is subsequently accessed.
In addition to data along boundary word lines of open blocks, some other data may be considered to be susceptible to read disturb errors and may be copied to another location. For example, a word line at a physical edge of a block may be subject to a higher risk of read disturb errors because of its physical location, with no charge on one side of it (regardless of subsequent programming). This may include a word line at one edge of a block in a planar memory (e.g. planar NAND) or at one edge of a block in 3-D memory (e.g. in top or bottom physical level of a block in 3-D NAND or other 3-D memory). Accordingly, data in such a location may be subject to special treatment to protect it from read disturb errors.
According to an example, data in along a word line at a physical edge of a block may be copied to a location outside the block. For example, data along an edge word line in an MLC block may be copied to a location in an SLC block. In some cases, a counter may be maintained and the data may be copied only after the counter reaches a threshold number of read operations. In other cases, no such counter may be maintained and the data may be copied from MLC to SLC immediately.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the attached claims. Many modifications and variations are possible in light of the above teaching.
Claims
1. A method of operating a nonvolatile memory comprising:
- identifying one or more high risk word lines in a Multi Level Cell (MLC) block that contain data that is at high risk of read disturb errors;
- selectively copying the data from the one or more high risk word lines to a location outside the MLC block;
- maintaining a copy of the data outside the MLC block; and
- subsequently directing read requests for the data to the copy of the data outside the MLC block.
2. The method of claim 1 wherein the location outside the MLC block is in a Single Level Cell (SLC) block.
3. The method of claim 1 wherein the identifying one or more high risk word lines is based on proximity to a boundary between written and unwritten word lines.
4. The method of claim 3 wherein the identifying one or more high risk word lines is further based on counting a number of read operations performed on an individual written word line in close proximity to the boundary.
5. The method of claim 4 wherein the individual word line is identified as a high risk word line in response to determining that the number of read operations directed to the individual written word line exceeds a threshold number.
6. The method of claim 1 wherein the identifying one or more high risk word lines is based on physical locations of word lines within a block.
7. The method of claim 6 wherein a word line located at a physical edge of the MLC block is identified as a high risk word line.
8. The method of claim 7 wherein the MLC block is written in a predetermined word line order and the word line at the physical end is the last written word line in the predetermined word line order.
9. The method of claim 7 wherein the nonvolatile memory is a three-dimensional nonvolatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate and wherein the one or more high risk word lines are in a highest or lowest physical level.
10. A nonvolatile memory system comprising:
- a plurality of Multi Level Cell (MLC) blocks that store more than one bit per cell;
- an identifying circuit that is configured to identify one or more high risk word lines in an individual MLC block that contains data that is at high risk of read disturb errors;
- a copying circuit that is configured to selectively copy the data from the one or more high risk word lines to a location outside the individual MLC block; and
- a read circuit that is configured to read the data from the location outside the individual MLC block.
11. The nonvolatile memory system of claim 10 further comprising a plurality of Single Level Cell (SLC) blocks that store only one bit per cell, and wherein the location is in an SLC block.
12. The nonvolatile memory system of claim 10 wherein the identifying circuit is configured to identify a boundary between written and unwritten word lines.
13. The nonvolatile memory system of claim 12 further comprising a read count circuit that counts the number of read operations performed on an individual written word line adjacent to the boundary between written and unwritten word lines.
14. The nonvolatile memory system of claim 13 further comprising a comparison circuit in communication with the read count circuit, the comparison circuit configured to compare the number of read operations performed with a threshold number and to designate the individual written word line as a high risk word line if the number of read operations performed exceeds the threshold number.
15. The nonvolatile memory system of claim 10 wherein the identifying circuit is configured to identify the one or more high risk word lines from their physical location at an end of the block.
16. The nonvolatile memory system of claim 15 wherein the MLC blocks are formed in a three dimensional memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, the one or more high risk word lines located in a highest or lowest physical level.
17. A method of operating a nonvolatile memory comprising:
- writing Multi Level Cell (MLC) data in an MLC block in a plurality of word lines of a block, leaving additional word lines unwritten;
- subsequently maintaining a count of read operations performed on a last fully written word line of the block;
- comparing the count with a threshold number;
- in response to determining that the count exceeds the threshold number, copying the data from the last fully written word line to a Single Level Cell (SLC) block;
- maintaining a copy of the data in the SLC block; and
- subsequently directing read requests for the data to the copy of the data in the SLC block.
18. The method of claim 17 wherein a partially written word line with only lower page data is located between the last fully written word line and the additional word lines that are unwritten.
19. The method of claim 17 wherein the nonvolatile memory is a three dimensional nonvolatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate.
20. The method of claim 17 wherein the memory system maintains a number of open MLC blocks that are open for writing new data and wherein individual counts are maintained of read operations performed on last fully written word lines of each open MLC block.
21. The method of claim 17 further comprising;
- subsequently copying the MLC data from the MLC block to another MLC block and designating the copy of the data in the SLC block as obsolete.
22. The method of claim 21 further comprising, prior to copying the MLC data from the MLC block to another block, writing additional MLC data in the MLC block.
23. The method of claim 22 wherein the writing of the additional MLC data in the MLC block substantially fills the MLC block.
Type: Application
Filed: Nov 18, 2014
Publication Date: May 19, 2016
Inventors: Rohit Sehgal (Mountain View, CA), Niles Yang (Mountain View, CA), Abhilash Kashyap (San Jose, CA)
Application Number: 14/546,591