DEVICES FORMED BY PERFORMING A COMMON ETCH PATTERNING PROCESS TO FORM GATE AND SOURCE/DRAIN CONTACT OPENINGS
A device includes an isolation region that defines an active region in a semiconducting substrate and a gate structure, wherein the gate structure has an axial length in a long axis direction thereof such that a first portion of the gate structure is positioned above the active region and a second portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure, wherein a first portion of the gate cap layer that is positioned above the first portion of the gate structure is thicker than a second portion of the gate cap layer that is positioned above the second portion of the gate structure.
1. Field of the Disclosure
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to devices that are formed by using various methods of performing a common etch patterning process to form gate and source/drain contact openings.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years, particularly the channel length of transistor devices. As a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be “device-level” contacts or simply “contacts” within the industry, as they contact the “device” that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.
In sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, an interlayer dielectric material is formed first and is patterned so as to define contact openings which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements, i.e., the source/drain region or the gate structure of a transistor.
In older technologies, the CA and CB contacts were typically formed at the same time. However, as device dimensions and gate pitch dimensions decreased, the formation of self-aligned contacts has become necessary so as to avoid creating an electrical short between the CA contact and the gate structure. Typically, the gate structure is fully encapsulated by a silicon nitride cap layer and a silicon nitride sidewall spacer. A layer of insulating material, such as silicon dioxide, is formed on the substrate adjacent the gate structure and above the source/drain regions. To form the opening for the self-aligned source/drain contact structure (CA), an RIE process is typically performed to remove the silicon dioxide material selectively relative to the silicon nitride materials that encapsulate the gate structure. Since formation of the contact opening for the gate contact (CB) necessarily had to involve etching through the silicon nitride gate cap layer, the formation of the CA contacts and the CB contact could not be performed at the same time. That is, performing a common CA/CB etching process with an etchant that would remove portions of the silicon nitride gate cap layer (so as to form the CB contact opening) would consume the protective silicon nitride sidewall spacers and the silicon nitride gate cap layer adjacent the contact openings for the CA contacts, thereby exposing the gate structure to the CA contact openings.
In one embodiment, the process flow of forming the TS structures 22, CA contacts 24 and CB contacts 26 may be as follows. After a first layer of insulating material 17A is deposited, TS openings are formed in the first layer of insulating material 17A that expose portions of underlying source/drain regions 20. Thereafter, traditional silicide is formed through the TS openings, followed by forming tungsten (not separately shown) on the metal silicide regions, and performing a CMP process down to the top of the gate cap layer 16. Then, a second layer of insulating material 17B is deposited and contact openings for the CA contacts 24 are formed in the second layer of insulating material 17B that expose portions of the underlying tungsten metallization. Next, the opening for the CB contact 26 is formed in the second layer of insulating material 17B and through the gate cap layer 16 so as to expose a portion of the gate electrode 14B. Typically, the CB contact 26 is in the form of a round or square plug. Thereafter, the CA contacts 24 and the CB contact 26 are formed in their corresponding openings in the second layer of insulating material 17B by performing one or more common deposition and CMP process operations, using the second layer of insulating material 17B as a polish-stop layer to remove excess material positioned outside of the contact openings. The CA contacts 24 and CB contact 26 typically contain a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and the layer of insulating material 17B. The source/drain contact structures 21 (TS contacts 22, CA contacts 24) and the CB contact 26 are all considered to be device-level contacts within the industry.
Also depicted in
As noted above, in a typical process flow, the CA contacts 24 and the CB contact 26 are formed at different times using two different mask layers to define the contact openings. Reducing the number of masks needed to manufacture an integrated circuit product reduces the cost of manufacturing. Thus, it would be highly desirable to form the openings for the CA contacts and the CB contacts using a single masking layer. Exposure technologies such as EUV, or even double patterning processes, make the formation of such closely spaced contact openings possible from a patterning point of view. However, in forming the opening for the gate contact (CB), the etching process much punch through the gate cap layer, which is typically made of silicon nitride. In contrast, when forming the source/drain contacts (CA), the etching process must be designed so as to stop on the silicon nitride hard mask (and silicon nitride spacers) so as not to create an electrical short circuit between the gate structure and the source/drain contact. Thus, current methodologies prevent the formation of the contact openings for both the gate contact and the source/drain contacts at the same time, thereby adding increased cost to manufacturing.
The present disclosure is directed to various methods of methods of forming gate and source/drain contact openings by performing a common etch patterning process that may avoid, or at least reduce, the effects of one or more of the problems identified above.
SUMMARY OF THE DISCLOSUREThe following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the subject matter that is described in further detail below. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to devices that are formed by using various methods of performing a common etch patterning process to form gate and source/drain contact openings. One illustrative device disclosed herein includes, among other things, an isolation region that defines an active region in a semiconducting substrate. The disclosed device further includes a gate structure, wherein the gate structure has an axial length in a long axis direction thereof such that a first portion of the gate structure is positioned above the active region and a second portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure, wherein a first portion of the gate cap layer that is positioned above the first portion of the gate structure is thicker than a second portion of the gate cap layer that is positioned above the second portion of the gate structure.
Another exemplary device of the presently disclosed subject matter includes an isolation region positioned in a semiconducting substrate, the isolation region surrounding and defining an active region of the semiconducting substrate. The illustrative device further includes, among other things, a gate structure extending continuously from the active region to the isolation region, wherein a first gate structure portion of the gate structure is positioned above the active region and a second gate structure portion of the gate structure is positioned above the isolation region. Additionally, a gate cap layer is positioned above the gate structure and includes a plurality of material layers, wherein a first gate cap portion of the gate cap layer is positioned above the first gate structure portion and has a first gate cap thickness. Furthermore, a second gate cap portion of the gate cap layer is positioned above the second gate structure portion and has a second gate cap thickness that is less than the first gate cap thickness.
In yet a further illustrative embodiment disclosed herein, an exemplary device includes an isolation region positioned in a semiconducting substrate, the isolation region surrounding and defining an active region of the semiconducting substrate. Additionally, the disclosed device includes a gate structure that extends continuously from a first portion of the isolation region across the active region to a second portion of the isolation region, wherein the gate structure includes, among other things, a first gate structure portion positioned above the first portion of the isolation region, a second gate structure portion positioned above the second portion of the isolation region, and a third gate structure portion positioned above the active region. Furthermore, a gate cap layer is positioned above the gate structure and includes, among other things, a first gate cap portion positioned above the first gate structure portion and having a first gate cap thickness, a second gate cap portion positioned above the second gate structure portion and having a second gate cap thickness, and a third gate cap portion positioned above the third gate structure portion and having a third gate cap thickness that is greater than each of the first and second gate cap thicknesses.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
DETAILED DESCRIPTIONVarious illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various systems, structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure generally relates to forming gate and source/drain contact openings by performing a common etch patterning process. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
The illustrative product 100 will be formed in and above a semiconductor substrate 102. The transistor devices depicted herein may be either NMOS or PMOS transistors, they may be any type of transistor device, e.g., either planar or FinFET transistor devices, and the gate structures of such devices may be formed by performing well-known gate-first or replacement gate processing techniques. Additionally, various doped regions, e.g., halo implant regions, well regions and the like, are not depicted in the attached drawings. The substrate 102 may have a variety of configurations, such as the depicted bulk silicon configuration. The substrate 102 may also have a silicon-on-insulator (SOI) configuration that includes a bulk silicon layer, a buried insulation layer and an active layer, wherein semiconductor devices are formed in and above the active layer. The substrate 102 may be made of silicon or it may be made of materials other than silicon. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. The various components and structures of the device disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application.
With continuing reference to
As an alternative, if the metal silicide materials for the NFET and PFET devices are the same, the process flow can be modified. That is, starting at the point depicted in
At the point shown in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A device, comprising:
- an isolation region that defines an active region in a semiconducting substrate;
- a gate structure, wherein said gate structure has an axial length in a long axis direction thereof such that a first portion of said gate structure is positioned above said active region and a second portion of said gate structure is positioned above said isolation region; and
- a gate cap layer positioned above said gate structure, wherein a first portion of said gate cap layer that is positioned above said first portion of said gate structure is thicker than a second portion of said gate cap layer that is positioned above said second portion of said gate structure.
2. The device of claim 1, wherein said first and second portions of said gate cap layer comprise silicon nitride.
3. The device of claim 1, wherein said second portion of said gate cap layer has a thickness that is approximately 10-20% of a thickness of said first portion of said gate cap layer.
4. The device of claim 1, wherein said first portion of said gate cap layer comprises a plurality of layers of material and said second portion of said gate cap layer is made of a subset of said plurality of layers of material.
5. The device of claim 1, wherein said gate cap layer consists of a single layer of material.
6. The device of claim 1, wherein, when viewed in cross-section taken through said gate cap layer in a direction parallel to said long axis of said gate structure, said gate cap layer has a stepped profile.
7. The device of claim 1, further comprising a gate contact structure that extends through said second portion of said gate cap layer and conductively contacts said second portion of said gate structure.
8. A device, comprising:
- an isolation region positioned in a semiconducting substrate, said isolation region surrounding and defining an active region of said semiconducting substrate;
- a gate structure extending continuously from said active region to said isolation region, wherein a first gate structure portion of said gate structure is positioned above said active region and a second gate structure portion of said gate structure is positioned above said isolation region; and
- a gate cap layer positioned above said gate structure and comprising a plurality of material layers, wherein a first gate cap portion of said gate cap layer is positioned above said first gate structure portion and has a first gate cap thickness, and wherein a second gate cap portion of said gate cap layer is positioned above said second gate structure portion and has a second gate cap thickness that is less than said first gate cap thickness.
9. The device of claim 8, wherein said first gate cap portion has a greater number of material layers than said second gate cap portion.
10. The device of claim 8, wherein said first gate cap portion comprises at least three material layers and said second gate cap portion consists of a single material layer.
11. The device of claim 8, wherein at least one of said plurality of material layers comprising said gate cap layer extends continuously from said first gate cap portion to said second gate cap portion.
12. The device of claim 8, wherein a first one of said plurality of material layers comprises silicon and nitrogen, and wherein a second one of said plurality of material layers comprises a high-k dielectric material having a dielectric constant that is greater than approximately 10.
13. The device of claim 8, wherein said gate cap layer has a stepped profile when viewed in cross-section taken through said gate cap layer in a direction that is parallel to a long axis of said gate structure.
14. The device of claim 8, further comprising a gate contact structure that extends through said second gate cap portion and conductively contacts said second gate structure portion.
15. The device of claim 8, wherein said second gate structure portion is positioned above a first portion of said isolation region, said gate structure further comprising a third gate structure portion that is positioned above a second portion of said isolation region and extends continuously from said first gate structure portion positioned above said active region, wherein said gate cap layer comprises a third gate cap portion that is positioned above said third gate structure portion, said third gate cap portion having a third gate cap thickness that is less than said first gate cap thickness.
16. A device, comprising:
- an isolation region positioned in a semiconducting substrate, said isolation region surrounding and defining an active region of said semiconducting substrate;
- a gate structure extending continuously from a first portion of said isolation region across said active region to a second portion of said isolation region, said gate structure comprising: a first gate structure portion positioned above said first portion of said isolation region; a second gate structure portion positioned above said second portion of said isolation region; and a third gate structure portion positioned above said active region; and
- a gate cap layer positioned above said gate structure, said gate cap layer comprising: a first gate cap portion positioned above said first gate structure portion and having a first gate cap thickness; a second gate cap portion positioned above said second gate structure portion and having a second gate cap thickness; and a third gate cap portion positioned above said third gate structure portion and having a third gate cap thickness that is greater than each of said first and second gate cap thicknesses.
17. The device of claim 16, wherein said first and second gate cap thicknesses are approximately 10-20% of said third gate cap thickness.
18. The device of claim 16, wherein said gate cap layer comprises a plurality of material layers, said third gate cap portion having a greater number of material layers than either of said first and second gate cap portions.
19. The device of claim 16, wherein said gate cap layer consists of a single layer of material.
20. The device of claim 16, wherein said gate cap layer has a stepped profile when viewed in cross-section taken through said gate cap layer in a direction that is parallel to a long axis of said gate structure.
Type: Application
Filed: Feb 25, 2016
Publication Date: Jun 30, 2016
Inventors: Ruilong Xie (Niskayuna, NY), William J. Taylor (Clifton Park, NY), Min Gyu Sung (Latham, NY)
Application Number: 15/053,640