SEMICONDUCTOR DEVICES WITH CONDUCTIVE CONTACT STRUCTURES HAVING A LARGER METAL SILICIDE CONTACT AREA
A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material.
1. Field of the Disclosure
The present disclosure generally relates to the formation of semiconductor devices and, more specifically, to various methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs (central processing units), storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate structure positioned above the channel region. These elements are sometimes referred to as the source, drain, channel and gate, respectively. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and prevent the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure.
Another form of 3D semiconductor device employs so-called nanowire structures for the channel region of the device. There are several known techniques for forming such nanowire structures. As the name implies, at the completion of the fabrication process, the nanowire structures typically have a generally circular cross-sectional configuration. Nanowire devices are considered to be one option for solving the constant and continuous demand for semiconductor devices with smaller feature sizes. However, the manufacture of nanowire devices is a very complex process. However, it is believed that, for nanowire devices to be useful in producing production integrated circuit devices, such a nanowire device must include a plurality of stacked nanowires, e.g., three or more, such that the device can generate an acceptable level of drive current. Forming such tall, stacked nanowire structures can be very challenging for many reasons.
Irrespective of whether a planar or non-planar device is considered, electrical connections must be formed to the device so that it may operate as intended. That is, electrical connections must be made to the source region, the drain region and the gate electrode of the device. Typically, the conductive structures that actually make contact with the device itself, i.e., the source region, the drain region and the gate electrode, are referred to as “contacts” within the industry. Such conductive contacts are formed in one or more layers of insulating material. The entire arrangement of the conductive contacts and the associated layer(s) of insulating material are sometimes referred to as the “contact level” of the overall electrical “wiring arrangement” that is formed to provide electrical connection to the integrated circuit device.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. A modern integrated circuit product will typically include several metallization layers, e.g., multiple layers of conductive vias and conductive lines. The M1 metallization layer is typically the first major “wiring” layer that is formed on the product. As device dimensions have decreased, the conductive contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. For this reason, contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, the gate electrode structures are used as etch masks for selectively removing the silicon dioxide material in order to expose the source/drain regions of the transistors, thereby providing self-aligned trenches which are substantially laterally delineated by the spacer structures of the gate electrode structures.
Notwithstanding the complex processing described above, device dimensions continue to decrease and packing densities continue to increase. For gate pitch scaling less than, for example, 50 nm, there is simply not enough space for the formation of the gate contact, the source contact and the drain contact using existing methodologies and traditional devices, e.g., planar devices. Thus, nanowire devices present a potentially attractive alternative to obtained the desired control of the gate (so as to avoid or at least reduce undesirable short channel effects) and to reduce the gate length of the transistor device, so as to thereby leave more room for the formation of the various source, drain and gate contacts. However, even with such scaled nanowire devices, the source/drain regions are very small in terms of area. Typically, an epi semiconductor material will be formed in the source/drain regions of the device and, thereafter, a metal silicide region will be formed on the epi material so as to reduce the contact resistance when forming a conductive contact to the source/drain region. Given the very small contact area available in the source/drain region, the resulting metal silicide region also has a corresponding small contract area, which means an undesirable increase in the contact resistance. Such an increase in contact resistance can result in the degradation of the performance of the device.
The present disclosure is directed to various methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices that may reduce or eliminate one or more of the problems identified above.
SUMMARY OF THE DISCLOSUREThe following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the subject matter that is described in further detail below. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices. One illustrative semiconductor device disclosed herein includes, among other things, a source/drain region, a gate structure, a gate cap layer positioned above the gate structure, and a sidewall spacer positioned adjacent to opposite sides of the gate structure. The disclosed semiconductor device further includes a first epi semiconductor material positioned in the source/drain region and a second epi semiconductor material positioned on the first epi semiconductor material, the first epi semiconductor material having a first lateral width at an upper surface thereof and the second epi semiconductor having a second lateral width at an upper surface thereof that is greater than the first lateral width, wherein the second epi semiconductor material extends laterally over and covers at least a portion of an uppermost end of the sidewall spacer. Additionally, the illustrative semiconductor device includes a metal silicide region positioned on the upper surface of the second epi semiconductor material.
Also disclosed herein is an exemplary nanowire device that includes a stacked nanowire structure, the stacked nanowire structure including a plurality of vertically spaced-apart nanowires. The illustrative nanowire device further includes, among other things, a source/drain region positioned adjacent to the stacked nanowire structure, a gate structure positioned around and above the stacked nanowire structure, a gate cap layer positioned above the gate structure, a sidewall spacer positioned adjacent to opposite sides of the gate structure, and a layer of insulating material positioned above the gate cap layer and above an uppermost end of the sidewall spacers. Additionally, a first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material directly contacting an end surface of each of the plurality of vertically spaced-apart nanowires and having a first lateral width at an upper surface thereof. Furthermore, a second epi semiconductor material is positioned on the first epi semiconductor material and has a second lateral width at an upper surface thereof that is greater than the first lateral width, the second epi semiconductor material extending laterally over and covering at least a portion of the layer of insulating material and at least a portion of the uppermost end of the sidewall spacer.
In another illustrative embodiment of the present disclosure, a nanowire device includes laterally spaced-apart first and second stacked nanowire structures, each of the first and second stacked nanowire structures including a plurality of vertically spaced-apart nanowires, wherein each nanowire of the plurality of vertically spaced-apart nanowires has an outer perimeter when viewed in a cross-section taken through each of the respective nanowires in a direction corresponding to a gate width direction of the nanowire device. The exemplary nanowire device also includes, among other things, a layer of insulating material positioned between the laterally spaced-apart first and second stacked nanowire structures, a gate insulation layer positioned around the outer perimeter of each nanowire of the plurality of vertically spaced-apart nanowires of the first and second stacked nanowire structures, and at least one work function adjusting metal layer positioned around the gate insulation layer and the outer perimeter of each nanowire of the plurality of vertically spaced-apart nanowires of the first and second stacked nanowire structures, wherein the at least one work function adjusting metal layer has an upper surface that is positioned above an upper surface of the layer of insulating material and above an uppermost nanowire of each of the first and second stacked nanowire structures. Furthermore, the disclosed nanowire device also includes at least one conductive material positioned above the upper surface of the work function adjusting metal layer, wherein the at least one conductive material is a part of a gate structure for the nanowire device. Additionally, a gate cap layer is positioned above the at least one conductive material.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
DETAILED DESCRIPTIONVarious illustrative embodiments of the present subject matter are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various systems, structures and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Generally, the present disclosure is directed to various methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices. As shown more fully below, an illustrative nanowire device, which, in the depicted example, is a gate-all-around (GAA) FinFET device, may be formed using the methods disclosed herein. As will be readily apparent, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the device 100 disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
In the depicted examples, the device will be disclosed in the context of forming a gate-all-around (GAA) FinFET device. However, the present disclosure should not be considered to be limited to the examples depicted herein. The substrate 102 may include a variety of configurations, such as a bulk silicon configuration, an SOI configuration or a SiGeOI configuration. Thus, the terms “substrate” or “semiconducting substrate” should be understood to cover all substrate configurations. The substrate 102 may also be made of materials other than silicon.
As shown in a simplistic plan drawing shown in the upper right corner of
With continuing reference to
As will be appreciated and understood by those skilled in the art after a complete reading of the present application, there are several novel methods and devices disclosed herein, and the inventions disclosed herein may provide several benefits. Among other things, the inventions disclosed herein provide a means to maximize the silicide to source/drain contact area, and they also allow for an increased contact metal volume as compared to prior art processing techniques and devices. Moreover, since the gate structure 150 is “buried” under insulating material, there is more room for the formation of the various contact structures discussed above. Other advantages and benefits of the various inventions disclosed herein will be recognized and appreciated by those skilled in the art after a complete reading of the present application. Additionally, although the present invention has been disclosed in the context of forming a nanowire device and a FinFET device, the presently disclosed inventions may be employed on traditional planar transistor devices. Lastly, the inventions disclosed herein have been disclosed in the context of using a replacement gate process flow to form the gate structure 150. However, the methods and devices disclosed herein may also be employed when forming gate structures for any type of device using traditional gate-first processing techniques, e.g., where the final gate structure includes a polysilicon gate electrode and a silicon dioxide gate insulation layer.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A semiconductor device, comprising:
- a source/drain region;
- a gate structure;
- a gate cap layer positioned above said gate structure;
- a sidewall spacer positioned adjacent to opposite sides of said gate structure;
- a first epi semiconductor material positioned in said source/drain region, said first epi semiconductor material having a first lateral width at an upper surface thereof;
- a second epi semiconductor material positioned on said first epi semiconductor material, said second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of said sidewall spacer and having a second lateral width at an upper surface thereof that is greater than said first lateral width; and
- a metal silicide region positioned on said upper surface of said second epi semiconductor material.
2. The semiconductor device of claim 1, wherein said first and second epi semiconductor materials comprise a same semiconductor material.
3. The semiconductor device of claim 1, wherein said second epi semiconductor material extends laterally over and covers a portion of said gate cap layer.
4. The semiconductor device of claim 1, further comprising a layer of insulating material positioned above said gate cap layer and said sidewall spacer, wherein said second epi semiconductor material extends laterally over and covers a portion of said layer of insulating material.
5. The semiconductor device of claim 1, wherein said gate structure comprises a gate insulation layer and a gate electrode positioned above said gate insulation layer.
6. The semiconductor device of claim 5, wherein said gate insulation layer comprises a high-k dielectric material and said gate electrode comprises at least one layer of a work function adjusting metal material.
7. The semiconductor device of claim 5, wherein said gate insulation layer comprises silicon dioxide and said gate electrode comprises a layer of polysilicon.
8. The semiconductor device of claim 1, further comprising a conductive contact structure that is conductively coupled to said metal silicide region.
9. The semiconductor device of claim 1, wherein said first epi semiconductor material directly contacts a channel region of said semiconductor device.
10. The semiconductor device of claim 9, wherein said semiconductor device is a nanowire device and said channel region comprises a plurality of vertically spaced-apart nanowires.
11. The semiconductor device of claim 9, wherein said semiconductor device is a gate-all-around FinFET device and said channel region comprises a vertically elongated fin structure.
12. A nanowire device, comprising:
- a stacked nanowire structure comprising a plurality of vertically spaced-apart nanowires;
- a source/drain region positioned adjacent to said stacked nanowire structure;
- a gate structure positioned around and above said stacked nanowire structure;
- a gate cap layer positioned above said gate structure;
- a sidewall spacer positioned adjacent to opposite sides of said gate structure;
- a layer of insulating material positioned above said gate cap layer and above an uppermost end of said sidewall spacer;
- a first epi semiconductor material positioned in said source/drain region, said first epi semiconductor material directly contacting an end surface of each of said plurality of vertically spaced-apart nanowires and having a first lateral width at an upper surface thereof; and
- a second epi semiconductor material positioned on said first epi semiconductor material and having a second lateral width at an upper surface thereof that is greater than said first lateral width, said second epi semiconductor material extending laterally over and covering at least a portion of said layer of insulating material and at least a portion of said uppermost end of said sidewall spacer.
13. The nanowire device of claim 12, further comprising a metal silicide region positioned on said upper surface of said second epi semiconductor material.
14. The nanowire device of claim 13, further comprising a conductive contact structure that is conductively coupled to said metal silicide region.
15. The semiconductor device of claim 12, wherein said first and second epi semiconductor materials comprise a same semiconductor material.
16. The semiconductor device of claim 12, wherein said gate structure comprises a gate insulation layer comprising silicon dioxide and a gate electrode comprising a layer of polysilicon material positioned above said gate insulation layer.
17. The nanowire device of claim 12, wherein each of said plurality of vertically spaced-apart nanowires has an outer perimeter when viewed in a cross-section taken through each of said respective nanowires in a direction corresponding to a gate width direction of said nanowire device, said gate structure comprising:
- a gate insulation layer positioned around said outer perimeter of each of said plurality of vertically spaced-apart nanowires, said gate insulation layer comprising a high-k dielectric material;
- at least one work function adjusting metal layer positioned around said gate insulation layer and said outer perimeter of each of said plurality of vertically spaced-apart nanowires, wherein said at least one work function adjusting metal layer has an upper surface that is positioned above an upper surface of said plurality of vertically spaced-apart nanowires; and
- at least one conductive material positioned above said upper surface of said work function adjusting metal layer, wherein said gate cap layer is positioned above said at least one conductive material.
18. A nanowire device, comprising:
- laterally spaced-apart first and second stacked nanowire structures, each of said first and second stacked nanowire structures comprising a plurality of vertically spaced-apart nanowires, wherein each nanowire of said plurality of vertically spaced-apart nanowires has an outer perimeter when viewed in a cross-section taken through each of said respective nanowires in a direction corresponding to a gate width direction of said nanowire device;
- a layer of insulating material positioned between said laterally spaced-apart first and second stacked nanowire structures;
- a gate insulation layer positioned around said outer perimeter of each nanowire of said plurality of vertically spaced-apart nanowires of said first and second stacked nanowire structures;
- at least one work function adjusting metal layer positioned around said gate insulation layer and said outer perimeter of each nanowire of said plurality of vertically spaced-apart nanowires of said first and second stacked nanowire structures, wherein said at least one work function adjusting metal layer has an upper surface that is positioned above an upper surface of said layer of insulating material and above an uppermost nanowire of each of said first and second stacked nanowire structures;
- at least one conductive material positioned above said upper surface of said work function adjusting metal layer, wherein said at least one conductive material comprises a part of a gate structure for said nanowire device; and
- a gate cap layer positioned above said at least one conductive material.
19. The nanowire device of claim 18, further comprising:
- a first epi semiconductor material positioned in a source/drain region of said nanowire device, said first epi semiconductor material having a first lateral width at an upper surface thereof; and
- a second epi semiconductor material positioned on said first epi semiconductor material, said second epi semiconductor material having a second lateral width at an upper surface thereof that is greater than said first lateral width.
20. The nanowire device of claim 19, further comprising a sidewall spacer positioned adjacent to opposite sides of said gate structure, wherein said second epi semiconductor material extends laterally over and covers at least a portion of an uppermost end of said sidewall spacer.
Type: Application
Filed: Mar 10, 2016
Publication Date: Jun 30, 2016
Inventors: Ruilong Xie (Niskayuna, NY), William J. Taylor, JR. (Clifton Park, NY), Ajey Poovannummoottil Jacob (Watervliet, NY)
Application Number: 15/065,998