METHOD OF TRIMMING FIN STRUCTURE
A method of trimming a fin structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure cladding the fin structure, in which the epitaxy structure has a first lattice plane with Miller index (111), a second lattice plane with Miller index (100) and a third lattice plane with Miller index (110); and (iii) removing the epitaxy structure and a portion of the fin structure to obtain a trimmed fin structure.
The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological progress in IC manufacture has produced several generations of ICs, and each generation fabricates smaller and more complex circuits than the previous generation. Currently, the semiconductor industry has progressed into nanometer technology nodes for higher device density and better electrical performance, and a variety of challenges from fabrication and design have led semiconductor technologies to three dimensional designs, such as fin-like field effect transistors (FinFETs). A typical FinFET is fabricated with a thin “fin” extending on a substrate. The channel of the FinFET is formed in the fin. In addition, a gate is formed to wrap the fin, and therefore a tri-gate structure is fabricated. It is beneficial to have a gate on three sides of the channel that allows the gate to control the channel from several sides. FinFET devices further include strained source/drain features to enhance carrier mobility and improve device performance. However, as device scaling down continues, conventional techniques have not been entirely satisfactory in all respects.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “under,” “below,” “lower,” “above,” “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure relates generally to a method of trimming a fin structure for an active device such as for example a fin-like field effect transistor (FinFET). In the FinFET, when the width of the fin structure is less than certain dimension such as for example 16 nm, the carrier mobility of the FinFET is unsatisfied, and a strain inducing layer covering the fin structure is used to enhance the carrier mobility. Nevertheless, when the strain inducing layer is formed on the fin structure, the width of the fin structure is unfavorably increased. Accordingly, in order to shrink the fin width, the fin structure is trimmed prior to forming the strain inducing layer. However, conventional fin-trimming techniques suffer problems in that a tip-top is formed on the top of the fin structure, and that leads to a poor electrical performance.
Accordingly, the present disclosure provides a novel method of trimming a fin structure that at least resolves the issue of the tip-top. Various embodiments of the present disclosure will be described in detail hereinafter.
As shown in
According to various embodiments of the present disclosure, the fin structure 110 includes crystalline silicon. In some embodiments, the top surface of the fin structure 110 has a lattice plane with Miller index (100), and the sidewall of the fin structure 110 has a lattice plane with Miller index (110). In yet some embodiments, the fin structure 110 may include a lower part containing silicon (Si) and an upper part containing silicon germanium (SiGe). In yet some embodiments, the fin structure 110 may be doped during deposition by adding impurities to the source/drain material of the epitaxy process or subsequent to its deposition process by an ion implantation process. In various examples, the fin structure 110 has a width d1 which is ranged from about 5 nm to about 25 nm. In some examples, the width d1 may be about 5 nm to about 15 nm. In yet some examples, the width d1 may be about 10 nm to about 20 nm. In yet some examples, the width d1 may be about 15 nm to about 25 nm. One skilled in the art will appreciate that a single fin structure 110 is shown for illustrative purposes only. As such, some embodiments may include a plurality of fin structures 110.
Referring to
In some embodiments, the epitaxy structure 120 includes a first lattice plane 121, a second lattice plane 123, a third lattice plane 125 and a fourth lattice plane 127. In some examples, the first lattice plane 121 and the second lattice plane 123 form a top angle Z of the epitaxy structure 120, and the top angle Z may be about 50 degrees to about 60 degrees. In yet some examples, each of the first, second, third and fourth lattice planes 121, 123, 125, 127 has Miller index (111).
In yet some embodiments, the epitaxy structure 120 has a maximum width d2 that is about 2 folds to about 7 folds of the width d1 of the fin structure 110. In some examples, the maximum width d2 may be about 2.5 folds to about 6 folds of the width d1 of the fin structure 110. For example, the maximum width d2 of the epitaxy structure 120 may be about 25 nm to about 60 nm. In some examples, the width d2 may be about 25 nm to about 40 nm. In yet some examples, the width d2 may be about 30 nm to about 50 nm. In yet some examples, the width d2 may be about 40 nm to about 60 nm.
Subsequently, as shown in
Thereafter, as illustrated in
In some embodiments, the exposed portion 122 of the epitaxy structure 120 has a width d3 that is greater than the width d1 (shown in
As illustrated in
Thereafter, as illustrated in
As shown in
Subsequently, the structure illustrated in
For many semiconductor materials such as silicon, silicon germanium or the like, the etching rate depends upon the orientations of the lattice planes. For instance, lattice planes with Miller index (100) have fast etching rates in the etching process, lattice planes with Miller index (110) have moderate etching rates, and lattice planes with Miller index (111) have slow etching rates. Significantly, the difference in etching rates between different lattice planes leads to the tip-top issue in typical fin-trimming approaches. Accordingly, the shape of the remaining epitaxy structure 120a with certain lattice planes shown in
Accordingly, the shape of the remaining epitaxy structure 120a may be well controlled by the method illustrates in
As shown in
Referring to
With reference to
As illustrated in
Referring to
In some embodiments, the width d6 of the epitaxy layer 150 is greater than the width d1 of the fin structure 110. In some examples, the width d6 of the epitaxy layer 150 may be about 1.5 folds to about 4 folds of the width d1 of the fin structure 110. In yet some embodiments, the width d6 of the epitaxy layer 150 is less than the maximum width d2 of the epitaxy structure 120.
As shown in
With reference to
As illustrated in
The trimmed fin structure 110a illustrated in Fig, 2H exhibits a cross section of substantially rectangular shape according to various embodiments of the present disclosure. Significantly the thickness and width of the epitaxy layer 150 may be independently controlled through the operations illustrated in
Other features may optionally be formed after the trimmed fin structure 110a is fabricated.
As shown in
In some embodiments, a gate structure 204 may be formed over a portion of the fin structure 110a, and the gate structure 204 traverses the fin structure 110a. In some embodiments, the gate structure 204 may include a gate electrode and a gate dielectric layer. The gate dielectric layer may be made of dielectric material such as for example silicon oxide, silicon nitride, high-k dielectric material, and/or other suitable dielectric material. Examples of high-k dielectric material include, but are limited to, HfZrO, HfSiON, HfTaO, HfSiO, HfTiO, HfO2, zirconium oxide, aluminum oxide, or the like. The gate electrode may include any suitable material such as for example polysilicon, copper, titanium, aluminum, tantalum, tungsten, molybdenum, nickel silicide, cobalt silicide, or other suitable materials. The gate structure 204 may further include spacers 206, as illustrated in
In addition, before or after the spacers 206 are formed, doped regions such as source and drain regions may be formed in the fin structure 110a according to some embodiments of the present disclosure. The gate structure 204 traversing the fin structure 110a may separate the doped source and drain regions. The source and drain regions may include lightly doped regions and/or heavily doped source. The doping species depend on the type of the device being fabricated, such as a p-channel FETs (PFETs) or an n-channel FETs (NFETs). The doped source and drain regions may be formed by implantation processes, diffusion process, and/or other suitable processes. In some embodiments, an annealing process may further be performed to activate the source and drain regions. The annealing processes may be, for example, a laser annealing process, a rapid thermal annealing (RTA) process, and/or other suitable annealing processes.
As illustrated in
In yet some embodiments, as illustrated in
As illustrated in
Other features may continuously be fabricated, including for example, forming an interconnect metal routing layer, an inter-layer dielectric (ILD) layers, via contacts, inter-metal dielectric (IMD) layers and metallic connecting wire and/or other suitable features, according to various embodiments of the present disclosure.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Advantages of various embodiments of the present disclosure include providing novel methods of trimming fin structures for active devices such as FinFETs. The methods disclosed herein provide an excellent shape of the fin structure, and therefore the FinFET exhibits excellent electrical performances such as for example a low leakage current and a high ratio of turn-on current to turn-off current (Ion/Ioff). The epitaxy structure with certain shapes and lattice planes disclosed herein compensates the difference in etching rates between different lattice planes during the etching process, and thereby obtaining an excellent cross section of the fin structure.
In accordance with one aspect of some embodiments, a method includes the operations described below. A fin structure is formed over a substrate. An epitaxy structure is formed on the fin structure. A planar layer is formed to cover the epitaxy structure. Portions of the planar layer and the epitaxy structure are removed such that a portion of the epitaxy structure is exposed out of the planar layer. A masking layer is formed over the exposed portion of the epitaxy structure. The planar layer and the epitaxy structure are patterned by using the masking layer, and thereby a remaining portion of the planar layer and a remaining epitaxy structure are obtained. The masking layer and the remaining portion of the planar layer are removed. Thereafter, the remaining epitaxy structure and a portion of the fin structure are removed so as to form a trimmed fin structure.
In accordance with another aspect of some embodiments, a method includes the operations described below. A fin structure is formed over a substrate. An epitaxy structure is formed on the fin structure. A planar layer is formed to cover the epitaxy structure. Portions of the planar layer and the epitaxy structure are removed such that a portion of the epitaxy structure is exposed out of the planar layer. An epitaxy layer is epitaxially grown on the exposed portion of the epitaxy structure. The planar layer and the epitaxy structure are patterned so that a remaining portion of the planar layer and a remaining epitaxy structure are obtained. The remaining portion of the planar layer is removed. Thereafter, the remaining epitaxy structure and portions of the epitaxy layer and the fin structure are removed so as to form a trimmed fin structure.
In accordance with another aspect of some embodiments, a method includes the operations described below. A fin structure is formed over a substrate. An epitaxy structure is epitaxially grown on the fin structure such that fin structure is clad in the epitaxy structure. The epitaxy structure includes a first lattice plane with Miller index (111), a second lattice plane with Miller index (100) and a third lattice plane with Miller index (110), and the first lattice plane with Miller index (111) forms an undercut of the epitaxy structure. The epitaxy structure and a portion of the fin structure are subsequently removed to obtain a trimmed fin structure.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A method, comprising:
- forming a fin structure over a substrate;
- forming an epitaxy structure on the fin structure;
- forming a planar layer covering the epitaxy structure;
- removing portions of the planar layer and the epitaxy structure such that a portion of the epitaxy structure is exposed out of the planar layer;
- forming a masking layer over the exposed portion of the epitaxy structure;
- patterning the planar layer and the epitaxy structure by using the masking layer, and thereby obtaining a remaining portion of the planar layer and a remaining epitaxy structure;
- removing the masking layer and the remaining portion of the planar layer; and
- removing the remaining epitaxy structure and a portion of the fin structure.
2. The method according to claim 1, wherein the act of forming the epitaxy structure comprises forming a first, a second, a third and a fourth lattice plane of the epitaxy structure.
3. The method according to claim 2, wherein the first lattice plane and the second lattice plane form a top angle of the epitaxy structure, and the top angle is about 50 degrees to about 60 degrees.
4. The method according to claim 2, wherein each of the first, second, third and fourth lattice planes has a Miller index (111).
5. The method according to claim 2, wherein the epitaxy structure has a maximum width that is about 2 folds to about 7 folds of a width of the fin structure.
6. The method according to claim 1, wherein the act of forming the planar layer comprises coating a flowable oxide over the substrate.
7. The method according to claim 1, wherein the act of removing the portions of the planar layer and the epitaxy structure comprises forming a lattice plane of the epitaxy structure by a chemical mechanical polishing (CMP) process, and the lattice plane has a Miller index (100).
8. The method according to claim 1, wherein the exposed portion of the epitaxy structure has a width that is greater than a width of the fin structure.
9. The method according to claim 1, wherein the exposed portion of the epitaxy structure has a lattice plane, and a distance between the a lattice plane and a top of the fin structure is ranged from about 5 nm to about 30 nm.
10. The method according to claim 1, wherein the act of forming the masking layer comprises forming a patterned photoresist that has a width of greater than a width of the exposed portion.
11. The method according to claim 1, wherein the masking layer has a width that is about 1.5 folds to about 4 folds of a width of the fin structure.
12. The method according to claim 1, wherein the masking layer has a width that is greater than a width of the exposed portion and less than a maximum width of the epitaxy structure in the act of forming the masking layer.
13. The method according to claim 1, wherein the remaining portion of the planar layer comprises a first portion and a second portion, and the first portion is spaced apart from the second portion by the remaining epitaxy structure.
14. The method according to claim 13, wherein the first portion is located between the masking layer and the remaining epitaxy structure, and the second portion is located between the remaining epitaxy structure and the substrate.
15. The method according to claim 1, wherein the act of patterning the planar layer and the epitaxy structure comprises forming a lattice plane of the epitaxy structure, and the lattice plane has a Miller index (110).
16. The method according to claim 1, wherein the act of removing the remaining epitaxy structure and the portion of the fin structure comprises applying an etchant containing tetramethylammonium hydroxide (TMAH).
17. A method, comprising:
- forming a fin structure over a substrate;
- forming an epitaxy structure on the fin structure;
- forming a planar layer covering the epitaxy structure;
- removing portions of the planar layer and the epitaxy structure such that a portion of the epitaxy structure is exposed out of the planar layer;
- epitaxially growing an epitaxy layer on the exposed portion of the epitaxy structure;
- patterning the planar layer and the epitaxy structure, and thereby obtaining a remaining portion of the planar layer and a remaining epitaxy structure;
- removing the remaining portion of the planar layer; and
- removing the remaining epitaxy structure and portions of the epitaxy layer and the fin structure.
18. The method according to claim 17, wherein the act of patterning the planar layer and the epitaxy structure comprises using the epitaxy layer as a hard mask.
19. The method according to claim 17, wherein the act of patterning the planar layer and the epitaxy structure comprises forming a lattice plane having a Miller index (110) of the remaining epitaxy structure.
20. A method of trimming a fin structure for a fin-like field effect transistor, comprising:
- forming a fin structure on a substrate;
- epitaxially growing an epitaxy structure cladding the fin structure, wherein the epitaxy structure comprises a first lattice plane with Miller index (111), a second lattice plane with Miller index (100) and a third lattice plane with Miller index (110), and the first lattice plane with Miller index (111) forms an undercut of the epitaxy structure; and
- removing the epitaxy structure and a portion of the fin structure to obtain a trimmed fin structure.
Type: Application
Filed: Jan 15, 2015
Publication Date: Jul 21, 2016
Inventors: Kuo-Sheng CHUANG (Hsinchu City), You-Hua CHOU (Hsinchu City)
Application Number: 14/597,700