Contact Formation for Split Gate Flash Memory
An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.
This patent application is a divisional of U.S. patent application Ser. No. 13/968,772, filed on Aug. 16, 2013, titled “Contact Formation for Split Gate Flash Memory,” which is incorporated by reference herein as if reproduced in its entirety.
BACKGROUNDFlash memories are commonly used in integrated circuits. There are many designs for the flash memories. In one of the designs, a flash memory includes a gate dielectric over an active region, a select gate over the gate dielectric, and a charge storage layer on a side of the select gate and separated from the active region by an insulating film. A memory gate is on an opposite side of the storage layer than the select gate. A source region and a drain region are formed in the active region, with the select gate, the charge storage layer, and the select gate between the source and drain regions.
The memory gate and the select gate are formed of polysilicon. The select gate and the memory gate have different structures, with the memory gate covered by an insulating film, and the select gate not covered by the dielectric layer. Accordingly, to form contact plugs to connect to the memory gate and the select gate, two separate photolithography processes are needed. The cost of manufacturing the integrated circuit is thus increased. In addition, since the contact plugs are landed on the polysilicon of the memory gate and the select gate, with no silicide therebetween, the contact resistance is high.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
An electrical connection to an embedded split gate flash memory and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the electrical connections to the embedded split gate flash memory are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Select gates 22 and memory gates 24 are formed as long strips having lengthwise directions extending in the column direction of memory array 20. The contact plugs for connecting to select gates 22 and memory gates 24 are formed in contact pad regions 34 (including regions 34A and 34B), which are on the opposite ends of memory array 20. The rectangles 38 are illustrated to show the positions for forming contact plugs, although the contact plugs have not been formed at this step.
As shown in
Referring to
Referring to
Next, as shown in
A conductive material is then formed to fill recesses 68 and 408, and the resulting structure is shown in
A planarization step, which is performed to remove excess portions of conductive material 70 and hard mask layer 66, is then performed, and the resulting structure is shown in
Referring to
The initial structure of these embodiments is essentially the same as shown in
Hard mask layer 66 is then used as an etching mask to remove exposed gate electrode 406 (
In the above-disclosed embodiments, select gates 72 (
In the embodiments of the present disclosure, by replacing the polysilicon of the select gates and memory gates in the split gate flash memory devices with metal-containing gates, the respective contact resistance is reduced. Furthermore, the replacement of the select gates and memory gates may be performed simultaneously as the replacement of IO devices, logic devices, and/or SRAM devices. Therefore, the manufacturing cost is not increased.
In accordance with some embodiments, an integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array.
In accordance with other embodiments, an integrated circuit structure includes a plurality of flash memory cells forming a memory array. Each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array. The select gate electrode further includes a second portion electrically connected to the first portion, wherein the second portion comprises a metal. A memory gate electrode includes a first portion forming memory gates of the column of the memory array, and a second portion, which includes a polysilicon bottom portion and a metal-containing top portion. The metal-containing top portion and the second portion of the select gate electrode are formed of a same material with same elements and same percentages of the elements, and have top surfaces level with each other.
In accordance with yet other embodiments, a method includes removing a first portion of a select gate electrode of a flash memory array. The select gate electrode further includes a second portion electrically connected to the first portion, wherein the second portion remains after the first portion is removed. The second portion forms select gates of a column of memory cells of the flash memory array. The method further includes filling a metal-containing material in a first recess left by the first portion of the select gate electrode.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims
1. A method comprising:
- providing a flash memory array comprising a column of memory cells and a select gate electrode on a substrate, the select gate electrode comprising a first portion and a second portion electrically connected to the first portion, the second portion of the select gate electrode coupled to select gates of the column of memory cells; and
- replacing the first portion of the select gate electrode with a metal-containing material, the second portion remaining after the first portion is replaced.
2. The method of claim 1, further comprising:
- simultaneously removing a gate electrode of a Metal-Oxide-Semiconductor (MOS) device on the substrate to form a first recess while replacing the first portion of the select gate electrode, the MOS device being a device selected from a group consisting essentially of an input/output device, a logic device, and a Static Random Access Memory (SRAM) device; and
- simultaneously forming the metal-containing material in the first recess while forming the metal-containing material in the first recess.
3. The method of claim 1, further comprising:
- removing a first portion of a dielectric layer overlapping a first portion of a memory gate electrode of the flash memory array to form a second recess, the memory gate electrode further comprising a second portion of the memory gate electrode electrically connected to the first portion of the memory gate electrode, the second portion of the memory gate electrode coupled to memory gates of the column of memory cells;
- filling a conductive hard mask layer in the second recess; and
- simultaneously forming the metal-containing material in the second recess and over the conductive hard mask layer while replacing the first portion of the select gate electrode.
4. The method of claim 3, wherein the removing the first portion of the select gate electrode comprises etching polysilicon using an extension portion of the conductive hard mask layer as an etching mask.
5. The method of claim 3, wherein the dielectric layer further comprises a second portion of the dielectric layer overlapping the second portion of the memory gate electrode, and wherein the second portion of the dielectric layer remains after the first portion of the dielectric layer is removed.
6. The method of claim 1 further comprising:
- forming an Inter-Layer Dielectric (ILD) over the select gate electrode; and
- forming a contact plug extending through the ILD, wherein the contact plug comprises a bottom surface in contact with a top surface of the metal-containing material.
7. A method comprising:
- providing a memory device comprising a memory array, a select gate electrode, and a memory gate electrode, the select gate electrode having a first segment extending into the memory array and a second segment outside of the memory array, the memory gate electrode having a first segment extending into the memory array and a second segment outside of the memory array;
- removing a first portion of the second segment of the memory gate electrode to form first openings;
- removing the second segment of the select gate electrode to form second openings; and
- forming a metal-containing material in the first openings and the second openings.
8. The method of claim 7, further comprising:
- forming an ILD over the memory device, the select gate electrode, and the memory gate electrode; and
- forming conductive plugs in the ILD contacting the second segment of the select gate electrode and the second segment of the memory gate electrode.
9. The method of claim 8, wherein a first one of the conductive plugs contacts the metal-containing material in the first openings.
10. The method of claim 8, where a first one of the conductive plugs contacts the second segment of the memory gate electrode.
11. The method of claim 7, wherein removing the first portion of the second segment of the memory gate electrode comprises:
- forming a photoresist over the memory device;
- patterning openings in the photoresist over the second segment of the select gate electrode and the second segment of the memory gate electrode; and
- removing the first portion of the second segment of the memory gate electrode with an etching selective to a material of the memory gate electrode.
12. The method of claim 7, further comprising:
- before removing the second segment of the select gate electrode, forming a hard mask over the memory array, the first segment of the select gate electrode, and the first segment and the second segment of the memory gate electrode; and
- after forming the hard mask, etching the second segment of the select gate electrode using the hard mask as an etching mask to form the second openings.
13. The method of claim 12, wherein forming the metal-containing material in the first openings comprises depositing the metal-containing material over the hard mask and the first segment of the memory gate electrode.
14. The method of claim 7, wherein prior to removing the first portion of the second segment of the memory gate electrode, the first segment and the second segment of the memory gate electrode comprise the first portion over a second portion, the first portion being a dielectric, the second portion being polysilicon, and wherein the method further comprises removing the dielectric from the first segment of the memory gate electrode.
15. The method of claim 7, wherein the first segment and the second segment of the select gate electrode comprise polysilicon.
16. The method of claim 7, further comprising planarizing the select gate electrode and the memory gate electrode, the select gate electrode and the memory gate electrode having top surfaces level with each other after the planarizing.
17. A method comprising:
- providing a plurality of flash memory cells on a substrate, each of the plurality of flash memory cells comprising a select gate and a memory gate;
- forming a select gate electrode for the select gates over the substrate, the forming comprising forming a first portion of a first conductive material coupled to the select gates, and forming a second portion of a second conductive material different from the first conductive material, the first portion and the second portion continuously connected to form a straight conductive strip in a plan view; and
- planarizing the select gate electrode, the first portion and the second portion being the same height after the planarizing.
18. The method of claim 17, wherein forming the select gate electrode comprises forming the first conductive material from polysilicon and the second conductive material from metal.
19. The method of claim 17, further comprising forming a memory gate electrode for the memory gates.
20. The method of claim 19, further comprising:
- forming an ILD over the plurality of flash memory cells, the select gate electrode, and the memory gate electrode; and
- forming conductive plugs in the ILD contacting the select gate electrode and the memory gate electrode.
Type: Application
Filed: May 31, 2016
Publication Date: Sep 22, 2016
Patent Grant number: 10068773
Inventors: Harry-Hak-Lay Chuang (Singapore), Wei-Cheng Wu (Zhubei City), Ya-Chen Kao (Fuxing Township), Chin-Yi Huang (Hsin-Chu)
Application Number: 15/169,270