Method of Manufacturing a Semiconductor Device by Plasma Doping
A method of manufacturing a semiconductor device includes forming a superjunction field effect transistor by: forming trenches in a semiconductor body from a first side: forming charge compensation layers by doping parts of the semiconductor body via sidewalls of the trenches by introducing dopants by plasma doping; after forming the charge compensation layers, widening a profile of the dopants introduced by plasma doping by diffusion caused by a thermal heating process; and forming a drain contact at a second side opposite to the first side. A surface concentration of the dopants introduced by plasma doping via a unit area of the sidewalls is at least five times larger than a concentration of dopants in a mesa region of the semiconductor body between neighboring trenches which corresponds to N, wherein N is a net doping of the semiconductor body between the neighboring trenches.
A key component in semiconductor applications is a solid state switch. As an example, switches turn loads of automotive applications or industrial applications on and off. Solid state switches typically include, for example, field effect transistors (FETs) like metal-oxide-semiconductor FETs (MOSFETs) or insulated gate bipolar transistors (IGBTs).
Key demands on solid state switches are low on-state resistance (Ron) and high breakdown voltage (Vbr). Minimizing the on-state resistance is often at the expense of the breakdown voltage. Therefore, a trade-off between Ron and Vbr has to be met.
Superjunction structures are widely used to improve a trade-off between the on-state resistance and the breakdown voltage. In a conventional n-channel superjunction device, alternating n-doped and p-doped regions replace one comparatively lower n-doped drift zone. In an on-state, current flows through the n-doped regions of the superjunction device which lowers the Ron. In an off or blocking state, the p-doped regions and the n-doped regions deplete or compensate each other to provide a high Vbr. A compensation structure design is one key element for improving the trade-off between Ron and Vbr.
Accordingly, a method of manufacturing a superjunction device and a superjunction device with an improved compensation structure design is needed.
SUMMARYAccording to an embodiment of a method of manufacturing a semiconductor device, the method includes forming a trench in a semiconductor body. The method further includes doping a part of the semiconductor body via sidewalls of the trench by plasma doping.
According to an embodiment of a semiconductor device, the semiconductor device includes a first semiconductor region of a first conductivity type at a sidewall of a trench extending into a semiconductor body from a first side. The semiconductor body further includes a drift zone of the first conductivity type. The semiconductor device further includes a first semiconductor layer over the first semiconductor region in the trench. The first semiconductor layer is of a second conductivity type complementary to the first conductivity type. The first conductivity type of the first semiconductor region is determined by a first species of dopants in the first semiconductor region. A doping profile of the first species of dopants declines from a maximum in the first semiconductor region to a minimum or to a minimum doping plateau in the drift zone. A value of the doping at the maximum is at least a factor of 10 higher than the doping at the minimum or at the minimum doping plateau.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of the specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain principles of the invention. Other embodiments of the invention and many of the intended advantages will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, “over”, “above”, “below”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing processes have been designated by the same references in the different drawings if not stated otherwise.
The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die.
The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.
As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together—intervening elements may be provided between the “coupled” or “electrically coupled” elements. The term “electrically connected” intends to describe a low-ohmic electric connection between the elements electrically connected together.
In this specification, n-doped may refer to a first conductivity type while p-doped is referred to a second conductivity type. It goes without saying that the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some Figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type. For example, “n−” means a doping concentration which is less than the doping concentration of an “n”-doping region while an “n+”-doping region has a larger doping concentration than the “n”-doping region, Indicating the relative doping concentration does not, however, mean that doping regions of the same relative doping concentration have the some absolute doping concentration unless otherwise stated. For example, two different n+ regions can have different absolute doping concentrations. The same applies, for example, to an n+ and a p+ region.
Specific embodiments described in this specification pertain to, without being limited thereto, power semiconductor devices which are controlled by field-effect and particularly to unipolar devices such as MOSFETs.
The term “field-effect” as used in this specification intends to describe the electric field mediated formation of an “inversion channel” and/or control of conductivity and/or shape of the inversion channel in a semiconductor channel region.
In the context of the present specification, the term “MOS” (metal-oxide-semiconductor) should be understood as including the more general term “MIS” (metal-insulator-semiconductor). For example, the term MOSFET (metal-oxide-semiconductor field-effect transistor) should be understood to include FETs having a gate insulator that is not an oxide, i.e., the term MOSFET is used in the more general term meaning IGFET (insulated-gate field-effect transistor) and MISFET, respectively.
The semiconductor body may be a pre-processed single-crystalline semiconductor substrate, for example a single-crystalline silicon substrate (Si substrate), a SiC substrate, a GaN substrate, a GaAs substrate or a silicon-on-insulator substrate. The semiconductor body may include none, one or a plurality of doped and/or undoped layers on the single-crystalline semiconductor substrate, e.g. epitaxial semiconductor layers. As an example, a thickness of the semiconductor layer(s) formed on the single-crystalline semiconductor substrate as well as a doping of the one or several layers may be appropriately chosen with regard to a desired voltage blocking capability of the semiconductor device that is to be formed in the semiconductor body. In particular the doping level of the semiconductor body should be chosen in such a way that the charge balance of the final compensation device is adequate for a desired blocking behavior.
The trench may be formed by an appropriate process, e.g. dry and/or wet etching As an example, the trench may be formed in a silicon body by an anisotropic plasma etch process, e.g. reactive ion etching (RIE) using an appropriate etch gas, e.g. at least one of Cl2, Br2, CCl4, CHCl3, CHBr3, BCl3, HBr. According to an embodiment, sidewalls of the trench may be slightly tapered, e.g. including a taper angle between 88° and 90°. Slightly tapered trench sidewalls may be beneficial with regard to avoiding trench cavities when filling up trenches.
Plasma doping of the part of the semiconductor body via sidewalls of the trench allows high dose implants at low energies and is also known as PLAD (plasma doping) or PIII (plasma immersion ion implantation). These methods allow for a precise doping of the part of the semiconductor body at the trench sidewalls. A conformal doping of the part of the semiconductor body at the trench sidewalls can be achieved by applying a voltage to a substrate surrounded by a radio frequency (RF) plasma including a dopant gas. Collisions between ions and neutral atoms as well as the biasing of the substrate lead to a broad annular distribution of the dopants allowing for a homogeneous doping over the trench sidewalls. Also a small vertical gradient in dose of doping in the part of the semiconductor body may be achieved by plasma doping. This allows for a vertical variation of a degree of charge compensation improving stability of manufacture and/or avalanche robustness. A vertical variation of dose of doping may be smaller 20%, or smaller than 10% or smaller than 5%.
When doping with PLAD, the semiconductor substrate, e.g. a semiconductor wafer, is exposed to a plasma including ions of dopants. These ions are accelerated by an electric field towards the substrate and are implanted into an exposed surface of the substrate. An implanted dose can be adjusted or controlled via DC voltage pulses, e.g. negative voltage pulses. A Faraday system allows to adjust or control the dose. Two sets of coils, i.e. a horizontal coil and a vertical coil allow to generate the plasma and keep it homogeneous. An ion density can be adjusted via a distance between the coils and the substrate. Interaction between the vertical coils and the horizontal coils allows to adjust or control homogeneity and the ion density.
A penetration depth of the dopants into the semiconductor body and the implant dose may be adjusted via a pulsed DC voltage applied between the semiconductor substrate and a shield ring surrounding it.
According to an embodiment, doping the part of the semiconductor body by plasma doping includes introducing the dopants into the part of the semiconductor body via the sidewalls at a dose in a range of 5×1011 cm−2 to 5×1012 m−2, or in a range of 7×1011 cm−2 to 2×1012 cm−2. This comparatively low dose requires modifications of the pulsed DC voltage typically used. Typically doses exceeding 1015 cm−2 implanted by these techniques. According to an embodiment, a pulse distance of the DC voltage pulses is adjusted in a range of 100 μs to 10 ms, in particular between 500 μs and 5 ms. A DC voltage pulse rise time is set to a value smaller than 0.1 μs, for example. According to an embodiment a pulse width ranges between 0.5 μs to 20 μs, or between 1 μs to 10 μs.
According to an embodiment, the semiconductor body includes a drift zone of a first conductivity type. Doping the part of the semiconductor body by plasma doping includes doping the part of the semiconductor body with dopants of a second conductivity type complementary to the first conductivity type. According to one embodiment, the doped part of the semiconductor body constitutes a charge compensation region, e.g. a p-doped column between an n-doped drift zone of a superjunction semiconductor device. According to another embodiment, a transistor or diode device is formed as the semiconductor device and includes the doped part of the semiconductor body as a vertical edge termination structure. According to an embodiment, the semiconductor device is a power semiconductor device including a breakdown voltage or voltage blocking capability of at least 100 V or at least 300 V.
According to an embodiment, further to plasma doping of the part of the semiconductor at the sidewalls, a variation of doping along the vertical direction in a silicon semiconductor body may be achieved by high energy implantation of protons for n-doping or helium for p-doping. This allows to improve an avalanche ruggedness of the device.
Further process steps for manufacturing semiconductor zones, e.g. source, drain, body, highly doped contact zones, and gate structures, trench fillings, dielectric layers, interlevel dielectrics, conductive layers such as highly doped semiconductor layer(s) or metal layer(s) may follow to complete the semiconductor device.
As an example, a width w of the trench 216 may range between 0.1 μm to 15 μm or between 1 μm to 10 μm. A depth d of the trench 216 may range between 10 μm to 120 μm or between 20 μm to 60 μm. As an example, the depth d may be appropriately chosen with regard to a desired voltage blocking capability of the semiconductor device to be manufactured.
Referring to the schematic cross-sectional view of the semiconductor body 210 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 210 illustrated in
The outdiffusion barrier layer 224 and/or an optional insulating layer as part of the outdiffusion barrier layer 224 may be removed after diffusion, e.g. by an etch process, But in case of the deposition of silicon this is typically not necessary.
Referring to the schematic cross-sectional view of the semiconductor body 210 illustrated in
According to an embodiment, thermal heating is carried out to further widen a lateral doping profile of the p-doped part 218.
Referring to the schematic cross-sectional view of the semiconductor body 210 illustrated in
FIGS, 3A to 3F illustrate schematic cross-sectional views of an n−-doped semiconductor body 310 at different phases of processing a superjunction semiconductor device. A mask 312 is formed on a first side 314 of the semiconductor body 310. Patterning of the mask 312, e.g. by lithography, results in mask openings. Trenches 316 are formed from the first side 314 into the semiconductor body 310, e.g. by using an anisotropic etch process such as RE.
Dimensions of the trenches 316, e.g. a width w and a depth d, may be chosen as described with regard to the embodiment illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 310 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 310 illustrated in FIG, 3D, plasma doping by PLAD or PIII using a process gas configured for p-doping, e.g. BF3 and/or B2H6 is carried out. Plasma doping leads to p-doping of the first semiconductor layer 340. A penetration depth of the dopants, or, in other words, a thickness of a doped part 342 of the first semiconductor layer 340 after PLAD is comparatively low, e.g. in a range between 0.2 nm and 20 nm, or between 0.5 nm to 10 nm or even between 1 nm to 3 nm (
Further referring to the schematic cross-sectional view of the semiconductor body 310 illustrated in
Between plasma doping of the first semiconductor layer 340 and filling up the trenches 316, an outdiffusion barrier layer as illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 310 illustrated in
Further processes for manufacturing a superjunction semiconductor device follow. For further details in this regard, reference is drawn to
A lateral width of the profiles depends upon a thermal budget leading to a widening of the profiles by diffusion. A doping profile N of a species of n-dopants declines from a maximum Nmax in the part 318 to a minimum doping plateau Nmin in a drift zone being part of the semiconductor body 310 between the trenches 316. A value of the doping at the maximum Nmax is at least a factor of ten or a factor of twenty larger than the doping at the minimum plateau Nmin. Depending upon a degree of a lateral extension of the profile N. the minimum plateau may be a minimum. A doping profile P of a species of p-dopants has a maximum Pmax in the pad 342.
Dimensions of the trenches 416, e.g. a width w and a depth d, may be chosen as described with regard to the embodiment illustrated in
Plasma doping by PLAD or PIII using a process gas configured for n-doping, e.g. PF3 and/or PH3 is carried out. Plasma doping leads to n-doping of a pad 418 of the semiconductor body 410 at sidewalls 420a, 420b as well as at a bottom side 422 of the trenches 416 (
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional vie of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
Referring to the schematic cross-sectional view of the semiconductor body 410 illustrated in
The n-dose introduced into the part 418 as illustrated in FIGS, 4A, 4B defines an n-doping in drift zone parts 481a, 481b and 481c, The p-dose introduced into the part 442 as illustrated in
The above described embodiments allow to manufacture superjunction devices having a precise charge compensation and compact design with homogeneous trench sidewall doping.
Terms such as “first”, “second”, and the like, are used to describe various structures, elements, regions, sections, etc. and are not intended to he limiting. Like terms refer to like elements throughout the description.
The terms “having”, “containing”, “including”, “comprising” and the like are open and the terms indicate the presence of stated elements or features, but not preclude additional elements or features. The articles “a”, an and the are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may he substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Claims
1. A method of manufacturing a semiconductor device, the method comprising:
- forming a superjunction field effect transistor by:
- forming trenches in a semiconductor body from a first side;
- forming charge compensation layers by doping parts of the semiconductor body via sidewalls of the trenches by introducing dopants by plasma doping;
- after forming the charge compensation layers, widening a profile of the dopants introduced by plasma doping by diffusion caused by a thermal heating process; and
- forming a drain contact at a second side opposite to the first side,
- wherein a surface concentration of the dopants introduced by plasma doping via a unit area of the sidewalls is at least five times larger than a concentration of dopants in a mesa region of the semiconductor body between neighboring trenches which corresponds to N, wherein N is a net doping of the semiconductor body between the neighboring trenches.
2. The method of claim 1, wherein the semiconductor body is a silicon semiconductor body.
3. The method of claim 1, wherein the semiconductor body is a silicon carbide semiconductor body.
4. The method of claim 1, wherein doping parts of the semiconductor body by plasma doping comprises adjusting a DC-voltage pulse distance in a range of 100 μs to 10 ms.
5. The method of claim 1, wherein doping parts of the semiconductor body by plasma doping comprises adjusting a DC-voltage pulse width in a range of 0.5 μs to 20 μs.
6. The method of claim 1, further comprising filling the trenches with an insulating material.
7. The method of claim 1, further comprising filling the trenches with a semiconductor material.
8. The method of claim 1, further comprising forming a first semiconductor layer on the doped parts of the semiconductor body.
9. The method of claim 8, wherein forming the first semiconductor layer on the doped parts of the semiconductor body comprises forming a silicon layer by lateral epitaxy or low-temperature chemical vapor deposition.
10. The method of claim 8, wherein forming the first semiconductor layer on the doped parts of the semiconductor body comprises:
- forming an amorphous silicon layer on the doped parts of the semiconductor body: and
- crystallizing the amorphous silicon layer by a heat treatment.
11. The method of claim 1, further comprising forming an outdiffusion barrier layer on the sidewalls of the trenches.
12. The method of claim 1, wherein the semiconductor body includes a drift zone of a first conductivity type, and wherein doping parts of the semiconductor body by plasma doping comprises doping the parts of the semiconductor body with dopants of a second conductivity type complementary to the first conductivity type.
13. The method of claim 1, wherein the semiconductor body includes a drift zone of a first conductivity type, and wherein doping parts of the semiconductor body by plasma doping comprises doping the parts of the semiconductor body with dopants of the first conductivity type, the method further comprising:
- forming a first semiconductor layer over the parts of the semiconductor body in the trenches; and
- doping the first semiconductor layer by plasma doping with dopants of a second conductivity type complementary to the first conductivity type.
14. The method of claim 13, further comprising:
- removing the first semiconductor layer from a bottom side of the trenches;
- forming a second semiconductor layer over the first semiconductor layer in the trenches; and
- doping the second semiconductor layer by plasma doping with dopants of the first conductivity type.
15. The method of claim 1, further comprising forming body regions in the semiconductor body at the first side, the body regions overlapping the charge compensation layers.
16. A method of manufacturing a semiconductor device, the method comprising:
- forming trenches in a semiconductor body from a first side:
- doping parts of the semiconductor body via sidewalls of the trenches by introducing dopants by plasma doping; and
- after introducing the dopants by plasma doping, widening a profile of the dopants introduced by plasma doping by diffusion caused by a thermal heating process,
- wherein a surface concentration of the dopants introduced by plasma doping via a unit area of the sidewalls is at least five times larger than a concentration of dopants in a mesa region of the semiconductor body between neighboring trenches which corresponds to N, wherein N is a net doping of the semiconductor body between the neighboring trenches.
17. The method of claim 16, wherein the semiconductor body includes a drift zone of a first conductivity type, and wherein doping parts of the semiconductor body by plasma doping comprises doping the parts of the semiconductor body with dopants of a second conductivity type complementary to the first conductivity type.
18. The method of claim 16, wherein the semiconductor body includes a drift zone of a first conductivity type, and wherein doping parts of the semiconductor body by plasma doping comprises doping the parts of the semiconductor body with dopants of the first conductivity type, the method further comprising:
- forming a first semiconductor layer over the parts of the semiconductor body in the trenches; and
- doping the first semiconductor layer by plasma doping with dopants of a second conductivity type complementary to the first conductivity type.
19. The method of claim 18, further comprising:
- removing the first semiconductor layer from a bottom side of the trenches;
- forming a second semiconductor layer over the first semiconductor layer in the trenches; and
- doping the second semiconductor layer by plasma doping with dopants of the first conductivity type.
20. The method of claim 16, wherein the semiconductor body is a silicon carbide semiconductor body.
Type: Application
Filed: Nov 14, 2016
Publication Date: Mar 2, 2017
Inventors: Peter Irsigler (Obernberg/Inn), Hans-Joachim Schulze (Taufkirchen)
Application Number: 15/350,954