ARRAY SUBSTRATE AND DISPLAY DEVICE AND METHOD FOR MAKING THE ARRAY SUBSTRATE

An array substrate includes a substrate, and a first TFT and a second TFT on the substrate. The second TFT is a low-temperature poly silicon TFT. The first TFT includes a buffer layer, a gate, a gate insulator layer, and a metal oxide semiconductor layer stacked on the substrate in that order. A source electrode and a drain electrode are separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT. The metal oxide semiconductor layer partially covers the source electrode and the drain electrode.

Skip to: Description  ·  Claims  · Patent History  ·  Patent History
Description
FIELD

The subject matter herein generally relates to an array substrate, a display device having the array substrate, and method for making the array substrate, more particularly to an array substrate for an organic light emitting diode (OLED) display device.

BACKGROUND

Two common kinds of display devices are liquid crystal and OLED. The OLED display device usually includes a substrate, a pixel array, and a driving circuit formed on the substrate. The OLED fabrication process is prone to damage from the high temperature fabrication process which results in degradation in display performance and quality. Furthermore, there is room for improvement in display, operation, and luminance of an OLED device.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations of the present technology will now be described, by way of example only, with reference to the attached figures.

FIG. 1 is a cross-sectional view of a first exemplary embodiment of an array substrate.

FIG. 2 illustrates a step for manufacturing the array substrate of FIG. 1 at block 301 of FIG. 7.

FIG. 3 illustrates a step for manufacturing the array substrate of FIG. 1 at block 303 of FIG. 7.

FIG. 4 illustrates a step for manufacturing the array substrate of FIG. 1 at block 305 of FIG. 7.

FIG. 5 illustrates a step for manufacturing the array substrate of FIG. 1 at block 309 of FIG. 7.

FIG. 6 illustrates a step for manufacturing the array substrate of FIG. 1 at block 311 of FIG. 7.

FIG. 7 is a flow chart of a method for making the array substrate of FIG. 1.

FIG. 8 is a cross-sectional view of a second exemplary embodiment of an array substrate.

FIG. 9 is a diagram of an equivalent circuit of a pixel unit in the array substrate of FIG. 8.

FIG. 10 illustrates a step for manufacturing the array substrate of FIG. 8 at block 701 of FIG. 15.

FIG. 11 illustrates a step for manufacturing the array substrate of FIG. 8 at block 703 of FIG. 15.

FIG. 12 illustrates a step for manufacturing the array substrate of FIG. 8 at block 705 of FIG. 15.

FIG. 13 illustrates a step for manufacturing the array substrate of FIG. 8 at block 709 of FIG. 15.

FIG. 14 illustrates a step for manufacturing the array substrate of FIG. 8 at block 711 of FIG. 15.

FIG. 15 is a flow chart of a method for making the array substrate of FIG. 8.

 DETAILED DESCRIPTION

It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure.

Several definitions that apply throughout this disclosure will now be presented.

The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “substantially” is defined to be essentially conforming to the particular dimension, shape, or other feature that the term modifies, such that the component need not be exact. For example, “substantially cylindrical” means that the object resembles a cylinder, but can have one or more deviations from a true cylinder. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like.

FIG. 1 illustrates a first embodiment of an array substrate (array substrate 10) in part and in cross section. In this embodiment, the array substrate 10 is used in a liquid crystal display device. The array substrate 10 comprises at least two kinds of thin film transistors (TFTs), a low-temperature poly silicon TFT and a metal oxide TFT. The low-temperature poly silicon TFT has a high electron mobility and a small volume. The metal oxide TFT has a low leakage current.

The array substrate 10 comprises a substrate 101, a plurality of first TFTs 100, and a plurality of second TFTs 200 on the substrate 101. A planar layer 19 covers the first TFTs 100 and the second TFTs 200. A common electrode 21 is formed on the planar layer 19. A pixel electrode 23 on the planar layer 19 is coupled to the first TFT 100. FIG. 1 shows only one first TFT 100 and one second TFT 200. In this embodiment, each of the first TFTs 100 is a metal oxide TFT, and each of the second TFTs 200 is a low-temperature poly silicon TFT.

Each first TFT 100 is a bottom-gate type TFT and comprises a buffer layer 103, a gate electrode 105, a gate insulator layer 107, a source electrode 109, a drain electrode 111, and a metal oxide semiconductor layer 113. The buffer layer 103, the gate electrode 105, and the gate insulator layer 107 are stacked on the substrate 101 in that order. A portion of the gate insulator layer 107 corresponding to the gate electrode 105 forms a step. The source electrode 109 and the drain electrode 111 are positioned at opposite sides of the step. The metal oxide semiconductor layer 113 is formed on the gate insulator layer 107 and partially covers both the source electrode 109 and the drain electrode 111. The metal oxide semiconductor layer 113 is configured to electrically couple the source electrode 109 and the drain electrode 111. The pixel electrode 23 is electrically coupled to the drain electrode 111. The gate insulator layer 107 comprises a first gate insulator layer 1071 formed on the buffer layer 103 and a second gate insulator layer 1072 formed on the first gate insulator layer 1071. The metal oxide semiconductor layer 113 may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. In this embodiment, the metal oxide semiconductor layer 113 is made of IGZO.

Each second TFT 200 is a top-gate type TFT and comprises a poly-silicon semiconductor layer 201, a buffer layer 203, a gate electrode 205, a gate insulator layer 207, a source electrode 209, and a drain electrode 211. The poly-silicon semiconductor layer 201, the buffer layer 203, the gate electrode 205, and the gate insulator layer 207 are stacked on the substrate 101 in that order. The gate electrode 205 corresponds to the poly-silicon semiconductor layer 201. Both the source electrode 209 and the drain electrode 211 pass through the buffer layer 203 and the gate insulator layer 207, and electrically couple to the poly-silicon semiconductor layer 201. The gate insulator layer 207 comprises a first gate insulator layer 2071 formed on the buffer layer 203 and a second gate insulator layer 2072 formed on the first gate insulator layer 2071.

The buffer layer 103 and the buffer layer 203 are defined within a single layer and are simultaneously formed in a single process. The first gate insulator layer 1071 and the first gate insulator layer 2071 are defined within a single layer and are simultaneously formed in a single process. The second gate insulator layer 1072 and the second gate insulator layer 2072 are defined within a single layer and are simultaneously formed in a single process.

In this embodiment, both the buffer layer 103 and the buffer layer 203 are made of an insulator material, such as silicon oxide or silicon nitride. Both the first gate insulator layer 1071 and the first gate insulator layer 2071 are made of silicon oxide. Both the second gate insulator layer 1072 and the second gate insulator layer 2072 are made of silicon oxide.

FIG. 7 illustrates an example method for making the array substrate 10 shown in FIG. 1. The example method is provided by way of example, as there are a variety of ways to carry out the method. Each block shown in FIG. 7 represents one or more processes, methods, or subroutines, carried out in the exemplary method. The exemplary method can begin at block 301.

At block 301, a poly-silicon semiconductor layer 201 is formed on a substrate 101 as shown in FIG. 2. The process of forming the poly-silicon semiconductor layer 201 on the substrate 101 may comprise depositing an amorphous silicon layer, laser annealing and ion doping the amorphous silicon layer. The substrate 101 can be made of a common material such as glass, quartz, or other material which is flexible.

At block 303, as shown in FIG. 3, a buffer layer 103 and a buffer layer 203 are formed on the substrate 101. A gate 105 is then formed on the buffer layer 103, and a gate 205 is formed on the buffer layer 203. The buffer layer 203 covers the poly-silicon semiconductor layer 201. The buffer layer 103 and the buffer layer 203 are made of an electrical insulator material. The process of forming the gate 105 and the gate 205 may comprise depositing a first metal layer on the buffer layer 103 and the buffer layer 203, and etching and patterning the first metal layer to form the gate 105 and the gate 205. The metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), or neodymium (Nd). The etching process can be a photolithography etching process.

At block 305, as shown in FIG. 4, a gate insulator layer 107 and a gate insulator layer 207 are formed, and a first hole 213 and a second hole 215 passing through the gate insulator layer 207 and the buffer layer 203 are defined to expose the poly-silicon semiconductor layer 201. A portion of the gate insulator layer 107 corresponding to the gate electrode 105 forms a step. The gate insulator layer 107 comprises a first gate insulator layer 1071 formed on the buffer layer 103 and a second gate insulator layer 1072 formed on the first gate insulator layer 1071. The gate insulator layer 207 comprises a first gate insulator layer 2071 formed on the buffer layer 203 and a second gate insulator layer 2072 formed on the first gate insulator layer 2071. The process of forming the gate insulator layer 107 and the gate insulator layer 207 may comprise depositing a first gate insulator layer to form the first gate insulator layer 1071 and 2071, and then depositing a second gate insulator layer on the first gate insulator layer to form the second gate insulator layer 1072 and 2072. Both the first gate insulator layer 1071 and the first gate insulator layer 2071 are made of silicon oxide. Both the second gate insulator layer 1072 and the second gate insulator layer 2072 are made of silicon nitride.

The buffer layer 103, the gate 105, and the gate insulator layer 107 cooperatively define a region of the first TFT 100. The poly-silicon semiconductor layer 201, the buffer layer 203, the gate 205, and the gate insulator layer 207 cooperatively define a region of the second TFT 200.

At block 307, the region of the second TFT 200 is subjected to a hydrogenation treatment. In this embodiment, the temperature of the hydrogenation treatment is higher than 400 degrees Celsius.

At block 309, as shown in FIG. 5, a source electrode 109, a source electrode 209, a drain electrode 111, and a drain electrode 211 are formed. The process of forming the source electrode 109, the source electrode 209, the drain electrode 111, and the drain electrode 211 may comprise depositing a second metal layer and etching and patterning the second metal layer to form the source electrode 109, the source electrode 209, the drain electrode 111, and the drain electrode 211. The source electrode 209 is formed in the first hole 213 and coupled to the poly-silicon semiconductor layer 201, and the drain electrode 211 is formed in the second through hole 215 and coupled to the poly-silicon semiconductor layer 201. The source electrode 109 and the drain electrode 111 are positioned at a same layer and are positioned at opposite sides of the step.

At block 311, as shown in FIG. 5, a metal oxide semiconductor layer 113 is formed. The process of forming the metal oxide semiconductor layer 113 may comprise depositing a metal oxide layer, and patterning the metal oxide layer to form the metal oxide semiconductor layer 113. The metal oxide semiconductor layer 113 is formed on the second gate insulator layer 1072 and corresponds to the gate 105. The metal oxide semiconductor layer 113 partially covers the source electrode 109 and the drain electrode 111. The metal oxide semiconductor layer 413 can be made of IGZO, zinc oxide, indium oxide, or gallium oxide.

At block 313, as shown in FIG. 1, a planar layer 19 is formed to cover the first TFT 100 and a second TFT 200. The method further comprises forming a common electrode layer 21 on the planar layer 19, and forming a pixel electrode layer 23, electrically coupled to the drain electrode 111 of the first TFT 100, on the planar layer 19.

The array substrate 10 includes the first TFTs 100 and the second TFTs 200. In this embodiment, each first TFT 100 is a metal oxide TFT, and each second TFT 200 is a low-temperature poly silicon TFT. The first TFT 100 is a metal oxide TFT, which has a low leakage current and can reduce power consumption. The second TFT 200 is a low-temperature poly silicon TFT, which has a high electron mobility and can effectively improve a reaction rate of the driving circuit. The low-temperature poly silicon TFT has a small volume and is of benefit for narrowing the non-display region. For each first TFT 100, the metal oxide semiconductor layer 113 is formed after the forming of the source electrode 109 and the drain electrode 111, which protects the metal oxide semiconductor layer 113 from damage during the forming process of the source electrode 109 and the drain electrode 111.

FIG. 8 illustrates a second embodiment of the array substrate 40 in part and in cross section. In this embodiment, the array substrate 40 is used in an organic light emitting diode display device. The array substrate 40 comprises at least two kinds of thin film transistors (TFTs), a low-temperature poly silicon TFT and a metal oxide TFT. The low-temperature poly silicon TFT has a high electron mobility and a small volume. The metal oxide TFT has a low leakage current.

The array substrate 40 comprises a plurality of pixel units 420 arranged in rows and columns. FIG. 9 illustrates one of the pixel units 420. Each pixel unit 420 comprises a light emitting diode 421, a switch TFT 400, a driving TFT 500, and a capacitor C. The switch TFT 400 is electrically connected between a gate line and a data line to switch the driving TFT 500 on or off. The driving TFT 500 is electrically connected between a power source VDD and the light emitting diode 421. The capacitor C is a storage capacitor and is electrically connected between a gate electrode of the driving TFT 500 and a drain electrode of the driving TFT 500. The capacitor C is configured to control electrical current of the driving TFT 500, thus the driving TFT 500 can control a luminance of the light emitting diode 421.

The array substrate 40 comprises a substrate 401, and a plurality of switch TFTs 400, a plurality of driving TFTs 500, and a plurality of poly silicon TFTs 600 formed on the substrate 401. The array substrate 40 further comprises a planar layer 49 covering the switch TFTs 400, the driving TFTs 500, and the poly silicon TFTs 600, a light-emitting material layer 51, a plurality of cathodes 53, a dielectric layer 55, and a plurality of anodes 57 each electrically coupled to one of the drain electrodes 511 of the driving TFTs 500. FIG. 8 shows only one switch TFT 400, one driving TFT 500, and one poly silicon TFT 600. In this embodiment, each switch TFT 400 and each driving TFT 500 are metal oxide TFTs, each poly silicon TFT 600 is a low-temperature poly silicon TFT.

Each driving TFT 500 is a bottom-gate type TFT and comprises a buffer layer 503, a gate electrode 505, a gate insulator layer 507, a source electrode 509, a drain electrode 111, and a metal oxide semiconductor layer 513. The buffer layer 503, the gate electrode 505, and the gate insulator layer 507 are stacked on the substrate 401 in that order. A portion of the gate insulator layer 507 corresponding to the gate electrode 505 forms a step. The source electrode 509 and the drain electrode 511 are positioned at opposite sides of the step. The metal oxide semiconductor layer 513 is formed on the gate insulator layer 507 and partially covers the source electrode 509 and the drain electrode 511. The metal oxide semiconductor layer 513 is configured to electrically couple the source electrode 509 and the drain electrode 511. The drain electrode 511 is electrically coupled to the anode 57. The gate insulator layer 507 comprises a first gate insulator layer 5071 formed on the buffer layer 503 and a second gate insulator layer 5072 formed on the first gate insulator layer 5071. The metal oxide semiconductor layer 513 may be made of indium gallium zinc oxide (IGZO), zinc oxide, indium oxide, or gallium oxide. In this embodiment, the metal oxide semiconductor layer 513 is made of IGZO.

Each switch TFT 400 is substantially the same as the driving TFT 500, except that the switch TFT 400 is not coupled to an anode.

Each poly silicon TFT 600 is a top-gate type TFT and comprises a poly-silicon semiconductor layer 601, a buffer layer 603, a gate electrode 605, a gate insulator layer 607, a source electrode 609, and a drain electrode 611. The poly-silicon semiconductor layer 601, the buffer layer 603, the gate electrode 605, and the gate insulator layer 607 are stacked on the substrate 401 in that order. The gate electrode 605 corresponds to the poly-silicon semiconductor layer 601. Both the source electrode 609 and the drain electrode 611 pass through the buffer layer 603 and the gate insulator layer 607 and electrically couple to the poly-silicon semiconductor layer 601. The gate insulator layer 607 comprises a first gate insulator layer 6071 formed on the buffer layer 603 and a second gate insulator layer 6072 formed on the first gate insulator layer 6071. The first gate insulator layer 5071 of each driving TFT 500 and the first gate insulator layer 6071 of each poly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process. The second gate insulator layer 5072 of each driving TFT 500 and the second gate insulator layer 6072 of each poly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process. The buffer layer 503 of each driving TFT 500 and the buffer 603 of each poly silicon TFT 600 are defined within a single layer and are simultaneously formed by a single process.

In this embodiment, both the first gate insulator layer 5071 and the first gate insulator layer 6071 are made of silicon oxide. Both the second gate insulator layer 5072 and the second gate insulator layer 6072 are made of silicon nitride.

FIG. 15 illustrates an example method for making the array substrate 40 shown in FIG. 8. The example method is provided by way of example, as there are a variety of ways to carry out the method. Each block shown in FIG. 15 represents one or more processes, methods or subroutines, carried out in the exemplary method. The method only describes the making of the driving TFT 500 and the poly silicon TFT 600, the making of the switch TFT 400 is not described. As the switch TFT 400 is substantially the same as the driving TFT 500, the method for making TFT 400 on the array substrate 40 resembles the method for making the driving TFT 500. The exemplary method can begin at block 701.

At block 701, a poly-silicon semiconductor layer 601 is formed on a substrate 401 as shown in FIG. 2. The process of forming the poly-silicon semiconductor layer 601 on the substrate 401 may comprise depositing an amorphous silicon layer, and laser annealing and ion doping the amorphous silicon layer. The substrate 401 can be made of a common material such as glass or quartz, or other material which is flexible.

At block 703, as shown in FIG. 11, a buffer layer 503, and a buffer layer 603 are formed on the substrate 401. A gate 505 is then formed on the buffer layer 503 and a gate 605 is formed on the buffer layer 603. The buffer layer 603 covers the poly-silicon semiconductor layer 601. The buffer layer 503 and the buffer layer 603 are made of an insulator material. The process of forming the gate 505 and the gate 605 may comprise depositing a first metal layer on the buffer layer 503 and the buffer layer 603 and etching and patterning the first metal layer to form the gate 505 and the gate 605. The metal layer can be made of an electrically conductive metal, such as molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), neodymium (Nd). The etching method can be a photolithography etching method.

At block 705, as shown in FIG. 12, a gate insulator layer 507 and a gate insulator layer 607 are formed, and a first hole 613 and a second hole 615 passing through the gate insulator layer 607 and the buffer layer 603 are defined to expose the poly-silicon semiconductor layer 601. A portion of the gate insulator layer 607 corresponding to the gate electrode 605 forms a step. The gate insulator layer 507 comprises a first gate insulator layer 5071 formed on the buffer layer 503 and a second gate insulator layer 5072 formed on the first gate insulator layer 5071. The gate insulator layer 607 comprises a first gate insulator layer 6071 formed on the buffer layer 603 and a second gate insulator layer 6072 formed on the first gate insulator layer 6071. The process of forming the gate insulator layer 507 and the gate insulator layer 607 may comprise depositing a first gate insulator layer to form the first gate insulator layer 5071 and 6071, and then depositing a second gate insulator layer on the first gate insulator layer to form the second gate insulator layer 5072 and 6072. Both the first gate insulator layer 5071 and the first gate insulator layer 6071 are made of silicon oxide. Both the second gate insulator layer 5072 and the second gate insulator layer 6072 are made of silicon nitride.

The buffer layer 503, the gate 505, and the gate insulator layer 507 cooperatively define a region of the driving TFT 500. The poly-silicon semiconductor layer 601, the buffer layer 603, the gate 605, and the gate insulator layer 607 cooperatively define a region of the poly silicon TFT 600.

At block 707, the region of the poly silicon TFT 600 is subjected to a hydrogenation treatment. In this embodiment, the temperature of the hydrogenation treatment is higher than 400 degrees Celsius.

At block 709, as shown in FIG. 13, a source electrode 509, a source electrode 609, a drain electrode 511, and a drain electrode 611 are formed. The process of forming the source electrode 509, the source electrode 609, the drain electrode 511, and the drain electrode 611 may comprise depositing a second metal layer and etching and patterning the second metal layer to form the source electrode 509, the source electrode 609, the drain electrode 511, and the drain electrode 611. The source electrode 609 is formed in the first hole 613 and coupled to the poly-silicon semiconductor layer 601 and the drain electrode 611 is formed in the second through hole 615 and coupled to the poly-silicon semiconductor layer 601. The source electrode 509 and the drain electrode 511 are positioned at opposite sides of the step.

At block 711, as shown in FIG. 14, a metal oxide semiconductor layer 513 is formed. The process of forming the metal oxide semiconductor layer 513 may comprise depositing a metal oxide layer and patterning the metal oxide layer to form the metal oxide semiconductor layer 513. The metal oxide semiconductor layer 513 is formed on the second gate insulator layer 5072 and corresponds to the gate 505. The metal oxide semiconductor layer 513 partially covers the source electrode 509 and the drain electrode 511. The metal oxide semiconductor layer 513 can be made of IGZO, zinc oxide, indium oxide, or gallium oxide.

At block 713, as shown in FIG. 8, a planar layer 49 is formed to cover the switch TFT 400, the driving TFT 500, and the poly silicon TFT 600. The method further comprises forming an anode 57 on the planar layer 49 which is electrically coupled to the drain electrode 511 of the driving TFT 500, and forming a cathode 53, a dielectric layer 55, and light-emitting material 51 on the planar layer 49.

The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of an image device. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.

Claims

1. An array substrate comprising:

a substrate;
a first TFT on the substrate, the first TFT being a metal oxide TFT; and
a second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;
wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT; the metal oxide semiconductor layer partially covers the source electrode and the drain electrode of the first TFT.

2. The array substrate of claim 1, wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed; the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.

3. The array substrate of claim 2, wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the buffer layer of the first TFT and a second gate insulator layer formed on the first gate insulator layer of the first TFT; and the gate insulator layers of the second TFT comprises a first gate insulator layer formed on the buffer layer of the second TFT and a second gate insulator layer formed on the first gate insulator layer of the second TFT.

4. The array substrate of claim 3, wherein the first gate insulator layers of the first TFT and the second TFT are made of silicon oxide; and the second gate insulator layers of the first TFT and the second TFT are made of silicon nitride.

5. The array substrate of claim 1, further comprising a planar layer covering the first TFT and the second TFT, a common electrode on the planar layer, and a pixel electrode electrically coupled to the first TFT.

6. An array substrate comprising:

a substrate;
a switch TFT on the substrate, the switch TFT being a metal oxide TFT;
a driving TFT on the substrate, the driving TFT being a metal oxide TFT; and
a poly silicon TFT on the substrate, the poly silicon TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT,
wherein the switch TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the switch TFT; the metal oxide semiconductor layer of the switch TFT covers the source electrode and the drain electrode of the switch TFT; and
wherein the driving TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the driving TFT; the metal oxide semiconductor layer of the driving TFT covers the source electrode and the drain electrode of the driving TFT.

7. The array substrate of claim 6, wherein the buffer layers of the poly silicon TFT, the switch TFT, and the driving TFT are defined by a single layer and are simultaneously formed; and

the gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are defined by a single layer and are simultaneously formed.

8. The array substrate of claim 6, wherein the gate insulator layer of the poly silicon TFT comprises a first gate insulator layer formed on the buffer layer of the poly silicon TFT and a second gate insulator layer formed on the first gate insulator layer; the gate insulator layer of the switch TFT comprises a first gate insulator layer formed on the buffer layer of the switch TFT and a second gate insulator layer formed on the first gate insulator layer; and the gate insulator layer of the driving TFT comprises a first gate insulator layer formed on the buffer layer of the driving TFT and a second gate insulator layer formed on the first gate insulator layer.

9. The array substrate of claim 8, wherein the first gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are made of the silicon oxide; and the second gate insulator layers of the poly silicon TFT, the switch TFT, and the driving TFT are made of silicon nitride.

10. The array substrate of claim 6, wherein the array substrate further comprises a planar layer covering the switch TFT, the driving TFT, and the poly silicon TFT, a lighting emitting material layer on the planar layer, a cathode on the planar layer, a dielectric layer on the planar layer, and an anode on the planar layer and electrically coupled to the driving TFT.

11. A display device comprising:

an array substrate comprising:
a substrate;
a first TFT on the substrate, the first TFT being a metal oxide TFT; and
a second TFT on the substrate, the second TFT being a low-temperature poly silicon TFT, the second TFT comprising a poly-silicon semiconductor layer, a buffer layer, a gate, and a gate insulator layer stacked on the substrate in that order, and a source electrode and a drain electrode passing through both the buffer layer and the gate insulator layer and coupled to the metal oxide semiconductor layer of the second TFT;
wherein the first TFT comprises a buffer layer, a gate, a gate insulator layer and a metal oxide semiconductor layer stacked on the substrate in that order, and a source electrode and a drain electrode separately positioned on the gate insulator layer and coupled to the metal oxide semiconductor layer of the first TFT; the metal oxide semiconductor layer partially covers the source electrode and the drain electrode.

12. The display device of claim 11, wherein the buffer layer of the first TFT and the buffer layer of the second TFT are defined by a single layer and are simultaneously formed; the gate insulator layer of the first TFT and the gate insulator layer of the second TFT are defined by a single layer and are simultaneously formed.

13. The display device of claim 12, wherein the gate insulator layer of the first TFT comprises a first gate insulator layer formed on the buffer layer of the first TFT and a second gate insulator layer formed on the first gate insulator layer of the first TFT; and the gate insulator layers of the second TFT comprises a first gate insulator layer formed on the buffer layer of the second TFT and a second gate insulator layer formed on the first gate insulator layer of the second TFT.

14. The display device of claim 13, wherein the first gate insulator layers of the first TFT and the second TFT are made of the silicon oxide; and the second gate insulator layers of the first TFT and the second TFT are made of silicon nitride.

15. The display device of claim 11, wherein the array substrate further comprises a planar layer covering the first TFT and the second TFT, a common electrode on the planar layer, and a pixel electrode electrically coupled to the first TFT.

16. A method for making an array substrate comprising:

forming a poly-silicon semiconductor layer on a substrate;
forming a buffer layer on the poly-silicon semiconductor layer and the substrate;
depositing a first metal layer and patterning the first metal layer to form a first gate electrode and a second gate electrode, the first gate electrode corresponding to the poly-silicon semiconductor layer;
forming a gate insulator layer covering the first gate electrode and the second gate electrode;
defining a first hole and a second hole passing through the buffer layer and the gate insulator layer to expose the poly-silicon semiconductor layer;
depositing a second metal layer on the gate insulator layer and patterning the second metal layer to form a first source electrode in the first hole and a first drain electrode in the second through hole, a second source electrode and a second drain electrode on the gate insulator layer; and
depositing a metal oxide layer on the gate insulator layer and patterning the metal oxide layer to form a metal oxide semiconductor layer coupled to the second source electrode and the second drain electrode.

17. The method of claim 16, wherein the method further comprises forming a planar layer to cover the gate insulator layer, the metal oxide semiconductor layer, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

18. The method of claim 17, wherein the method further comprises forming an anode on the planar layer which is electrically coupled to the second drain electrode, forming a dielectric layer on the planar layer, forming an emitting material on the planar layer, and forming a cathode on the planar layer.

19. The method of claim 17, wherein the method further comprises forming a common electrode layer on the planar layer, and forming a pixel electrode layer on the planar layer which is electrically coupled to the second drain electrode.

Patent History
Publication number: 20170084641
Type: Application
Filed: Jun 30, 2016
Publication Date: Mar 23, 2017
Inventors: HSIN-HUA LIN (New Taipei), YI-CHUN KAO (New Taipei)
Application Number: 15/198,116
Classifications
International Classification: H01L 27/12 (20060101);