Method of Reducing the Heights of Source-Drain Sidewall Spacers of FinFETs Through Etching
A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.
This application is continuation of U.S. patent application Ser. No. 14/961,048, entitled “Method of Reducing Heights of Source-Drain Sidewall Spacers of FinFETs Through Etching,” filed Dec. 7, 2015 which application is a divisional of U.S. patent application Ser. No. 14/090,763, entitled “A Method of Reducing Heights of Source-Drain Sidewall Spacers of FinFETs Through Etching,” filed Nov. 26, 2013, now U.S. Pat. No. 9,209,302 issued Dec. 8, 2015 which application claims the benefit of the following provisionally filed U.S. Patent application: Application Ser. No. 61/780,647, filed Mar. 13, 2013, and entitled “Novel FinFET Structure with Improved High Current Sustainability,” which application is hereby incorporated herein by reference.
BACKGROUNDTransistors are key components of modern integrated circuits. To meet the requirement of increasingly faster speed, the drive currents of transistors need to be increasingly greater. Since the drive currents of transistors are proportional to the gate widths of the transistors, transistors with greater widths are preferred.
The increase in the gate widths of the transistors, however, conflicts with the requirements of reducing the sizes of semiconductor devices. Fin field-effect transistors (FinFET) were thus developed. By forming fins that act as the channel region of the FinFET, the drive currents of the transistors are increased without the cost of occupying more chip area.
The FinFETs, however, also suffer from drawbacks. With the increasing down-scaling of FinFETs, the increasingly smaller sizes of the fins result in the increase of the resistances in the source/drain regions, and hence the degradation of device drive currents. The contact resistances between the contact plugs and source/drain silicide regions of the FinFETs are also increased due to small fin areas. Additionally, it is difficult to form contact plugs connected to source/drain silicide regions of the FinFETs. This is because the fins of the FinFETs have small areas, the landing areas for the corresponding contact plugs are thus small. The process window for landing contact plugs accurately on fins is also small, which means that there is little room for the process variations to occur without affecting the reliability of the resulting FinFETs.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative, and do not limit the scope of the disclosure.
A Fin Field-Effect Transistor (FinFET) and the method of forming the same are provided. The intermediate stages of manufacturing the FinFET are provided. The variations of the FinFET and the respective formation method are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Referring to
Referring to
In alternative embodiments, before the recessing of STI regions, 22, portion 21 of semiconductor substrate 20 (
Referring to
In some embodiments, gate electrode layer 36 is formed of polysilicon. In other embodiments, gate electrode layer 36 includes a material selected from metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN) and molybdenum nitride (MoNx)), metal carbides (such as tantalum carbide (TaC) and hafnium carbide (HfC)), metal-nitride-carbides (such as TaCN), metal oxides (such as molybdenum oxide (MoO x)), metal oxynitrides (such as molybdenum oxynitride (MoOxNy), metal silicides (such as nickel silicide), and combinations thereof. Gate electrode layer 36 can also be a metal layer capped with a polysilicon layer.
Mask layer 38 may further be formed on top of gate electrode layer 36 in accordance with some embodiments. Mask layer 38 may include silicon nitride. Alternatively, other materials that are different from the subsequently formed fin spacers may be used.
Gate stack 30 is then patterned to form gate dielectric 40, gate electrode 42, and mask 44.
Next, as is illustrated in
Next, spacer layer 48 is patterned, forming gate spacers 54 and fin spacers 56, as shown in
In some processes, after the horizontal portions of spacer layer 48 are removed, the patterning of spacer layer 48 is concluded. As a result, the top edge of semiconductor fin 24 is level with the top end of the resulting fin spacers 56. Alternatively stated, in the respective FinFETs, height Hc1 of semiconductor fin 24 is equal to height Hc2 of fin spacers 56. In some embodiments of the present disclosure, after the structure as shown in
In the embodiments wherein spacer layer 48 (
Since gate spacer layer 48 (
Gate spacers 54 and fin spacers 56 are formed by patterning the same gate spacer layer 48 (
After the formation of gate spacers 54, an implantation step may be performed to implant the exposed end portions 242 of semiconductor fin 24 to form source and drain regions 64. Depending on the desirable type of the resulting FinFET, a p-type impurity is implanted to form a p-type FinFET, or an n-type impurity is implanted to form an n-type FinFET.
As shown in
In accordance with some embodiments, an integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. A gate stack is overlying a middle portion of the semiconductor fin. A fin spacer is on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height, wherein the first height is greater than about two times the second height.
In accordance with other embodiments, an integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a FinFET. The FinFET includes a semiconductor fin over the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. The FinFET further includes a gate stack over a middle portion of the semiconductor fin, a source/drain region at an end of the semiconductor fin, and a fin spacer on a sidewall of the source/drain region. The fin spacer has a second height, wherein the first height is greater than about two times the second height. The FinFET further includes a source/drain silicide layer having a sidewall portion on a sidewall of the source/drain region, wherein a bottom end of the source/drain silicide layer contacts a top end of the first fin spacer.
In accordance with yet other embodiments, a method includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer to form a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is etched. When the step of etching the fin spacer is finished, a first height of the fin spacer is smaller than about a half of a second height of the semiconductor fin.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims
1. A method comprising:
- forming a gate stack covering a first portion of a semiconductor fin;
- forming a spacer layer over the gate stack and the semiconductor fin;
- patterning the spacer layer to form: a gate spacer on a sidewall of the gate stack; and a fin spacer on a sidewall of a second portion of the semiconductor fin;
- etching the fin spacer until a first height of the fin spacer is smaller than about a half of a second height of the semiconductor fin; and
- forming a silicide region contacting a top part of the second portion of the semiconductor fin, with the silicide region overlapping and contacting a top end of the fin spacer.
2. The method of claim 1, wherein the forming the spacer layer comprises:
- depositing a first dielectric layer formed of a first dielectric material; and
- depositing a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is formed of a second dielectric material different from the first dielectric material.
3. The method of claim 2, wherein the etching the fin spacer is continued until the second dielectric layer is fully removed from the fin spacer.
4. The method of claim 2, wherein when the etching the fin spacer is finished, each of the gate spacer and the fin spacer comprises a remaining portion of the first dielectric material and a remaining portion of the second dielectric material.
5. The method of claim 2, wherein the first dielectric material is silicon oxide, and the second dielectric material is silicon nitride.
6. The method of claim 1, wherein when the etching the fin spacer is finished, a ratio of a height of the semiconductor fin to a height of the fin spacer is between about 2 and about 10.
7. The method of claim 1 further comprising forming a contact plug to contact the silicide region.
8. The method of claim 7, wherein the fin spacer comprises a slanted sidewall having a top end in contact with a bottom end of the silicide region, and a bottom end connected to an isolation region.
9. A method comprising:
- forming a gate stack on a first portion of a semiconductor fin;
- forming a spacer layer over the gate stack and the semiconductor fin;
- performing a first etching to remove horizontal portions of the spacer layer, wherein remaining portions of the spacer layer comprise: a gate spacer on a sidewall of the gate stack; and a fin spacer on a sidewall of a second portion of the semiconductor fin; and
- performing a second etching to thin the gate spacer and the fin spacer, wherein the second etching is performed using different process conditions than the first etching, and after the second etching, a portion of the fin spacer remains.
10. The method of claim 9, wherein the spacer layer comprises a first sub layer and a second sub layer over the first sub layer, with the first sub layer and the second sub layer formed of different materials, and wherein after the second etching, the second sub layer is fully removed from the fin spacer, and the second sub layer has a portion remaining in the gate spacer.
11. The method of claim 10, wherein the first sub layer comprises silicon oxide, and the second sub layer comprises silicon nitride.
12. The method of claim 10, wherein after the second etching, both the first sub layer and the second sub layer remain in each of the gate spacer and the fin spacer.
13. The method of claim 10, wherein each of the first etching and the second etching comprises:
- etching the second sub layer using a first etching gas; and
- etching the first sub layer using a second etching gas different from the first etching gas.
14. The method of claim 9, wherein when the second etching is finished, a ratio of a height of the semiconductor fin to a height of the fin spacer is between about 2 and about 10.
15. The method of claim 9 further comprising:
- implanting the second portion of the semiconductor fin to form a source/drain region;
- after the second etching, siliciding exposed surfaces of the source/drain region to form a silicide layer; and
- forming a contact plug to contact the silicide layer.
16. A method comprising:
- recessing shallow trench isolation regions, with a semiconductor region between the recessed shallow trench isolation regions forming a semiconductor fin;
- forming a gate stack on a first portion of the semiconductor fin, and leaving a second portion of the semiconductor fin un-covered by the gate stack;
- forming a gate spacer having a sidewall contacting a sidewall of the gate stack;
- forming a fin spacer having a sidewall contacting a sidewall of the second portion of the semiconductor fin, wherein each of the gate spacer and the fin spacer comprises a portion of a first dielectric layer and a portion of a second dielectric layer, with the second dielectric layer being over, and formed of a different dielectric material than, the first dielectric layer; and
- performing a first etching step to remove an entirety of the portion of the second dielectric layer in the fin spacer, wherein the portion of the second dielectric layer in the fin spacer remains after the first etching step.
17. The method of claim 16, wherein the forming the gate spacer and the forming the fin spacer comprise:
- a second etching step to pattern the second dielectric layer; and
- a third etching step to pattern the first dielectric layer, wherein the second etching step and the third etching step are performed before the first etching step.
18. The method of claim 17 further comprising:
- after the first etching step, performing a fourth etching step to thin portions of the first dielectric layer in both the gate spacer and the fin spacer.
19. The method of claim 18, wherein a top portion of the second portion of the semiconductor fin is exposed as a result of the first etching step and the fourth etching step, and the method further comprises siliciding a surface of the top portion of the second portion of the semiconductor fin.
20. The method of claim 16, wherein the first dielectric layer is formed of silicon oxide, and the second dielectric layer is formed of silicon nitride.
Type: Application
Filed: Jan 4, 2017
Publication Date: Apr 27, 2017
Patent Grant number: 9887275
Inventors: Jam-Wem Lee (Hsin-Chu), Tsung-Che Tsai (Hsin-Chu), Yi-Feng Chang (Xinbei City)
Application Number: 15/398,576