ADAPTIVE GAIN CONTROL USING SAMPLE-AND-HOLD CIRCUIT FOR ANALOG CDS
An image processing circuit includes a first sample-and-hold circuit that samples a first data from a pixel, a second sample-and-hold circuit that samples a second data from the pixel, a voltage-to-current circuit that includes a resistor and a current source and receives the first and second data to output a difference data, an adaptive gain control determination circuit that determines whether a rate of change of a signal from the pixel exceeds a threshold based on an output of the second sample-and-hold circuit, and a current-mode ADC that converts the difference data from an analog form to a digital form.
1. Field of the Invention
This application relates generally to image sensor readout chains, which includes sample-and-hold circuits. More specifically, this application relates to an image sensor readout circuit that implements analog gain to improve noise performance and maintain dynamic range.
2. Description of Related Art
Image sensing devices typically consist of an image sensor, generally an array of pixel circuits, as well as signal processing circuitry and any associated control or timing circuitry. Within the image sensor itself, charge is collected in a photoelectric conversion device of the pixel circuit as a result of the impingement of light.
One example of a pixel circuit is illustrated in
While
The voltage at signal line 106 is measured at two different times under the control of timing circuits and switches, which results in a reset signal (“P-phase value”) and light-exposed or data signal (“D-phase value”) of the pixel. This process is referred to as a correlated double sampling (CDS) method. The reset signal is then subtracted from the data signal to produce a value which is representative of an accumulated charge in the pixel, and thus the amount of light shining on the pixel. The accumulated charge is then converted to a digital value. Such a conversion typically requires several circuit components such as sample-and-hold (S/H) circuits, analog-to-digital converters (ADC), and timing and control circuits, with each circuit component serving a purpose in the conversion. For example, the purpose of the S/H circuit may be to sample the analog signals from different time phases of the photo diode operation, after which the analog signals may be converted to digital form by the ADC. A single-slope ADC is illustrated in
As illustrated by
In many practical pixel readout circuits, there is a tradeoff between ADC noise floor and ADC maximum input level. In order to best sense the pixels with low illumination, the readout chain is preferably set to provide high signal gain with lowest input referred noise. At strong illumination, on the other hand, the readout chain is preferably set to provide low signal gain in order not to have saturation. In other words, the preferred settings for low illumination pixels and high illumination pixels are different.
In summary, common attempts to improve noise performance may reduce the dynamic range of the image sensor. Thus, there exists a need for a pixel readout chain that improves the signal-to-noise ratio (SNR) without degrading the dynamic range of the image sensor.
BRIEF SUMMARY OF THE INVENTIONVarious aspects of the present disclosure relate to a sample-and-hold circuit and/or a black sun detection circuit for improving the operation of a sample-and-hold circuit.
In one aspect of the present disclosure, an image processing circuit comprises a first sample-and-hold circuit configured to sample a first data from a pixel; a second sample-and-hold circuit configured to sample a second data from the pixel; a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a difference data; an adaptive gain control determination circuit configured to determine whether a rate of change of a signal from the pixel exceeds a first predetermined threshold based on an output of the second sample-and-hold circuit; and a current-mode analog-to-digital converter configured to convert the difference data from an analog form to a digital form.
In another aspect of the present disclosure, a method of processing an image comprises sampling a first data from a pixel by a first sample-and-hold circuit; sampling a second data from the pixel by a second sample-and-hold circuit; receiving the first data and the second data by a voltage-to-current circuit including a resistor and a current source; outputting a difference data by the voltage-to-current circuit; determining whether a rate of change of a signal from the pixel exceeds a predetermined threshold by an adaptive gain control determination circuit based on an output of the second sample-and-hold circuit; and converting the difference data from an analog form to a digital form by a current-mode analog-to-digital converter.
In yet another aspect of the present disclosure, an imaging device comprises: a pixel including a photoelectric conversion device configured to convert an incident light into an analog signal; and an image processing circuit, including: a first sample-and-hold circuit configured to sample a first data from the pixel, a second sample-and-hold circuit configured to sample a second data from the pixel, a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a difference data, an adaptive gain control determination circuit configured to determine whether a rate of change of the analog signal from the pixel exceeds a predetermined threshold based on an output of the second sample-and-hold circuit, and a current-mode analog-to-digital converter configured to convert the difference data from an analog form to a digital form.
This disclosure can be embodied in various forms, including hardware or circuits controlled by computer-implemented methods, computer program products, computer systems and networks, user interfaces, and application programming interfaces; as well as hardware-implemented methods, signal processing circuits, image sensor circuits, application specific integrated circuits, field programmable gate arrays, and the like. The foregoing summary is intended solely to give a general idea of various aspects of the present disclosure, and does not limit the scope of the disclosure in any way.
These and other more detailed and specific features of various embodiments are more fully disclosed in the following description, reference being had to the accompanying drawings, in which:
In the following description, numerous details are set forth, such as flowcharts, data tables, and system configurations. It will be readily apparent to one skilled in the art that these specific details are merely exemplary and not intended to limit the scope of this application.
In this manner, the present disclosure provides for improvements in the technical field of signal processing, as well as in the related technical fields of image sensing and image processing.
[Analog Gain]
The dynamic range R of an image sensor circuit is determined by the maximum possible voltage swing of the signals in the circuit, divided by the noise of a dark pixel. Because the voltage swing of a particular circuit design is fixed, the dynamic range is also fixed.
[Adaptive Gain Control]
To maintain this dynamic range, it is preferable to utilize two different analog gains in the sensor circuit, and to control the gain selection adaptively (“Adaptive Gain Control” or AGC). Specifically, it is preferable to use a first analog gain of 1 (“low”) and a second analog gain of G (“high”), where G>1.
Thus, it is guaranteed that the maximum swing of the output (that is, after the analog gain stage) will always stay within the usable dynamic range R of the circuit. Concurrently, average noise performance of the image sensor is improved because the signals with a level lower than R/G are amplified by the analog gain and thus exhibit an improved SNR. While
Using the analog circuit logic illustrated in
To detect whether the difference signal DIFF exceeds the threshold, a switched capacitor comparator may be used.
[Dual S/H Implementation]
To achieve sufficiently high throughput while performing CDS, the above S/H circuits may be combined in a dual S/H configuration.
To accomplish this, switches 901 and 902 are controlled at an appropriate timing so that S/H circuits 911 and 912 successively sample the input signal at the proper time so that Vdata and Vreset appear at the top and bottom S/H circuits, respectively. ADC 920 converts the two voltages into digital values. Additionally, a subtraction is performed so that the appropriate output signal is obtained. This subtraction may be performed in the analog domain before analog-to-digital conversion, or may be performed in the digital domain after each signal has been individually converted to digital form.
To sample the reset signal, switches 1002 and 1007 are closed, and switches 1006 and 1008 are opened. This causes capacitor 1022 to be charged to the voltage Vreset−Vref. After capacitor 822 has been charged up, switches 1002 and 1007 open (disconnect) to complete the sampling. To sample the data signal, a similar operation is performed. That is, switches 1001 and 1004 are closed, and switches 1003 and 1005 are opened. This causes capacitor 1021 to be charged to the voltage Vdata−Vref. After capacitor 1021 has been charged up, the switches 1001 and 1004 are opened.
In order to convert the difference between the reset to the data signal into current, switches 1003, 1005, 1006, and 1008 turn on. As a result the sampled reset voltage will appear on the right side of the resistor and the sampled data voltage will be on the left side of resistor 1050.
Because the voltages appearing on the left and right sides of resistor 1050 are Vdata and Vreset, respectively, the current that flows through resistor 1050 is Iin=(Vreset−Vdata)/R1. This current flows to the input of current-mode ADC 1060 and is converted to a digital value. In this configuration, any type of current-mode ADC may be used; for example, a sigma-delta ADC may be used to convert the difference signal into a digital value with a high accuracy.
As can be seen from
In dual S/H circuit 1000, ADC 1060 receives as an input the current Iin=(Vreset−Vdata)/R1. This indicates that the CDS subtraction step (that is, subtracting the reset value from the light exposed signal value) is automatically done in the analog domain via the circuit arrangement. This occurs without any additional circuitry required. Another benefit to the configuration of dual S/H circuit 1000 is that ADC 1060 receives a scaled version of the signal difference with a scaling factor of 1/R1. This is equivalent to an analog gain in the circuit. Thus, R1 may be controlled (for example, by using a variable resistor, several resistors that may be selected among, and the like) to achieve various analog gains, such as gain 1 and gain G as described above. Thus, dual S/H circuit 1000 has both CDS subtraction and analog gain capabilities built in. The output of ADC 1020 is a digital value corresponding to (Vreset−Vdata)/R1, and may include additional gain in the digital domain if desired.
To achieve AGC detection, the trip point of amplifier 1011 may be shifted as described above. Thus, a signal present at intermediate output node 1070 may be fed to a AGC circuit, such as the AGC flip flop described above with regard to
In
The two S/H transistor circuits 1120 are connected to V2I circuit 1130, which comprises a current source having current I1 and the resistor having resistance R1 as described above. The resistor is connected across the two S/H outputs, and as a result the current in the resistor (IR) is given by the difference between the sampled reset signal and the sampled data signal, divided by R1. That is, IR=(Vreset−Vdata)/R1.
As illustrated in
Current IR is fed via another source-follower PMOS transistor to ADC 1140, which is preferably a current mode sigma-delta ADC. Thus, ADC 1140 sees an input current (Vreset−Vdata)/R1. As described above with regard to
ADC 1140 is not restricted to a current mode sigma-delta ADC, but may be any type of analog-to-digital converter. For example, ADC 1140 may be a single slope ADC, a flash ADC, a sigma-delta ADC, a successive approximation ADC, and the like. It is preferable to use a sigma-delta ADC for ADC 1140, because a sigma-delta ADC operates using oversampling where each conversion is the result of many high speed samples. The output from a sigma-delta ADC may be passed through a decimation filter to generate the final digital output. As a result, ADC 1140 will have an inherent low-pass filtering characteristic which helps reduce the sampling amplifiers and resistor noise.
The implementation illustrated above may be used concurrently with other circuit features that rely on similar circuit components. For example, it is possible to implement “black sun spot” detection and control using common circuit components with the AGC detection and control illustrated above.
A black sun spot is a problem in some image sensor implementations where very strong illumination (for example, if a camera is pointed at the sun) causes the reset value to be very large and possibly reach the maximum value for the circuit. In this case, both the reset value and the data value are at the lowest possible level of the circuit operating range, and thus the difference between the data value and the reset value is zero. As a result, the output becomes black when there is very strong incoming illumination. This is referred to as the “black sun spot” problem because the resultant output image shows a black spot when the camera is directly pointing at the sun.
Black sun spot detection may be implemented using a switched capacitor comparator and a flip flop in a manner similar to that illustrated above with respect to
In
The two S/H transistor circuits 920 are connected to V2I circuit 930, which comprises a current source having current I1 and a resistor having resistance R1 as described above. The resistor R is connected across the two S/H outputs, and as a result the current in the resistor (IR) is given by the difference between the sampled reset signal and the sampled data signal, divided by R1. That is, IR=(Vreset−Vdata)/R1.
As illustrated in
Current IR is fed via another source-follower PMOS transistor to ADC 1240, which is preferably a current mode sigma-delta ADC. Thus, ADC 1240 sees an input current (Vreset−Vdata)/R1. As described above with regard to
ADC 1240 is not restricted to a current mode sigma-delta ADC, but may be any type of analog-to-digital converter. For example, ADC 940 may be a single slope ADC, a flash ADC, a sigma-delta ADC, a successive approximation ADC, and the like. It is preferable to use a sigma-delta ADC for ADC 940, because a sigma-delta ADC operates using oversampling where each conversion is the result of many high speed samples. The output from a sigma-delta ADC may be passed through a decimation filter to generate the final digital output. As a result, ADC 1240 will have an inherent low-pass filtering characteristic which helps reduce the sampling amplifiers and resistor noise.
Clamping circuit 1260 includes a select transistor that is operated via a voltage Vclamp at the gate thereof, and a source-follower transistor. The clamping circuit restricts a minimum voltage VSL of the signal line. Thus, even if the signal line could potentially fall to a very low level as a result of very strong illumination on the photodiode, the clamping circuit maintains the voltage to a particular minimum value.
AGC/BS flip flop 1250 may be implemented as a single flip flop, or as a pair of flip flops operating in tandem such that one flip flop operates for AGC and another operates for black sun spot detection and control. In the case of a single flip flop, the AGC and BS determinations may be performed in a time divisional manner.
The comparison results during both the black sun comparison and AGC stages are latched by AGC/BS flip flop 1250 illustrated in
[Imaging Device]
Vertical signal line 1413 conducts the analog signal for a particular column to a column circuit 1430. While
Column circuit 1430 is controlled by a horizontal driving circuit 1440, also known as a “column scanning circuit.” Each of vertical driving circuit 1420, column circuit 1430, and horizontal driving circuit 1040 receive one or more clock signals from a controller 1450. Controller 1450 controls the timing and operation of various image sensor components such that analog signals from pixel array 1410, having been converted to digital signals in column circuit 1430, are output via output circuit 1460 for signal processing, storage, transmission, and the like.
CONCLUSIONWith regard to the processes, systems, methods, heuristics, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described as occurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It further should be understood that certain steps could be performed simultaneously, that other steps could be added, or that certain steps described herein could be omitted. In other words, the descriptions of processes herein are provided for the purpose of illustrating certain embodiments, and should in no way be construed so as to limit the claims.
Accordingly, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments and applications other than the examples provided would be apparent upon reading the above description. The scope should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. It is anticipated and intended that future developments will occur in the technologies discussed herein, and that the disclosed systems and methods will be incorporated into such future embodiments. In sum, it should be understood that the application is capable of modification and variation.
All terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those knowledgeable in the technologies described herein unless an explicit indication to the contrary in made herein. In particular, use of the singular articles such as “a,” “the,” “said,” etc. should be read to recite one or more of the indicated elements unless a claim recites an explicit limitation to the contrary.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
Claims
1. An image processing circuit, comprising:
- a first sample-and-hold circuit configured to sample a first data from a pixel;
- a second sample-and-hold circuit configured to sample a second data from the pixel;
- a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a difference data;
- an adaptive gain control determination circuit configured to determine whether a rate of change of a signal from the pixel exceeds a first predetermined threshold based on an output of the second sample-and-hold circuit; and
- a current-mode analog-to-digital converter configured to convert the difference data from an analog form to a digital form.
2. The image processing circuit according to claim 1, wherein
- in a case where the rate of change of the signal exceeds the first predetermined threshold, the adaptive gain control determination circuit is configured to determine that a first analog gain is to be applied, and
- in a case where the rate of change of the signal does not exceed the first predetermined threshold, the adaptive gain control determination circuit is configured to determine that a second analog gain is to be applied.
3. The image processing circuit according to claim 2, wherein the resistor is a variable resistor, and the adaptive gain control determination circuit is configured to set a resistance of the resistor to a first value in a case that the first analog gain is to be applied, and to a second value in a case where the second analog gain is to be applied.
4. The image processing circuit according to claim 2, wherein the first analog gain is a gain of 1, and the second analog gain is a gain of G, where G>1.
5. The image processing circuit according to claim 4, wherein the first predetermined threshold is a dynamic range of the pixel divided by G.
6. The image processing circuit according to claim 1, wherein the second sample-and-hold circuit includes a switched capacitor comparator circuit and a threshold shifter circuit configured to shift a threshold of the switched capacitor comparator circuit.
7. The image processing circuit according to claim 1, further comprising:
- a black sun spot determination circuit configured to determine whether the rate of change of the signal from the pixel exceeds a second predetermined threshold based on the output of the second sample-and hold circuit at a timing different from a timing of the adaptive gain control determination circuit.
8. The image processing circuit according to claim 7, wherein the second sample-and-hold circuit includes a switched capacitor comparator circuit, a first threshold shifter circuit configured to shift a threshold of the switched capacitor comparator circuit, and a second threshold shifter circuit configured to shift the threshold of the switched capacitor comparator circuit.
9. The image processing circuit according to claim 8, wherein the first threshold shifter circuit and the second threshold shifter circuit are connected in series.
10. A method of processing an image, comprising:
- sampling a first data from a pixel by a first sample-and-hold circuit;
- sampling a second data from the pixel by a second sample-and-hold circuit;
- receiving the first data and the second data by a voltage-to-current circuit including a resistor and a current source;
- outputting a difference data by the voltage-to-current circuit;
- determining whether a rate of change of a signal from the pixel exceeds a predetermined threshold by an adaptive gain control determination circuit based on an output of the second sample-and-hold circuit; and
- converting the difference data from an analog form to a digital form by a current-mode analog-to-digital converter.
11. The method according to claim 10, wherein the determining comprises:
- determining that a first analog gain is to be applied in a case where the rate of change of the signal exceeds the first predetermined threshold, and
- determining that a second analog gain is to be applied in a case where the rate of change of the signal does not exceed the first predetermined threshold.
12. The method according to claim 11, wherein the resistor is a variable resistor, the method further comprising:
- setting a resistance of the resistor to a first value by the adaptive gain control determination circuit, in a case that the first analog gain is to be applied, and
- setting the resistance of the resistor to a second value by the adaptive gain control determination circuit, in a case where the second analog gain is to be applied.
13. The method according to claim 11, wherein the first analog gain is a gain of 1, and the second analog gain is a gain of G, where G>1.
14. The method according to claim 13, wherein the first predetermined threshold is a dynamic range of the pixel divided by G.
15. The method according to claim 10, wherein the second sample-and-hold circuit includes a switched capacitor comparator circuit and a threshold shifter circuit configured to shift a threshold of the switched capacitor comparator circuit.
16. The method according to claim 10, further comprising:
- determining whether the rate of change of the signal from the pixel exceeds a second predetermined threshold by a black sun spot determination circuit based on the output of the second sample-and hold circuit at a timing different from a timing of the adaptive gain control determination circuit.
17. The method according to claim 16, wherein the second sample-and-hold circuit includes a switched capacitor comparator circuit, a first threshold shifter circuit configured to shift a threshold of the switched capacitor comparator circuit, and a second threshold shifter circuit configured to shift the threshold of the switched capacitor comparator circuit.
18. The method according to claim 17, wherein the first threshold shifter circuit and the second threshold shifter circuit are connected in series.
19. An imaging device, comprising:
- a pixel including a photoelectric conversion device configured to convert an incident light into an analog signal; and
- an image processing circuit, including: a first sample-and-hold circuit configured to sample a first data from the pixel, a second sample-and-hold circuit configured to sample a second data from the pixel, a voltage-to-current circuit including a resistor and a current source, and configured to receive the first data and the second data and output a difference data, an adaptive gain control determination circuit configured to determine whether a rate of change of the analog signal from the pixel exceeds a predetermined threshold based on an output of the second sample-and-hold circuit, and a current-mode analog-to-digital converter configured to convert the difference data from an analog form to a digital form.
20. The imaging device according to claim 19, wherein
- in a case where the rate of change of the signal exceeds the first predetermined threshold, the adaptive gain control determination circuit is configured to determine that a first analog gain is to be applied, and
- in a case where the rate of change of the signal does not exceed the first predetermined threshold, the adaptive gain control determination circuit is configured to determine that a second analog gain is to be applied.
Type: Application
Filed: Oct 30, 2015
Publication Date: May 4, 2017
Inventors: Noam Eshel (Pardesia), Golan Zeituni (Kfar-Saba)
Application Number: 14/928,536