SEMICONDUCTOR DEVICE
A semiconductor device capable of holding data for a long time is provided. The semiconductor device includes a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A first terminal of the second transistor is electrically connected to a gate of the second transistor and the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor has a wider bandgap than the first semiconductor.
1. Field of the Invention
One embodiment of the present invention relates to a semiconductor device.
One embodiment of the present invention relates to an object, a method, and a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, and a composition of matter. One embodiment of the present invention relates to a driving method of the semiconductor device and a manufacturing method of the semiconductor device.
In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. In some cases, a memory device, a display device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device.
2. Description of the Related Art
A transistor including an oxide semiconductor (OS) in a channel formation region (hereinafter referred to as an OS transistor) is known. A variety of semiconductor devices including OS transistors have been proposed.
Patent Document 1 discloses an example in which an OS transistor is used in a dynamic random access memory (DRAM). The OS transistor has extremely low leakage current in an off state (off-state current); thus, a DRAM having a low refresh frequency and low power consumption can be formed.
Patent Document 2 discloses a nonvolatile memory including an OS transistor. Unlike a flash memory, the nonvolatile memory has unlimited cycling capability, can easily operate at high speed, and consumes less power.
The off-state current of a memory including the OS transistor can be reduced when the threshold voltage of the OS transistor is increased, so that the data holding characteristics of the memory can be improved. Patent Document 2 discloses an example in which an OS transistor has a second gate (also referred to as a back gate) to control the threshold voltage of the OS transistor so that the off-state current is lowered.
In order for the memory to hold data for a long time, a constant negative potential needs to be continuously applied to the second gate of the OS transistor. Patent Documents 2 and 3 each disclose a configuration example of a circuit for driving a second gate of an OS transistor.
Patent Document 4 discloses a method in which a negative potential is generated by a charge pump and applied to a second gate of an OS transistor.
REFERENCE Patent Document
- [Patent Document 1] Japanese Published Patent Application No. 2013-168631
- [Patent Document 2] Japanese Published Patent Application No. 2012-069932
- [Patent Document 3] Japanese Published Patent Application No. 2012-146965
- [Patent Document 4] Japanese Published Patent Application No. 2015-164386
An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. Another object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.
Note that the description of a plurality of objects does not mutually preclude the existence. One embodiment of the present invention does not necessarily achieve all the objects listed above. Objects other than those listed above are apparent from the description of the specification, drawings, claims, and the like, and such objects could be an object of one embodiment of the present invention.
One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. A gate of the second transistor is electrically connected to a first terminal of the second transistor. The first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor preferably has a wider bandgap than the first semiconductor.
One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first oxide semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first oxide semiconductor provided therebetween. The second transistor includes a second oxide semiconductor in a channel formation region. A gate of the second transistor is electrically connected to a first terminal of the second transistor. The first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The first oxide semiconductor preferably contains In and M (M is Ga, Al, B, Si, Ti, Zr, La, Ce, Y, Hf, Ta, Nb, or Sc). The second oxide semiconductor preferably contains In and M. The ratio of the number of M atoms to the number of In atoms in the second oxide semiconductor is preferably higher than that in the first oxide semiconductor.
One embodiment of the present invention is a semiconductor device including first to third transistors, a capacitor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a second semiconductor in a channel formation region. The bandgap of the second semiconductor is preferably greater than or equal to 2.2 eV. A gate of the second transistor is electrically connected to a gate of the third transistor. The gate of the third transistor is electrically connected to a first terminal of the capacitor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential.
In the above embodiment, the second semiconductor preferably has a wider bandgap than the first semiconductor.
One embodiment of the present invention is a semiconductor device including first to third transistors, a capacitor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first oxide semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first oxide semiconductor provided therebetween. The second transistor includes a second oxide semiconductor in a channel formation region. A gate of the second transistor is electrically connected to a gate of the third transistor. The gate of the third transistor is electrically connected to a first terminal of the capacitor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential.
In the above embodiment, the first oxide semiconductor preferably contains In and M. The second oxide semiconductor preferably contains In and M. The ratio of the number of M atoms to the number of In atoms in the second oxide semiconductor is preferably higher than that in the first oxide semiconductor.
One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first semiconductor provided therebetween. The second transistor includes a third gate and a fourth gate. The second transistor includes a second semiconductor in a channel formation region. The third gate and the fourth gate overlap with each other in a region with the second semiconductor provided therebetween. The fourth gate and the second semiconductor overlap with each other in a region with a charge accumulation layer provided therebetween. The third gate is electrically connected to a first terminal of the second transistor. The first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The second semiconductor preferably has a wider bandgap than the first semiconductor.
One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a circuit. The first transistor includes a first gate and a second gate. The first transistor includes a first oxide semiconductor in a channel formation region. The first gate and the second gate overlap with each other in a region with the first oxide semiconductor provided therebetween. The second transistor includes a third gate and a fourth gate. The second transistor includes a second oxide semiconductor in a channel formation region. The third gate and the fourth gate overlap with each other in a region with the second oxide semiconductor provided therebetween. The fourth gate and the second oxide semiconductor overlap with each other in a region with a charge accumulation layer provided therebetween. The third gate is electrically connected to a first terminal of the second transistor. The first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to the circuit. The circuit has a function of generating a negative potential. The first oxide semiconductor preferably contains In and M. The second oxide semiconductor preferably contains In and M. The ratio of the number of M atoms to the number of In atoms in the second oxide semiconductor is preferably higher than that in the first oxide semiconductor.
One embodiment of the present invention is a memory device including the semiconductor device in any of the above embodiments.
One embodiment of the present invention is an electronic device including the semiconductor device in any of the above embodiments and a display device, a microphone, a speaker, an operation key, or a housing.
According to one embodiment of the present invention, a semiconductor device capable of holding data for a long time is provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of reducing power consumption is provided. In addition, according to one embodiment of the present invention, a novel semiconductor device is provided.
Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.
In the accompanying drawings:
Embodiments and examples of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the description below, and it is easily understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description in the following embodiments and examples.
Note that in the structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and a description thereof is not repeated. Furthermore, the same hatching pattern is applied to portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.
Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not limited to such a scale.
Unless otherwise specified, an on-state current in this specification refers to a drain current of a transistor in the on state. Unless otherwise specified, the on state of an n-channel transistor means that voltage (VGS) between its gate and source is higher than or equal to the threshold voltage (Vth), and the on state of a p-channel transistor means that VGS is lower than or equal to Vth. For example, the on-state current of an n-channel transistor sometimes refers to a drain current that flows when VGS is higher than or equal to Vth. The on-state current of a transistor depends on voltage (VDS) between its drain and source in some cases.
Unless otherwise specified, an off-state current in this specification refers to a drain current of a transistor in the off state. Unless otherwise specified, the off state of an n-channel transistor means that VGS is lower than Vth, and the off state of a p-channel transistor means that VGS is higher than Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current that flows when VGS is lower than Vth. The off-state current of a transistor depends on VGS in some cases. Thus, “the off-state current of a transistor is lower than 10−21 A” sometimes means that there is VGS at which the off-state current of a transistor is lower than 10−21 A.
The off-state current of a transistor depends on VDS in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at VDS with an absolute value of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current may be an off-state current at VDS used in a semiconductor device or the like including the transistor.
In this specification and the like, the terms “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used to describe the connection relation of a transistor. This is because a source and a drain of a transistor are interchangeable depending on the structure, operation conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (or drain) terminal, a source (or drain) electrode, or the like as appropriate depending on the situation.
In this specification, a high power supply potential is referred to as an H level (or VDD), and a low power supply potential is referred to as an L level (or GND), in some cases.
Furthermore, in this specification, any of the embodiments and the examples described below can be combined as appropriate. In addition, in the case where a plurality of structure examples are described in one embodiment, any of the structure examples can be combined as appropriate.
Embodiment 1In this embodiment, a circuit configuration of a semiconductor device of one embodiment of the present invention is described.
<<Circuit 10>>A circuit 10 illustrated in
The transistors M0 represent transistors used in a variety of circuits such as a memory circuit, an arithmetic circuit, and a pixel circuit. Although three transistors M0 are illustrated in
The transistors M0 each include a first gate and a second gate. The second gates have a function of controlling Vth of the respective transistors M0. Capacitors C0 correspond to wiring capacitance added to the second gates. In each of the transistors M0, the first gate and the second gate preferably overlap with each other in a region with a semiconductor layer provided therebetween.
The circuit 10 has a function of writing a potential to the second gates of the transistors M0 and holding the potential.
For example, in the case where a negative potential is written to the second gates of the transistors M0 by the circuit 10, V of the transistors M0 can be kept high while the negative potential of the second gates is held. When Vth of the transistors M0 is kept high, the transistors M0 can be prevented from being normally-on and therefore power consumption of the whole semiconductor device including the transistors M0 can be reduced. For example, in the case where the transistor M0 is used as a selection transistor of a memory cell, charge in a capacitor functioning as a storage can be held for a long time.
The voltage holding circuit 11 has a function of applying a potential VBG generated in the voltage generation circuit 12 to the second gates of the transistors M0 and holding the potential.
The voltage generation circuit 12 has a function of generating VBG from GND or VDD. VDD, a signal CLK, and a signal WAKE are input to the voltage generation circuit 12. The signal CLK is a clock signal and used to operate the voltage generation circuit 12. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 12. For example, when an H-level signal is supplied as the signal WAKE, the signal CLK is input to the voltage generation circuit 12 and the voltage generation circuit 12 generates VBG.
Next, a specific configuration example of the voltage holding circuit 11 is described with reference to
<Voltage Holding Circuit 11a>
A voltage holding circuit 11a illustrated in
In
The transistor M11 may include a first gate and a second gate.
In
However, when Vth of the transistor M11 is low, the cutoff current of the transistor M11 is increased and the voltage holding circuit 11a cannot hold the negative potential for a long time (a point b in
That is, in order to operate the voltage holding circuit 11a properly, the cutoff current of the transistor M11 needs to be reduced.
Furthermore, withstand voltage between a source and a drain (hereinafter referred to as source-drain withstand voltage) of the transistor M11 is preferably high. When the source-drain withstand voltage of the transistor M11 is high, the voltage generation circuit 12 generating high voltage and the transistor M0 can be easily connected to each other.
The channel length of the transistor M11 is preferably longer than that of the transistor M0. In the case where the channel length of the transistor M0 is less than 1 μm, for example, the channel length of the transistor M11 is greater than or equal to 1 μm, preferably greater than or equal to 3 μm, further preferably greater than or equal to 5 μm, and still further preferably greater than or equal to 10 μm.
When the channel length of the transistor M11 is long, the transistor M11 is not affected by a short-channel effect and the cutoff current can be low. Furthermore, the source-drain withstand voltage of the transistor M11 can be increased.
For example, when the transistor M0 is used in a circuit for which high integration is required, such as a memory cell, the channel length of the transistor M0 is preferably short. Meanwhile, the transistor M11 can be manufactured outside the memory cell; thus, a long channel length does not become a problem. When the channel length of the transistor is long, the on-state current of the transistor is decreased; however, the transistor M11 is generally used in the off state and therefore high on-state current is not required.
An OS transistor or a transistor including a wide bandgap semiconductor in a channel formation region is preferably used as the transistor M11. The off-state current is low and the source-drain withstand voltage is high in the OS transistor and the transistor including the wide bandgap semiconductor. Note that in this specification, the term “wide bandgap semiconductor” is a semiconductor whose bandgap is 2.2 eV or greater. Examples of the wide bandgap semiconductor include silicon carbide, gallium nitride, and diamond.
The cutoff current of the OS transistor or the transistor including the wide bandgap semiconductor remains low even in a high-temperature environment; thus, when such a transistor is used as the transistor M11, the circuit 10 can be operated in a high-temperature environment.
The transistor M11 preferably includes a semiconductor having low electron affinity in a channel formation region. With the use of the semiconductor having low electron affinity, Vth of the transistor M11 can be shifted in the positive direction and the cutoff current can be reduced.
The transistor M11 is required to have the cutoff current lower than that of the transistor M0 and the source-drain withstand voltage higher than that of the transistor M0. In contrast, the transistor M0 is required to have the on-state current higher than that of the transistor M11. As described above, in the case where transistors having different required properties are manufactured over the same substrate, the transistors are formed using different semiconductors. The transistor M11 preferably includes a semiconductor having a wider bandgap than that of the transistor M0 in the channel formation region. Furthermore, the transistor M11 preferably includes a semiconductor having lower electron affinity than that of the transistor M0 in the channel formation region. The transistor M0 preferably includes a semiconductor having higher electron mobility than that of the transistor M11 in a channel formation region.
Here, an oxide semiconductor containing indium (In) and an element M (an In-M oxide semiconductor) and an oxide semiconductor containing In, zinc (Zn), and the element M (an In-M-Zn oxide semiconductor) are considered. The element M is an element having higher bonding energy with oxygen than that of In. The element M is preferably gallium (Ga), for example. Other elements that can be used as the element M are aluminum (Al), boron (B), silicon (Si), titanium (Ti), zirconium (Zr), lanthanum (La), cerium (Ce), yttrium (Y), hafnium (Hf), tantalum (Ta), niobium (Nb), scandium (Sc), and the like. Our investigation shows that as the ratio of the number of M atoms [M] to the number of In atoms [In] ([M]/[In]) is increased, the bandgaps of the above-described In-M oxide semiconductor and In-M-Zn oxide semiconductor are increased.
Table 1 shows the electron affinity (χ) and the bandgap (EG) of an In—Ga oxide semiconductor, and Table 2 shows the electron affinity and the bandgap of an In—Ga—Zn oxide semiconductor in the case where the element M is Ga, for example. The values in Table 1 and Table 2 are measured by ultraviolet photoelectron spectroscopy (UPS) and a photoluminescence (PL) method.
In Table 1, IGO(α:β) is an In—Ga oxide semiconductor formed by a sputtering method using an In—Ga oxide target having a ratio of In:Ga=α:β. Similarly, in Table 2, IGZO(α:β:γ) is an In—Ga—Zn oxide semiconductor formed by a sputtering method using an In—Ga—Zn oxide target having a ratio of In:Ga:Zn=α:β:γ.
According to Table 1, as the ratio of the number of Ga atoms to the number of In atoms increases, the In—Ga oxide semiconductor has a lower electron affinity and a wider bandgap. Similarly, according to Table 2, as the ratio of the number of Ga atoms to the number of In atoms increases, the In—Ga—Zn oxide semiconductor has a lower electron affinity and a wider bandgap.
According to the above description, in the case where the In-M oxide semiconductor is used for the channel formation regions of the transistor M11 and the transistor M0, the ratio of the number of M atoms to the number of In atoms in the channel formation region of the transistor M11 is preferably higher than that in the channel formation region of the transistor M0.
Similarly, in the case where the In-M-Zn oxide semiconductor is used for the channel formation regions of the transistor M11 and the transistor M0, the ratio of the number of M atoms to the number of In atoms in the channel formation region of the transistor M11 is preferably higher than that in the channel formation region of the transistor M0.
When the transistor M11 has such a structure, the voltage holding circuit 11a can hold a potential for a long time.
<Voltage Holding Circuit 11b>
A voltage holding circuit 11b illustrated in
A gate of the transistor M13 is electrically connected to a first terminal of the capacitor C12 and a gate of the transistor M12. A first terminal of the transistor M12 is electrically connected to the second gates of the transistors M0, and a second terminal of the transistor M12 is supplied with the potential VBG from the voltage generation circuit 12.
The gate of the transistor M12, the first terminal of the capacitor C12, and the gate of the transistor M13 are in an electrically floating state. These wirings in the electrically floating state are referred to as a node N11.
Note that the transistor M12 may include a first gate and a second gate.
Next, operation of the voltage holding circuit 11b is described with reference to
First, a positive potential (VC1) is applied to a second terminal of the capacitor C12 in order to supply a tunnel current to a gate insulating film of the transistor M13, so that negative charge is injected into the node N11.
At this time, a potential difference is preferably generated between a source and a drain of the transistor M13 so that a drain current flows in the transistor M13. When the drain current flows in the transistor M13, charge can be injected into the node N11 by utilizing hot-electron injection. Note that the charge can be injected in a short time by the hot-electron injection; however, deterioration of a device is easily caused. In that case, the potential difference is not generated between the source and the drain of the transistor M13, and the charge may be injected by a Fowler-Nordheim tunneling method.
By the negative charge injected into the node N11, Vth of the transistor M12 can be increased (shifted in the positive direction). When Vth of the transistor M12 is increased, the cutoff current of the transistor M12 can be reduced.
Next, the potential VBG is applied in order to write the potential to the second gates of the transistors M0.
At this time, it is preferable that VC1 be set to approximately a potential that supplies a tunnel current to the transistor M13 and that turns on the transistor M12.
Next, VBG and VC1 are set to GND, so that the potential of the second gates of the transistors M0 is held (
The negative charge is preferably injected into the node N11 in advance at the time of
The transistor M12 may have the same characteristics as the transistor M11 of the voltage holding circuit 11a in order to reduce the cutoff current.
The channel length of the transistor M12 is preferably longer than that of the transistor M0. In the case where the channel length of the transistor M0 is less than 1 μm, for example, the channel length of the transistor M12 is greater than or equal to 1 μm, preferably greater than or equal to 3 μm, further preferably greater than or equal to 5 μm, and still further preferably greater than or equal to 10 μm.
An OS transistor or a transistor including a wide bandgap semiconductor in a channel formation region is preferably used as the transistor M12.
The transistor M12 preferably includes a semiconductor having a wider bandgap than that of the transistor M0 in a channel formation region. The transistor M0 preferably includes a semiconductor having higher electron mobility than that of the transistor M12 in the channel formation region.
In the case where the In-M oxide semiconductor is used for the channel formation regions of the transistor M12 and the transistor M0, the ratio of the number of M atoms to the number of In atoms in the channel formation region of the transistor M12 is preferably higher than that in the channel formation region of the transistor M0.
In the case where the In-M-Zn oxide semiconductor is used for the channel formation regions of the transistor M12 and the transistor M0, the ratio of the number of M atoms to the number of In atoms in the channel formation region of the transistor M12 is preferably higher than that in the channel formation region of the transistor M0.
When the transistor M12 has such a structure, the voltage holding circuit 11b can hold a potential for a long time.
<Voltage Holding Circuit 11c>
A voltage holding circuit 11c illustrated in
The transistor M14 includes a first gate and a second gate. In the transistor M14, the first gate and the second gate preferably overlap with each other in a region with a semiconductor layer provided therebetween. The transistor M14 includes a first gate insulating film between the first gate and the semiconductor layer and a second gate insulating film between the second gate and the semiconductor layer. Note that in the following description, the transistor M14 is an n-channel transistor.
The transistor M14 includes a charge accumulation layer in the second gate insulating film. In each of
When a potential VC is applied to the second gate of the transistor M14, charge can be injected into the charge accumulation layer. For example, when the potential VC that is a positive potential is applied, negative charge can be injected into the charge accumulation layer.
By the negative charge injected into the charge accumulation layer, Vth of the transistor M14 can be shifted in the positive direction. As a result, the cutoff current of the transistor M14 can be reduced, and the transistor M14 can hold the potential applied to the second gates of the transistors M0 for a long time.
A specific example of the charge accumulation layer will be described later in Embodiment 3.
The transistor M14 may have the same characteristics as the transistor M11 of the voltage holding circuit 11a in order to reduce the cutoff current.
The channel length of the transistor M14 is preferably longer than that of the transistor M0. In the case where the channel length of the transistor M0 is less than 1 μm, for example, the channel length of the transistor M14 is greater than or equal to 1 μm, preferably greater than or equal to 3 μm, further preferably greater than or equal to 5 μm, and still further preferably greater than or equal to 10 μm.
An OS transistor or a transistor including a wide bandgap semiconductor in a channel formation region is preferably used as the transistor M14.
The transistor M14 preferably includes a semiconductor having a wider bandgap than that of the transistor M0 in a channel formation region. The transistor M0 preferably includes a semiconductor having higher electron mobility than that of the transistor M14 in the channel formation region.
In the case where the In-M oxide semiconductor is used for the channel formation regions of the transistor M14 and the transistor M0, the ratio of the number of M atoms to the number of In atoms in the channel formation region of the transistor M14 is preferably higher than that in the channel formation region of the transistor M0.
In the case where the In-M-Zn oxide semiconductor is used for the channel formation regions of the transistor M14 and the transistor M0, the ratio of the number of M atoms to the number of In atoms in the channel formation region of the transistor M14 is preferably higher than that in the channel formation region of the transistor M0.
When the transistor M14 has such a structure, the voltage holding circuit 11c can hold a potential for a long time, and the circuit 10 can hold a potential for a long time.
Note that the above-described charge accumulation layer may be provided in the transistor M0.
Next, the voltage generation circuit 12 is described in detail with reference to
<Voltage Generation Circuit 12a>
As illustrated in
The transistors M21 to M24 are connected in series between the input terminal IN and the output terminal OUT, and each has a structure in which a gate and a first terminal are connected so that the transistor functions as a diode. The capacitors C21 to C24 are connected to the gates of the transistors M21 to M24, respectively.
A signal CLK is input to the first terminals of the capacitors C21 and C23 in the odd-numbered stages, and a signal CLKB is input to the first terminals of the capacitors C22 and C24 in the even-numbered stages. The signal CLKB is an inverted clock signal obtained by phase inversion of the signal CLK.
The voltage generation circuit 12a has a function of stepping down GND input to the input terminal IN to generate VBG. The voltage generation circuit 12a can generate a negative potential only by the supply of the signals CLK and CLKB.
The voltage generation circuit 12 may include a transistor having a first gate and a second gate.
<Voltage Generation Circuit 12b>
As illustrated in
The transistors M25 to M28 each include a first gate and a second gate. In each of the transistors M25 to M28, the first gate and the second gate preferably overlap with each other in a region with a semiconductor layer provided therebetween.
The transistors M25 to M28 are connected in series between the input terminal IN and the output terminal OUT, and each has a structure in which a first gate and a first terminal are connected so that the transistor functions as a diode. The capacitors C25 to C28 are connected to the first gates of the transistors M25 to M28, respectively.
The signal CLK is input to the first terminals of the capacitors C25 and C27 in the odd-numbered stages, and the signal CLKB is input to the first terminals of the capacitors C26 and C28 in the even-numbered stages. The signal CLKB is an inverted clock signal obtained by phase inversion of the signal CLK.
The voltage generation circuit 12b has a function of stepping down GND input to the input terminal IN to generate VBG. The voltage generation circuit 12b can generate a negative potential only by the supply of the signals CLK and CLKB.
In the voltage generation circuit 12b, the transistors M25 to M28 are each provided with the second gate, and voltage is applied to the second gates to control Vth of the transistors M25 to M28. In the voltage generation circuit 12b, the second gates of the transistors M25 to M28 are connected to the input terminal IN.
The second gates of the transistors M25 to M28 are connected to the input terminal IN where the voltage is the highest in the voltage generation circuit 12b. That is, voltage higher than that applied to a source is applied to the second gates of the transistors M25 to M28. This can lower Vth of the transistors M25 to M28 as compared with the case of not applying the voltage to the second gates, increasing current driving characteristics of the transistors M25 to M28. As a result, the voltage generation circuit 12b can step down the voltage with a small number of stages; thus, the number of stages can be reduced. Accordingly, the voltage generation circuit 12b can be reduced in size, leading to lower power consumption.
<Voltage Generation Circuit 12c>
In the voltage generation circuit 12c illustrated in
In the voltage generation circuit 12c, the same voltage is applied to the first gates and the second gates of the transistors M25 to M28; accordingly, the on-state current is increased as compared with the case of not applying the voltage to the second gates. As a result, the voltage generation circuit 12c can step down the voltage with a small number of stages; thus, the number of stages can be reduced. Accordingly, the voltage generation circuit 12c can be reduced in size.
<Voltage Generation Circuit 12d>
In the voltage generation circuit 12d illustrated in
The voltage generation circuit 12d has a structure in which a reduction in leakage current of the transistors M25 to M28 is emphasized as compared with the voltage generation circuits 12b and 12c. The second gates of the transistors M25 to M28 are connected to the output terminal OUT where the voltage is the lowest in the voltage generation circuit 12d. The voltage lower than those applied to sources is applied to the second gates of the transistors M25 to M28; thus, Vth of the transistors M25 to M28 in the voltage generation circuit 12d can be further increased as compared with the voltage generation circuits 12b and 12c. This can reduce reverse current of the diode-connected transistors M25 to M28, preventing leakage of charges from the capacitors C25 to C28. Accordingly, capacitance values of the capacitors C25 to C28 can be lowered, so that the voltage generation circuit 12d can be reduced in size.
When the circuit 10 has such a structure, a semiconductor device capable of holding data for a long time can be provided. In addition, a semiconductor device capable of reducing power consumption can be provided.
Embodiment 2In this embodiment, application examples of the circuit 10 described in Embodiment 1 are described with reference to
The memory cell 110 illustrated in
In the memory cell 110 illustrated in
In the memory cell 110 illustrated in
In the memory cell 110 illustrated in
The transistor M0 preferably has low off-state current. For example, the off-state current of the transistor M0 is preferably lower than or equal to 10−18 A/μm, further preferably lower than or equal to 10−21 A/μm, and still further preferably lower than or equal to 10−24 A/μm. An OS transistor can be used as a transistor having low off-state current.
The transistor 112 preferably has little variation in threshold voltage. Here, transistors with little variation in threshold voltage refer to transistors fabricated in the same process to have an acceptable threshold voltage difference of 100 mV or less, and are specifically transistors including single crystal silicon in channels.
The memory cell 110 utilizes a characteristic in which the charge of the node FN can be held, so that data can be written, held, and read as follows.
Writing and holding of data will be described. First, a potential is applied to the wiring WL so that the transistor M0 is turned on. Accordingly, the potential of the wiring BL is applied to the node FN. That is, predetermined charge is supplied to a node FN (data writing). Here, charge for applying either of two different potential levels (hereinafter referred to as an L level and an H level) is supplied. After that, the transistor M0 is turned off, so that the charge supplied to the node FN is held (data holding).
Since the off-state current of the transistor M0 is extremely low, the charge of the gate of the transistor M0 is held for a long time.
Next, reading of data will be described. An appropriate potential (reading potential) is applied to the wiring RL while a predetermined potential (constant potential) is applied to the wiring SL, so that the potential of the wiring BL varies depending on the amount of charge held in the gate of the transistor 112. In general, in the case where the transistor 112 is a p-channel transistor, an apparent threshold voltage Vth_H when the H level is supplied to the node FN is lower than an apparent threshold voltage Vth_L when the L level is supplied to the node FN. Here, the apparent threshold voltage refers to the potential of the wiring RL that is needed to turn on the transistor 112. Thus, when the potential of the wiring RL is set to a potential V0 that is between Vth_H and Vth_L, charge supplied to the gate of the transistor 112 can be determined. For example, in the case where the L level is supplied in data writing, the transistor 112 is turned on when the potential of the wiring RL is V0 (<Vth_L). In the case where the H level is supplied in data writing, the transistor 112 remains in an off state even when the potential of the wiring RL is set to V0 (>Vth_H). Therefore, the held data can be read by determining the potential of the wiring BL.
Note that although the transistor 112 is a p-channel transistor in the above description, one embodiment of the present invention is not limited thereto, and the transistor 112 might be an n-channel transistor.
The memory device 120 includes the memory cells 110 arranged in a matrix of m rows and n columns. Here, m and n are each a natural number of 2 or more. The memory cells 110 provided in an m-th row are electrically connected to wirings WL[m] and RL[m], and the memory cells 110 provided in an n-th column are electrically connected to a wiring BL[n] and the wiring SL.
The second gates of the transistors M0 included in the memory cells 110 are electrically connected to the circuit 10 through the wirings BGL. In other words, the circuit 10 has a function of controlling the second gates of the transistors M0 included in all the memory cells.
When the circuit 10 controls the second gate of the transistor M0, the transistor M0 can have appropriate Vth and can be prevented from being normally-on. Consequently, the off-state current of the transistor M0 can be reduced, and the transistor M0 can hold charge written to the node FN.
When the memory device 120 has such a structure, a memory device capable of holding data for a long time even after the memory device is powered off can be provided.
<DRAM>The memory cell 130 illustrated in
In the memory cell 130 illustrated in
The transistor M0 preferably has low off-state current. For example, the off-state current of the transistor M0 is preferably lower than or equal to 10−18 A/μm, further preferably lower than or equal to 10−21 A/μm, and still further preferably lower than or equal to 10−24 A/μm. An OS transistor can be used as a transistor having low off-state current.
The wiring WL has a function of supplying signals for controlling the on/off state of the transistor M0, and the wiring BL has a function of writing charge to the capacitor 131 through the transistor M0. By turning off the transistor M0 after charge is written to the capacitor 131, the charge written to the capacitor 131 can be held.
Since the charge written to the capacitor 131 leaks to the outside through the transistor M0, operation of rewriting (refreshing) the charge written to the capacitor 131 at regular intervals is needed. However, the refresh frequency is low because the off-state current of the transistor M0 is extremely low and the amount of charge that leaks from the capacitor 131 is small.
The memory device 140 includes the memory cells 130 arranged in a matrix of m rows and n columns. The memory cells 130 provided in the m-th row are electrically connected to the wiring WL[m], and the memory cells 130 provided in the n-th column are electrically connected to the wiring BL[n]. The wiring CL is electrically connected to a terminal VCM for applying a constant low potential.
The second gates of the transistors M0 included in the memory cells 130 are electrically connected to the circuit 10 through the wirings BGL. In other words, the circuit 10 has a function of controlling the second gates of the transistors M0 included in all the memory cells.
When the circuit 10 controls the second gate of the transistor M0, the transistor M0 can have appropriate Vth and can be prevented from being normally-on. Consequently, the off-state current of the transistor M0 can be reduced, and the transistor M0 can hold charge written to the capacitor 131.
When the memory device 140 has such a structure, a memory device capable of operating at low power with infrequent refresh operation can be provided.
<Register>The register circuit 150 includes the transistor M0 including the first and second gates, a capacitor 154, a node N5, and a flip-flop circuit 153.
The flip-flop circuit 153 includes inverters 151 and 152. The inverter 151 whose direction is opposite to the direction of the inverter 152 is connected in parallel with the inverter 152, and a node to which an output side of the inverter 151 is connected corresponds to an output terminal OUT.
The second gate of the transistor M0 is electrically connected to the circuit 10, the first gate of the transistor M0 is electrically connected to an input terminal Sig1, one of the source and the drain of the transistor M0 is electrically connected to an input terminal Sig2, and the other of the source and the drain of the transistor M0 is electrically connected to the node N5.
A first terminal of the capacitor 154 is electrically connected to the node N5, and a constant low potential is applied to a second terminal of the capacitor 154. The ground potential may be applied as the low potential. The node N5 is electrically connected to the flip-flop circuit 153.
The transistor M0 preferably has low off-state current. For example, the off-state current of the transistor M0 is preferably lower than or equal to 10−18 A/μm, further preferably lower than or equal to 10−21 A/μm, still further preferably lower than or equal to 10−24 A/μm. An OS transistor can be used as a transistor having low off-state current.
The register circuit 150 stores and outputs data with input signals from the input terminals Sig1 and Sig2. For example, when high-level voltages are input from the input terminals Sig1 and Sig2, the transistor M0 is turned on, so that a high-level voltage is input to the node N5. Consequently, a low-level voltage obtained by inversion in the inverter 151 is output from the output terminal OUT of the register circuit 150, and at the same time, data of the low-level voltage is stored in the flip-flop circuit 153. In contrast, when a low-level voltage is input from the input terminal Sig2, a high-level voltage is output from the output terminal OUT similarly, and data of the high-level voltage is stored in the flip-flop circuit 153.
The capacitor 154 has a function of holding the voltage of the node N5.
The register circuit 150 can hold the potential of the node N5 even when supply of power supply voltage is stopped by turning off the transistor M0 after a potential is applied from the input terminal Sig2 to the node N5. This is because the off-state current of the transistor M0 is extremely low. In other words, by using the register circuit 150, it is possible to provide a memory device that can hold data even after supply of power supply voltage is stopped.
The circuit 10 has a function of supplying signals for controlling the second gate of the transistor M0. When the circuit 10 controls the second gate of the transistor M0, the transistor M0 can have appropriate Vth and can be prevented from being normally-on. Consequently, the off-state current of the transistor M0 can be reduced, and the transistor M0 can hold charge written to the node N5.
Note that in this embodiment, a simple configuration of two inverter circuits is described as an example of the flip-flop circuit 153; however, one embodiment of the present invention is not limited thereto, and a clocked inverter capable of performing clock operation or a configuration in which a NAND circuit and an inverter are combined can be used as appropriate. For example, a known flip-flop circuit such as an RS flip-flop circuit, a JK flip-flop circuit, a D flip-flop circuit, or a T flip-flop circuit can be used as appropriate.
<Display Device>The first gate of the transistor M0 is electrically connected to the wiring GL, the second gate of the transistor M0 is electrically connected to the wiring BGL, one of the source and the drain of the transistor M0 is electrically connected to the wiring SL, and the other of the source and the drain of the transistor M0 is electrically connected to the node N7.
A first terminal of the capacitor 171 is electrically connected to the node N7, and a constant low potential is applied to a second terminal of the capacitor 171.
The capacitor 171 may be provided as needed. In the case where parasitic capacitance of an electrode, a wiring, or the like can be used as capacitance needed to drive the pixel 170, the capacitor 171 may be omitted.
The transistor M0 preferably has low off-state current. For example, the off-state current of the transistor M0 is preferably lower than or equal to 10−18 A/μm, further preferably lower than or equal to 10−21 A/μm, still further preferably lower than or equal to 10−24 A/μm. An OS transistor can be used as a transistor having low off-state current.
A first terminal of the display element 172 is electrically connected to the node N7, and a constant low potential is applied to a second terminal of the display element 172. The ground potential may be applied as the low potential. A dielectric element whose optical characteristics are changed when voltage is applied to its electrodes at opposite ends can be used as the display element 172. For example, a liquid crystal element or an element used for electronic paper or the like, such as an electrophoretic element or a twisting ball element, can be used.
The wiring GL has a function of supplying signals for controlling the on/off state of the transistor M0, and the wiring SL has a function of supplying voltage applied to the display element 172 through the transistor M0.
Since the off-state current of the transistor M0 is extremely low, when the transistor M0 is turned off, the node N7 can hold voltage applied immediately before turning off the transistor M0. While the voltage of the node N7 is held, the display element 172 can maintain its display state.
The pixel 170 can hold the voltage of the node N7 for a long time. Thus, the optical characteristics of the display element 172 can be unchanged even when supply of power supply voltage is stopped. For example, even in the case where a liquid crystal element that cannot store data, such as a twisted nematic (TN) liquid crystal, is used, the element can be always maintained in a state in which voltage is applied. Consequently, it is possible to exclude rewrite operation or it is possible to reduce the frequency of rewrite operation markedly.
The display device 180 includes the pixels 170 arranged in a matrix of m rows and n columns. The pixels 170 provided in the m-th row are electrically connected to a wiring GL[m], and the pixels 170 provided in the n-th column are electrically connected to a wiring SL[n].
The second gates of the transistors M0 included in the pixels 170 are electrically connected to the circuit 10 through the wirings BGL. In other words, the circuit 10 has a function of controlling the second gates of the transistors M0 included in all the pixels.
When the circuit 10 controls the second gate of the transistor M0, the transistor M0 can have appropriate Vth and can be prevented from being normally-on. Consequently, the off-state current of the transistor M0 can be reduced, and the transistor M0 can hold charge written to the node N7.
The circuit 10 can control and hold Vth of the transistors M0 in the pixels 170 connected to the circuit 10 at optimal levels and can temporarily change Vth so that the transistors M0 are set as normally-on transistors. When m×n transistors connected to the circuit 10 are temporarily changed into normally-on transistors, the voltage (i.e., display images) stored in the pixels can be refreshed at the same time by one signal.
When the display device 180 has such a structure, a display device capable of operating at low power with infrequent rewrite operation can be provided. In addition, a display device including a plurality of pixels that can easily perform refresh operation can be obtained. Furthermore, a display device capable of displaying an image even when supply of power is stopped can be obtained.
Embodiment 3In this embodiment, structures of the OS transistors used in any of the above embodiments are described.
<Oxide Semiconductor>First, an oxide semiconductor that can be used for an OS transistor is described.
An oxide semiconductor preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. Here, the case where an oxide semiconductor contains indium, an element M, and zinc is considered.
First, preferred ranges of the atomic ratio of indium, the element M, and zinc contained in an oxide semiconductor according to the present invention are described with reference to
In
Dashed-dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is 1:1:β (where β≧0), a line where the atomic ratio [In]:[M]:[Zn] is 1:2:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:3:β, a line where the atomic ratio [In]:[M]:[Zn] is 1:4:β, a line where the atomic ratio [In]:[M]:[Zn] is 2:1:β, and a line where the atomic ratio [In]:[M]:[Zn] is 5:1:β.
Dashed-double dotted lines indicate a line where the atomic ratio [In]:[M]:[Zn] is (1+γ):2:(1−γ) (where −1≦γ≦1). The oxide semiconductor shown in
InMZnO4 has a layered crystal structure (also referred to as a layered structure) and includes one layer that contains indium and oxygen (hereinafter referred to as an In layer) for every two (M,Zn) layers that contain the element M, zinc, and oxygen, as illustrated in
Indium and the element M can be replaced with each other. Therefore, when the element Min the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. In that case, a layered structure that contains one In layer for every two (In,M,Zn) layers is obtained.
An oxide semiconductor whose atomic ratio [In]:[M]:[Zn] is 1:1:2 has a layered structure that contains one In layer for every three (M,Zn) layers. In other words, if [Zn] is higher than [In] and [M], the proportion of the (M,Zn) layer to the In layer becomes higher when the oxide semiconductor is crystallized.
Note that in the case where the number of (M,Zn) layers with respect to one In layer is not an integer in the oxide semiconductor, the oxide semiconductor might have plural kinds of layered structures where the number of (M,Zn) layers with respect to one In layer is an integer. For example, in the case of [In]:[M]:[Zn]=1:1:1.5, the oxide semiconductor might have the following layered structures: a layered structure of one In layer for every two (M,Zn) layers and a layered structure of one In layer for every three (M,Zn) layers.
For example, in the case where the oxide semiconductor is deposited with a sputtering apparatus, a film having an atomic ratio deviated from the atomic ratio of a target is formed. In particular, [Zn] in the film might be smaller than [Zn] in the target depending on the substrate temperature in deposition.
A plurality of phases (e.g., two phases or three phases) exist in the oxide semiconductor in some cases. For example, with an atomic ratio [In]:[M]:[Zn] that is close to 0:2:1, two phases of a spinel crystal structure and a layered crystal structure are likely to exist. In addition, with an atomic ratio [In]:[M]:[Zn] that is close to 1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide semiconductor, a grain boundary might be formed between different crystal structures.
In addition, the oxide semiconductor containing indium in a higher proportion can have high carrier mobility (electron mobility). This is because in an oxide semiconductor containing indium, the element M, and zinc, the s orbital of heavy metal mainly contributes to carrier transfer, and when the indium content in the oxide semiconductor is increased, overlaps of the s orbitals of indium atoms are increased; therefore, an oxide semiconductor having a high content of indium has higher carrier mobility than that of an oxide semiconductor having a low content of indium.
In contrast, when the indium content and the zinc content in an oxide semiconductor become lower, carrier mobility becomes lower. Thus, with an atomic ratio of [In]:[M]:[Zn]=0:1:0 and the vicinity thereof (e.g., a region C in
Accordingly, an oxide semiconductor in one embodiment of the present invention preferably has an atomic ratio represented by a region A in
A region B in
Note that conditions where a layered structure of an oxide semiconductor is formed are not uniquely determined by the atomic ratio. There is a difference in the degree of difficulty in forming a layered structure among atomic ratios. Even with the same atomic ratio, whether a layered structure is formed or not depends on a formation condition. Therefore, the regions illustrated in
The transistor 200 includes a conductor 205 (conductors 205a and 205b) and a conductor 260 that function as gate electrodes, insulators 220, 222, 224, and 250 that function as gate insulating layers, an oxide semiconductor 230 (oxide semiconductors 230a, 230b, and 230c), a conductor 240a that functions as one of a source and a drain, a conductor 240b that functions as the other of the source and the drain, and an insulator 280 that includes excess oxygen.
The oxide semiconductor 230 includes the oxide semiconductor 230a, the oxide semiconductor 230b over the oxide semiconductor 230a, and the oxide semiconductor 230c over the oxide semiconductor 230b. Note that the oxide semiconductor 230b functions as a channel formation region because when the transistor 200 is turned on, current flows mainly in the oxide semiconductor 230b. Although current sometimes flows in regions in the vicinity of the interfaces (mixed regions in some cases) between the oxide semiconductor 230b and the oxide semiconductors 230a and 230c, the other regions of the oxide semiconductors 230a and 230c function as insulators.
The conductor 205 is formed using a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (e.g., a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.
For example, a conductor having a barrier property against hydrogen, e.g., tantalum nitride, may be used as the conductor 205a, and tungsten, which has high conductivity, may be stacked thereover as the conductor 205b. The use of the combination of the materials can suppress diffusion of hydrogen into the oxide semiconductor 230 while conductivity of a wiring is ensured. Note that a two-layer structure of the conductor 205a and the conductor 205b is illustrated in
Each of the insulators 220 and 224 is preferably an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. In particular, the insulator 224 is preferably an insulator containing excess oxygen (containing oxygen in excess of that in the stoichiometric composition). In the case where such an insulator containing excess oxygen is provided in contact with an oxide semiconductor in the transistor 200, oxygen vacancies in the oxide semiconductor can be compensated. Note that the insulators 220 and 224 are not necessarily formed of the same material.
The insulator 222 preferably has a single-layer structure or a stacked-layer structure formed using an insulator containing silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), or the like. Aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. A layer of silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.
Note that the insulator 222 may have a stacked-layer structure of two or more layers. In this case, the stacked layers are not necessarily formed of the same material but may be formed of different materials.
In the case where the insulator 222 including a high-k material is provided between the insulator 220 and the insulator 224, the insulator 222 can be negatively charged. That is, the insulator 222 can function as the charge accumulation layer in the voltage holding circuit 11c described in Embodiment 1.
For example, in the case where the insulator 220 and the insulator 224 are formed using silicon oxide and the insulator 222 is formed using a material having a lot of electron trap states such as hafnium oxide, aluminum oxide, or tantalum oxide, the state where the potential of the conductor 205 is higher than the potential of the source electrode and the drain electrode is kept at a temperature higher than the operating temperature or the storage temperature of the semiconductor device (e.g., at a temperature of 125° C. or higher and 450° C. or lower, typically 150° C. or higher and 300° C. or lower) for 10 milliseconds or longer, typically one minute or longer. Thus, electrons are moved from the oxide semiconductor in the transistor 200 to the conductor 205. At this time, some of the moving electrons are trapped by the electron trap states of the insulator 222.
In the transistor in which a necessary amount of electrons is trapped by the electron trap states of the insulator 222, Vth is shifted in the positive direction. By controlling the voltage of the conductor 205, the amount of electrons to be trapped can be controlled, and thus Vth can be controlled.
The treatment for trapping the electrons may be performed in the manufacturing process of the transistor. For example, the treatment is preferably performed at any step before factory shipment, such as after the formation of a conductor connected to a source conductor or a drain conductor of the transistor, after the preceding process (wafer processing), after a wafer-dicing step, or after packaging.
Furthermore, Vth can be controlled by appropriate adjustment of the thicknesses of the insulators 220, 222, and 224. A transistor having low leakage current in an off state can be provided. The thicknesses of the insulators 220, 222, and 224 are preferably reduced because Vth can be easily controlled by the conductor 205. For example, each of the thicknesses of the insulators 220, 222, and 224 is less than or equal to 50 nm, preferably less than or equal to 30 nm, further preferably less than or equal to 10 nm, and still further preferably less than or equal to 5 nm.
The oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are formed using metal oxide such as In-M-Zn oxide. In—Ga oxide or In—Zn oxide may be used as the oxide semiconductor 230.
The energy level of the conduction band minimum of each of the oxide semiconductors 230a and 230c is closer to the vacuum level than that of the oxide semiconductor 230b. Typically, a difference in the energy level between the conduction band minimum of the oxide semiconductor 230b and the conduction band minimum of each of the oxide semiconductors 230a and 230c is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV. That is, a difference in the electron affinity between each of the oxide semiconductors 230a and 230c and the oxide semiconductor 230b is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV.
The energy gap of the oxide semiconductor 230b is preferably greater than or equal to 2 eV and further preferably greater than or equal to 2.5 eV and less than or equal to 3.0 eV. Furthermore, the energy gap of each of the oxide semiconductors 230a and 230c is preferably greater than or equal to 2 eV, further preferably greater than or equal to 2.5 eV, and still further preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV. The energy gap of each of the oxide semiconductors 230a and 230c is preferably greater than that of the oxide semiconductor 230b. For example, a difference in the energy gap between the oxide semiconductor 230a and the oxide semiconductor 230b is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV. Similarly, a difference in the energy gap between the oxide semiconductor 230c and the oxide semiconductor 230b is preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV.
The thickness of each of the oxide semiconductors 230a, 230b, and 230c is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 60 nm.
When the carrier density of an oxide semiconductor is reduced, the negative shift of the threshold voltage of a transistor can be suppressed or the off-state current of the transistor can be reduced. A state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, and thus can have a low carrier density.
A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor is preferably used as the oxide semiconductors 230a and 230c. For example, the carrier density of the oxide semiconductors 230a and 230c is lower than 8×1011/cm3, preferably lower than 1×1011/cm3, further preferably lower than 1×1010/cm3, and greater than or equal to 1×10−9/cm3.
In contrast, when the carrier density of the oxide semiconductor is increased, the field-effect mobility of the transistor can be increased in some cases. In order to increase the carrier density of the oxide semiconductor, the impurity concentration in the oxide semiconductor is slightly increased or the density of defect states in the oxide semiconductor is increased. For example, an oxide semiconductor in which the impurity concentration is slightly increased or the density of defect states is increased in the range where a favorable on/off ratio is obtained in the VGS-IDS characteristics of the transistor can be regarded as substantially intrinsic.
The carrier density of the oxide semiconductor 230b is preferably higher than that of the oxide semiconductors 230a and 230c. The carrier density of the oxide semiconductor 230b is preferably higher than or equal to 1×105 cm−3 and lower than 1×1018 cm−3, further preferably higher than or equal to 1×107 cm−3 and lower than or equal to 1×1017 cm−3, still further preferably higher than or equal to 1×109 cm−3 and lower than or equal to 5×1016 cm−3, yet further preferably higher than or equal to 1×1010 cm−3 and lower than or equal to 1×1016 cm−3, and yet still preferably higher than or equal to 1×1011 cm−3 and lower than or equal to 1×1015 cm−3.
The density of defect states in a mixed layer formed at an interface between the oxide semiconductors 230a and 230b or an interface between the oxide semiconductors 230b and 230c is preferably made low.
Specifically, when the oxide semiconductors 230a and 230b or the oxide semiconductors 230b and 230c contain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide semiconductor 230b is an In—Ga—Zn oxide semiconductor, it is preferable to use an In—Ga—Zn oxide semiconductor, a Ga—Zn oxide semiconductor, gallium oxide, or the like as each of the oxide semiconductors 230a and 230c.
At this time, the oxide semiconductor 230b serves as a main carrier path. Since the density of defect states at the interface between the oxide semiconductors 230a and 230b and the interface between the oxide semiconductors 230b and 230c can be made low, the influence of interface scattering on carrier conduction is small, and high on-state current can be obtained.
When an electron is trapped in a trap state, the trapped electron behaves like fixed charge; thus, Vth of a transistor is shifted in the positive direction. The oxide semiconductors 230a and 230c can make the trap state apart from the oxide semiconductor 230b. This structure can prevent the positive shift of Vth of the transistor.
A material whose conductivity is sufficiently lower than that of the oxide semiconductor 230b is used for the oxide semiconductors 230a and 230c. In that case, the oxide semiconductor 230b, the interface between the oxide semiconductors 230b and 230a, and the interface between the oxide semiconductors 230b and 230c mainly function as a channel region. For example, an oxide semiconductor with high insulation performance and any of the atomic ratios represented by the region C in
In the case where an oxide semiconductor with any of the atomic ratios represented by the region A in
Here, in the transistor 200 illustrated in
The oxide semiconductor 230c has lower crystallinity than the oxide semiconductor 230b in some cases. The oxide semiconductor 230b preferably includes a CAAC-OS which is described later. When the crystallinity of the oxide semiconductor 230c is reduced, the oxide semiconductor 230c has higher oxygen permeability; thus, oxygen is easily supplied from the insulator positioned above the oxide semiconductor 230c to the oxide semiconductor 230b in some cases. Here, the oxide semiconductor 230c may be an amorphous oxide semiconductor or an amorphous-like oxide semiconductor (a-like OS) which is described later.
The oxide semiconductor 230a may include a CAAC-OS. The oxide semiconductor 230a preferably has higher crystallinity than the oxide semiconductor 230c.
The insulator 250 can have a single-layer structure or a stacked-layer structure formed using an insulator containing silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), or the like. Aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. A layer of silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.
As the insulator 250, like the insulator 224, an oxide insulator that contains oxygen in excess of the stoichiometric composition is preferably used. When such an insulator containing excess oxygen is provided in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be reduced.
As the insulator 250, an insulating film formed of aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, or the like, which has barrier properties against oxygen and hydrogen, can be used. The insulator 250 formed of such a material functions as a layer that prevents release of oxygen from the oxide semiconductor 230 and entry of impurities such as hydrogen from the outside.
Note that the insulator 250 may have a stacked-layer structure similar to that of the insulator 220, the insulator 222, and the insulator 224. When the insulator 250 includes an insulator in which a necessary amount of electrons is trapped by electron trap states, Vth of the transistor 200 can be shifted in the positive direction. The transistor 200 having the structure is a normally-off transistor that is in a non-conduction state (also referred to as an off state) even when the gate voltage is 0 V.
In addition to the insulator 250, a barrier film may be provided between the oxide semiconductor 230 and the conductor 260 in the semiconductor device illustrated in
For example, an insulating film containing excess oxygen is provided in contact with the oxide semiconductor 230 and covered by a barrier film, whereby the composition of the oxide semiconductor can be almost the same as the stoichiometric composition or can be in a supersaturated state containing more oxygen than that in the stoichiometric composition. It is also possible to prevent entry of impurities such as hydrogen into the oxide semiconductor 230.
One of the conductor 240a and the conductor 240b functions as a source electrode and the other functions as a drain electrode.
Any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of the metals as its main component can be used for the conductors 240a and 240b. Although a single-layer structure is illustrated in the drawings, a stacked-layer structure of two or more layers may be used.
For example, a titanium film and an aluminum film may be stacked. Other examples include a two-layer structure where an aluminum film is stacked over a tungsten film, a two-layer structure where a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure where a copper film is stacked over a titanium film, and a two-layer structure where a copper film is stacked over a tungsten film.
Other examples include a three-layer structure where a titanium film or a titanium nitride film is formed, an aluminum film or a copper film is stacked over the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is formed over the aluminum film or the copper film; and a three-layer structure where a molybdenum film or a molybdenum nitride film is formed, an aluminum film or a copper film is stacked over the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed over the aluminum film or the copper film. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.
The conductor 260 functioning as a gate electrode can be formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of these metals as its component, or an alloy containing any of these metals in combination. Alternatively, one or both of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
For example, a two-layer structure where a titanium film is stacked over an aluminum film may be used. Other examples include a two-layer structure where a titanium film is stacked over a titanium nitride film, a two-layer structure where a tungsten film is stacked over a titanium nitride film, and a two-layer structure where a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film.
Other examples include a three-layer structure where a titanium film is formed, an aluminum film is stacked over the titanium film, and a titanium film is formed over the aluminum film. Alternatively, an alloy film or a nitride film that contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.
The conductor 260 can also be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. The conductor 260 can have a stacked-layer structure of the above light-transmitting conductive material and the above metal.
When a conductive material having a high work function is used for the conductor 260, Vth of the transistor 200 can be increased and the cutoff current of the transistor 200 can be reduced. A conductive material whose work function is preferably greater than or equal to 4.8 eV, further preferably greater than or equal to 5.0 eV, still further preferably greater than or equal to 5.2 eV, yet further preferably greater than or equal to 5.4 eV, and yet still further preferably greater than or equal to 5.6 eV is used for the conductor 260. Examples of a conductive material having a high work function include molybdenum, molybdenum oxide, platinum (Pt), platinum (Pt) silicide, nickel (Ni) silicide, indium tin oxide, and In—Ga—Zn oxide to which nitrogen is added.
The insulator 280 is provided over the transistor 200. The insulator 280 preferably includes an insulator containing oxygen in excess of that in the stoichiometric composition. That is, in the insulator 280, a region containing oxygen in excess of that in the stoichiometric composition (hereinafter also referred to as excess-oxygen region) is preferably formed. In particular, in the case of using an oxide semiconductor in the transistor 200, when an insulator including an excess-oxygen region is provided as an interlayer film or the like in the vicinity of the transistor 200, oxygen vacancies in the transistor 200 are reduced, whereby the reliability can be improved.
As the insulator including the excess-oxygen region, specifically, an oxide material that releases part of oxygen by heating is preferably used. An oxide material that releases part of oxygen by heating is an oxide film of which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018 atoms/cm3, preferably greater than or equal to 3.0×1020 atoms/cm3 in TDS analysis. Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C.
For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, “silicon oxynitride” refers to a material that contains oxygen at a higher proportion than nitrogen, and “silicon nitride oxide” refers to a material that contains nitrogen at a higher proportion than oxygen.
The insulator 280 covering the transistor 200 may function as a planarization film that covers a roughness thereunder.
<Transistor Structure 2>Note that in the transistor 200 in
In the structure illustrated in
The conductor 260a is formed by a thermal CVD method, an MOCVD method, or an atomic layer deposition (ALD) method. In particular, the conductor 260a is preferably formed by an ALD method. When the conductor 260a is formed by an ALD method or the like, plasma damage to the insulator 250 can be reduced. In addition, the conductor 260a is preferably formed by an ALD method or the like because coverage thereof can be improved. Thus, the highly reliable transistor 200 can be provided.
The conductor 260b is formed using a material having high conductivity, such as tantalum, tungsten, copper, or aluminum. Furthermore, the conductor 260c formed over the conductor 260b is preferably formed using a conductor that is not easily oxidized, such as tungsten nitride. In the case where the insulator 280 is formed using an oxide material from which oxygen is released, the conductor 260 can be prevented from being oxidized by the released oxygen.
Thus, the oxidation of the conductor 260 can be prevented, and oxygen released from the insulator 280 can be supplied to the oxide semiconductor 230 efficiently.
When the conductor 260c having a large contact area with the insulator 280 including the excess-oxygen region is formed using a conductor that is not easily oxidized, it is possible to suppress absorption of excess oxygen in the insulator 280 by the conductor 260. Furthermore, when the conductor 260b is formed using a conductor having high conductivity, the transistor 200 with low power consumption can be provided.
<Transistor Structure 3>Note that in the transistor 200 in
The structure illustrated in
The conductor 260a is formed by a thermal CVD method, an MOCVD method, or an ALD method. In particular, the conductor 260a is preferably formed by an ALD method. When the conductor 260a is formed by an ALD method or the like, plasma damage to the insulator 250 can be reduced. In addition, the conductor 260a is preferably formed by an ALD method or the like because coverage thereof can be improved. Thus, the highly reliable transistor 200 can be provided.
The conductor 260b is formed using a material having high conductivity, such as tantalum, tungsten, copper, or aluminum.
The insulator 270 is provided to cover the conductor 260. In the case where the insulator 280 is formed using an oxide material from which oxygen is released, the insulator 270 is formed using a substance having a barrier property against oxygen to prevent the conductor 260 from being oxidized by the released oxygen.
For example, the insulator 270 can be formed using metal oxide such as aluminum oxide. The insulator 270 is formed to a thickness with which the oxidation of the conductor 260 is prevented. For example, the thickness of the insulator 270 is set greater than or equal to 1 nm and less than or equal to 10 nm, preferably greater than or equal to 3 nm and less than or equal to 7 nm.
Thus, the oxidation of the conductor 260 can be prevented, and oxygen released from the insulator 280 can be supplied to the oxide semiconductor 230 efficiently.
<Transistor Structure 4>Note that in the transistor 200 in
In the structure illustrated in
For example, in the case where metal oxide containing indium is used for the oxide semiconductor 230b, titanium nitride or the like is used for the conductors 240a and 240b. When a material having high conductivity, such as tantalum, tungsten, copper, or aluminum, is used for the conductors 241a and 241b, the transistor 200 with high reliability and low power consumption can be provided.
As illustrated in
Note that in the transistor 200 in
The oxide semiconductor 230c, the insulator 250, and the conductor 260 are formed in an opening formed in the insulator 280.
Since the transistor 200 illustrated in
Note that in the transistor 200 in
In the transistor 200 illustrated in
Since the transistor 200 illustrated in
The oxide semiconductor 230d is provided between the oxide semiconductor 230b and the insulator 280 including the excess-oxygen region. Thus, generation of a shallow level in the vicinity of a channel formed in the oxide semiconductor 230b is suppressed as compared with the case where the oxide semiconductor 230b is directly in contact with the insulator 280 as illustrated in
In this embodiment, one embodiment of a semiconductor device is described with reference to
Examples of a semiconductor device of one embodiment of the present invention are illustrated in
The semiconductor device of one embodiment of the present invention includes a transistor 300, the transistor 200, and a capacitor 400 as illustrated in
The transistor 300 is provided over a substrate 301 and includes a conductor 306, an insulator 304, a semiconductor region 302 that is a part of the substrate 301, and low-resistance regions 308a and 308b functioning as a source region and a drain region.
The transistor 300 may be a p-channel transistor or an n-channel transistor.
It is preferable that a region of the semiconductor region 302 where a channel is formed, a region in the vicinity thereof, the low-resistance regions 308a and 308b functioning as a source region and a drain region, and the like contain silicon, more preferably single crystal silicon. Alternatively, a material including germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), gallium aluminum arsenide (GaAlAs), or the like may be contained. Silicon whose effective mass is controlled by applying stress to the crystal lattice and thereby changing the lattice spacing may be contained. Alternatively, the transistor 300 may be a high-electron-mobility transistor (HEMT) with GaAs, GaAlAs, or the like.
The low-resistance regions 308a and 308b contain an element which imparts n-type conductivity, such as arsenic or phosphorus, or an element which imparts p-type conductivity, such as boron, in addition to a semiconductor material used for the semiconductor region 302.
The conductor 306 functioning as a gate electrode can be formed using a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron, or a conductive material such as a metal material, an alloy material, or a metal oxide material.
Note that a work function is determined by a material of the conductor, whereby the threshold voltage can be adjusted. Specifically, it is preferable to use titanium nitride, tantalum nitride, or the like as the conductor. Furthermore, in order to ensure the conductivity and embeddability of the conductor, it is preferable to use a stack including metal materials such as tungsten and aluminum as the conductor. In particular, tungsten is preferable in terms of heat resistance.
Note that the transistor 300 illustrated in
An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked sequentially and cover the transistor 300.
The insulator 320, the insulator 322, the insulator 324, and the insulator 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.
The insulator 322 functions as a planarization film for eliminating a level difference caused by the transistor 300 or the like underlying the insulator 322. A top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to increase the level of planarity.
The insulator 324 is preferably formed using, for example, a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 301, the transistor 300, or the like into a region where the transistor 200 is formed.
As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. Diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that suppresses hydrogen diffusion is preferably provided between the transistor 200 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film from which hydrogen is less likely to be released.
The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulator 324 that is converted into hydrogen atoms per area of the insulator 324 is less than or equal to 10×1015 atoms/cm2, preferably less than or equal to 5×1015 atoms/cm2 in TDS analysis in the range of 50° C. to 500° C., for example.
Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 324 is preferably 0.7 times or less that of the insulator 326, more preferably 0.6 times or less that of the insulator 326. In the case where a material with a low dielectric constant is used as an interlayer film, the parasitic capacitance between wirings can be reduced.
A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 400 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 each function as a plug or a wiring. Note that a plurality of structures of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases, as described later. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where a part of a conductor functions as a wiring and a part of a conductor functions as a plug.
As a material of each of plugs and wirings (e.g., the conductor 328 and the conductor 330), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single-layer structure or a stacked-layer structure. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.
Furthermore, the conductor 328 and the conductor 330 preferably include a conductor having a barrier property against hydrogen. The conductor having a barrier property against hydrogen is formed particularly in an opening of the insulator 324 having a barrier property against hydrogen. In such a structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, so that diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.
Note that as the conductor having a barrier property against hydrogen, tantalum nitride may be used, for example. By stacking tantalum nitride and tungsten, which has high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while the conductivity of a wiring is ensured. In this case, a tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 324 having a barrier property against hydrogen.
A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in
In addition, the conductor 356 is preferably formed using a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. Note that in the case where copper is used for the conductor 356, a conductor that suppresses diffusion of copper and the conductor 356 are preferably stacked. The conductor that suppresses diffusion of copper is preferably formed using, for example, tantalum, an alloy containing tantalum such as tantalum nitride, ruthenium, or an alloy containing ruthenium.
For example, the insulator 350 is preferably formed using an insulator that suppresses diffusion of copper or that has barrier properties against oxygen and hydrogen. For a film that suppresses diffusion of copper, silicon nitride can be used, for example. Therefore, the insulator 350 can be formed using a material similar to that used for forming the insulator 324.
It is particularly preferable that a conductor that suppresses diffusion of copper be provided in an opening included in the insulator 350 that suppresses diffusion of copper, and copper be stacked over the conductor that suppresses diffusion of copper. This structure can suppress diffusion of copper into the vicinity of a wiring.
An insulator 358, an insulator 210, an insulator 212, and an insulator 214 are stacked sequentially over the insulator 354. A substance that suppresses diffusion of copper or that has barrier properties against oxygen and hydrogen is preferably used for one or all of the insulator 358, the insulator 210, the insulator 212, and the insulator 214.
The insulator 358 and the insulator 212 are preferably formed using, for example, a film that suppresses diffusion of copper from a region where the substrate 301 or the transistor 300 is formed or the like into a region where the transistor 200 is formed, or a film having a barrier property that suppresses diffusion of hydrogen or impurities from the region where the substrate 301 or the transistor 300 is formed or the like into the region where the transistor 200 is formed. Therefore, the insulator 358 and the insulator 212 can be formed using a material similar to that used for forming the insulator 324.
The insulator 210 can be formed using a material similar to that used for forming the insulator 320. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 210.
As the insulator 214, metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used, for example.
In particular, aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as hydrogen and moisture which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as hydrogen and moisture into the transistor 200 in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide semiconductor in the transistor 200 can be suppressed. Therefore, aluminum oxide is suitably used as a protective film for the transistor 200.
An insulator 216 is provided over the insulator 214. The insulator 216 can be formed using a material similar to that used for forming the insulator 320. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 216.
A conductor 218 and the like are embedded in the insulator 358, the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 functions as a plug or a wiring that is electrically connected to the capacitor 400 or the transistor 300. The conductor 218 can be formed using a material similar to that used for forming the conductor 328 and the conductor 330.
In particular, the conductor 218 in a region in contact with the insulator 358, the insulator 212, and the insulator 214 is preferably a conductor that suppresses diffusion of copper or that has barrier properties against oxygen, hydrogen, and water. In such a structure, the transistor 300 and the transistor 200 can be completely separated by a layer that suppresses diffusion of copper or that has barrier properties against oxygen, hydrogen, and water. That is, diffusion of copper from the conductor 356 or diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.
The transistor 200 and the insulator 280 are provided over the insulator 214. Note that the transistor 200 illustrated in
An insulator 282, an insulator 284, and an insulator 410 are stacked sequentially over the insulator 280. A conductor 244 and the like are embedded in the insulator 220, the insulator 222, the insulator 224, the insulator 280, the insulator 282, the insulator 284, and the insulator 410. Note that the conductor 244 functions as a plug or a wiring that is electrically connected to the capacitor 400, the transistor 200, or the transistor 300. The conductor 244 can be formed using a material similar to that used for forming the conductor 328 and the conductor 330.
Note that a substance having barrier properties against oxygen and hydrogen is preferably used for one or both of the insulator 282 and the insulator 284. Thus, the insulator 282 can be formed using a material similar to that used for forming the insulator 214. The insulator 284 can be formed using a material similar to that used for forming the insulator 212. The insulator 410 can be formed using an insulator similar to that of the insulator 210.
As the insulator 282, metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used, for example.
In particular, aluminum oxide has an excellent blocking effect that prevents permeation of oxygen and impurities such as hydrogen and moisture which cause a change in electrical characteristics of the transistor. Accordingly, the use of aluminum oxide can prevent entry of impurities such as hydrogen and moisture into the transistor 200 in and after a manufacturing process of the transistor. In addition, release of oxygen from the oxide semiconductor in the transistor 200 can be suppressed. Therefore, aluminum oxide is suitably used as a protective film for the transistor 200.
The insulator 284 is preferably formed using, for example, a film having a barrier property that prevents hydrogen or impurities from diffusing from a region where the capacitor 400 is formed into a region where the transistor 200 is formed. Therefore, the insulator 284 can be formed using a material similar to that used for forming the insulator 324.
As an example of the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be given. Diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that suppresses hydrogen diffusion is preferably provided between the transistor 200 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film from which hydrogen is less likely to be released.
Therefore, a structure can be obtained in which the transistor 200 and the insulator 280 including the excess-oxygen region are positioned between a stacked-layer structure of the insulator 210, the insulator 212, and the insulator 214 and a stacked-layer structure of the insulator 282, the insulator 284, and the insulator 410. The insulator 212, the insulator 214, the insulator 282, and the insulator 284 have a barrier property that suppresses diffusion of oxygen or impurities such as hydrogen and water.
Oxygen released from the insulator 280 and the transistor 200 can be prevented from diffusing into the layer where the capacitor 400 is formed or the layer where the transistor 300 is formed. Furthermore, impurities such as hydrogen and water can be prevented from diffusing from a layer over the insulator 282 and a layer under the insulator 214 into the transistor 200.
That is, oxygen can be efficiently supplied from the excess-oxygen region of the insulator 280 to the oxide semiconductor in the transistor 200, so that oxygen vacancies can be reduced. Moreover, oxygen vacancies can be prevented from being formed by impurities in the oxide semiconductor in the transistor 200. Thus, the oxide semiconductor in the transistor 200 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved.
For example, as illustrated in
In the structure, the transistor 200 and the insulator 280 can be enclosed with the insulator 212, the insulator 214, the insulator 282, and the insulator 284. The insulator 212, the insulator 214, the insulator 282, and the insulator 284 have a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, entry and diffusion of hydrogen or water from the side surfaces of the transistor 200 and the insulator 280 into the transistor 200 can be prevented even when the semiconductor device described in this embodiment is subjected to scribing.
Furthermore, in the structure, excess oxygen in the insulator 280 can be prevented from diffusing into the outside of the insulator 282 and the insulator 214. Accordingly, excess oxygen in the insulator 280 is efficiently supplied to the oxide semiconductor in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide semiconductor in the transistor 200. Thus, the oxide semiconductor in the transistor 200 can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, a change in electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved.
In another example, as illustrated in
The conductor 412 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 412 is formed concurrently with another component such as a conductor, copper, aluminum, or the like which is a low-resistance metal material may be used.
Note that the conductor 424 can be formed using a material similar to that used for forming the conductor 412 functioning as an electrode of the capacitor.
The insulator 430, the insulator 432, and the insulator 434 are provided over the conductor 424 and the conductor 412. The insulator 430, the insulator 432, and the insulator 434 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Although a three-layer structure is illustrated in the drawings, a single-layer structure, a two-layer structure, or a stacked-layer structure of four or more layers may be used.
For example, a material with high dielectric strength such as silicon oxynitride is preferably used for the insulator 430 and the insulator 434. Furthermore, a high dielectric constant (high-k) material such as aluminum oxide is preferably used for the insulator 432. In the capacitor 400 having the structure, a sufficient capacitance can be provided because of a high dielectric constant (high-k) insulator, and the dielectric strength can be increased and the electrostatic breakdown can be suppressed because of an insulator with high dielectric strength.
The conductor 416 is provided over the conductor 412 with the insulator 430, the insulator 432, and the insulator 434 provided therebetween. Note that the conductor 416 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor 416 is formed concurrently with another component such as a conductor, copper, aluminum, or the like which is a low-resistance metal material may be used.
For example, as illustrated in
That is, a capacitance is formed also on the side surfaces of the conductor 412, so that a capacitance per projected area of a capacitor can be increased. Thus, the semiconductor device can be reduced in area, highly integrated, and miniaturized.
An insulator 450 is provided over the conductor 416 and the insulator 434. The insulator 450 can be formed using a material similar to that used for forming the insulator 320. The insulator 450 covering the capacitor 400 may function as a planarization film that covers a roughness thereunder.
The above is the description of the structure example. With the use of the structure, a change in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including an OS transistor. Furthermore, an OS transistor with a high on-state current can be provided. Furthermore, an OS transistor with a low off-state current can be provided. Furthermore, a semiconductor device with low power consumption can be provided.
Modification Example 1In the transistor 300 illustrated in
The transistor 200 illustrated in
In the semiconductor device illustrated in
In this embodiment, a structure of an oxide semiconductor of one embodiment of the present invention is described.
<Structure of Oxide Semiconductor>An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis-aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and not to have fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.
This means that a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.
<CAAC-OS>First, a CAAC-OS will be described.
A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).
Analysis of a CAAC-OS by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO4 crystal that is classified into the space group R-3m is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in
On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in a direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. When analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector to the sample surface as an axis (φ axis), as shown in
Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4 crystal in a direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) shown in
In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, even in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.
In
In
As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.
The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).
Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. For example, impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources. For example, oxygen vacancy in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source when hydrogen is captured therein.
<nc-OS>
Next, an nc-OS is described.
Analysis of an nc-OS by XRD is described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.
For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of thinned nc-OS including an InGaZnO4 crystal in a direction parallel to the formation surface, a ring-shaped diffraction pattern (a nanobeam electron diffraction pattern) shown in
Furthermore, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed in some cases as shown in
As described above, in the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.
Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).
The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
<a-Like OS>
An a-like OS has a structure between those of the nc-OS and the amorphous oxide semiconductor.
The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation will be described below.
An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.
First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.
It is known that a unit cell of an InGaZnO4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4 in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4 crystal.
In this manner, growth of the crystal part in the a-like OS is sometimes induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.
For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm3 and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3 and lower than 6.3 g/cm3.
Note that in the case where an oxide semiconductor having a certain composition does not exist in a single crystal structure, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be estimated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to estimate the density.
As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked film including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
Embodiment 6In this embodiment, a CPU in which the semiconductor device or memory device described in any of the above embodiments can be used will be described.
An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.
The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 processes an interrupt request from an external input/output device or a peripheral circuit depending on its priority or a mask state. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 depending on the state of the CPU.
The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above circuits.
In the CPU illustrated in
In the CPU illustrated in
In this embodiment, a programmable logic device (PLD) that can be formed using the memory device or semiconductor device described in any of the above embodiments will be described.
A PLD has a structure in which adequate-scale logic circuits (logic blocks, or programmable logic elements) are electrically connected to each other by a routing resource, and the functions of the logic blocks and the connection between the logic blocks can be changed after manufacture. The functions of the logic blocks and the connection between the logic blocks formed using a routing resource are defined by configuration data, and the configuration data is stored in a register included in each logic block or a register included in the routing resource. A register for storing configuration data is hereinafter referred to as a configuration memory.
The transistor 757 has a function of controlling electrical connection between a point A of the wiring 755 and a point C of the wiring 756. The transistor 758 has a function of controlling electrical connection between a point B of the wiring 755 and the point C of the wiring 756. The transistor 759 has a function of controlling electrical connection between the point A of the wiring 755 and a point D of the wiring 756. The transistor 760 has a function of controlling electrical connection between the point B of the wiring 755 and the point D of the wiring 756. The transistor 761 has a function of controlling electrical connection between the point A and the point B of the wiring 755. The transistor 762 has a function of controlling electrical connection between the point C and the point D of the wiring 756.
The switch circuits 752 also have a function of controlling electrical connection between the wiring group 751 and terminals 754 of the PLD 750.
Note that the logic block 740 may further include a multiplexer circuit. The multiplexer circuit can select whether the output signal from the LUT 741 goes through the flip-flop 742.
The type of the flip-flop 742 may be determined by configuration data. Specifically, the flip-flop 742 may have a function of any of a D flip-flop, a T flip-flop, a JK flip-flop, and an RS flip-flop, depending on the configuration data.
The memory circuit or flip-flop included in the logic block 740 can be formed using the semiconductor device or memory device described in any of the above embodiments. With the use of the semiconductor device or memory device described in any of the above embodiments, the logic block 740 can hold data even in a power-off state, leading to a reduction in power consumption.
Embodiment 8The semiconductor device of one embodiment of the present invention can be used for vehicles such as an automobile, a motorcycle, and a bicycle, aircrafts, ships, and the like. The semiconductor device of one embodiment of the present invention can also be used for electronic devices such as a cellular phone, a wristwatch, a portable game machine, a portable data terminal, an e-book reader, a video camera, a digital still camera, and a goggle-type display (head-mounted display).
The sensor portion 805 is configured to acquire information by measuring the surrounding state. For example, a camera, an acceleration sensor, a direction sensor, a pressure sensor, a temperature sensor, a humidity sensor, an illuminance sensor, or a global positioning system (GPS) signal receiving circuit can be used as the sensor portion 805.
For example, when an arithmetic device in the housing 801 determines that the ambient light level measured by an illuminance sensor of the sensor portion 805 is sufficiently higher than the predetermined illuminance, a reflective liquid crystal element is used as a display element of the display portion 803. In the case where the arithmetic device determines that it is dim, an organic EL element is used as a display element of the display portion 803. Thus, image information can be displayed in such a manner that, for example, a reflective display element is used in an environment with strong external light and a self-luminous display element is used in a dim environment. As a result, the power consumption of the electronic device can be reduced.
In this embodiment, application examples of an RF tag that can include the semiconductor device of one embodiment of the present invention will be described with reference to
An RF tag 4000 of one embodiment of the present invention is fixed to a product by being attached to a surface thereof or embedded therein. For example, the RF tag 4000 is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. Since the RF tag 4000 of one embodiment of the present invention can be reduced in size, thickness, and weight, it can be fixed to a product without spoiling the design of the product. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have an identification function by being provided with the RF tag 4000 of one embodiment of the present invention, and the identification function can be utilized to prevent counterfeiting. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag of one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic devices, or the like. Vehicles can also have a higher level of security against theft or the like by being provided with the RF tag of one embodiment of the present invention.
As described above, by using the RF tag of one embodiment of the present invention for each application described in this embodiment, power for operation such as writing or reading of data can be reduced, which results in an increase in the maximum communication distance. Moreover, data can be held for an extremely long period even in the state where power is not supplied; thus, the RF tag can be preferably used for application in which data is not frequently written or read.
In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components. Thus, the terms do not limit the number or order of components. In this specification and the like, a “first” component in one embodiment can be referred to as a “second” component in other embodiments or claims. Furthermore, in this specification and the like, a “first” component in one embodiment can be referred to without the ordinal number in other embodiments or claims.
In this specification and the like, the term such as “electrode” or “wiring” does not limit a function of a component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Furthermore, the term “electrode” or “wiring” can also mean a combination of a plurality of “electrodes” and “wirings” formed in an integrated manner.
In this specification and the like, “voltage” and “potential” can be replaced with each other. The term “voltage” refers to a potential difference from a reference potential. When the reference potential is a ground potential, for example, “voltage” can be replaced with “potential”. The ground potential does not necessarily mean 0 V. Potentials are relative values, and the potential applied to a wiring or the like is changed depending on the reference potential, in some cases.
In this specification and the like, the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film”, and the term “insulating film” can be changed into the term “insulating layer” in some cases.
In this specification and the like, a switch is in a conductive state (on state) or in a non-conductive state (off state) to determine whether current flows therethrough or not. Alternatively, a switch has a function of selecting and changing a current path. Examples of a switch include an electrical switch and a mechanical switch. That is, any element can be used as a switch as long as it can control current, without limitation to a certain element.
Examples of the electrical switch include a transistor (e.g., a bipolar transistor or a MOS transistor), a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a metal-insulator-metal (MIM) diode, a metal-insulator-semiconductor (MIS) diode, or a diode-connected transistor), and a logic circuit in which such elements are combined.
In the case of using a transistor as a switch, an “on state” of the transistor refers to a state in which a source and a drain of the transistor are electrically short-circuited. Furthermore, an “off state” of the transistor refers to a state in which the source and the drain of the transistor are electrically disconnected. In the case where a transistor operates just as a switch, the polarity (conductivity type) of the transistor is not particularly limited to a certain type.
An example of a mechanical switch is a switch formed using a micro electro mechanical systems (MEMS) technology, such as a digital micromirror device (DMD). Such a switch includes an electrode which can be moved mechanically, and operates by controlling conduction and non-conduction in accordance with movement of the electrode.
For example, in this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, another connection relationship is included in the drawings or the texts.
Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).
Examples of the case where X and Y are directly connected include the case where an element that allows an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load) is not connected between X and Y, and the case where X and Y are connected without the element that allows the electrical connection between X and Y provided therebetween.
For example, in the case where X and Y are electrically connected, one or more elements that enable an electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) can be connected between X and Y.
For example, in the case where X and Y are functionally connected, one or more circuits that enable a functional connection between X and Y (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a D/A converter circuit, an A/D converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a step-up circuit or a step-down circuit) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit that can increase signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit; a signal generation circuit; a memory circuit; or a control circuit) can be connected between X and Y. Note that, for example, in the case where a signal output from X is transmitted to Y even when another circuit is interposed between X and Y, X and Y are functionally connected. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
Note that in this specification and the like, an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, in this specification and the like, the explicit description “X and Y are electrically connected” is the same as the description “X and Y are connected”.
For example, any of the following expressions can be used for the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1 and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to one part of Z1 and another part of Z1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to one part of Z2 and another part of Z2 is directly connected to Y.
Examples of the expressions include, “X, Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order”, and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order”. When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.
Other examples of the expressions include, “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1 is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2 is on the third connection path” and “a source (or a first terminal or the like) of a transistor is electrically connected to X at least with a first connection path through Z1, the first connection path does not include a second connection path, the second connection path includes a connection path through which the transistor is provided, a drain (or a second terminal or the like) of the transistor is electrically connected to Y at least with a third connection path through Z2, and the third connection path does not include the second connection path”. Still another example of the expression is “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1 on a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least Z2 on a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor”. When the connection path in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.
Note that these expressions are examples and there is no limitation on the expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, and a layer).
Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film functions as the wiring and the electrode. Thus, “electrical connection” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
Example 1In this example, the transistor 200 in
The transistor 200 was fabricated over a Si wafer.
The insulator 216 was formed using a 120-nm-thick silicon oxide film. The silicon oxide film was formed by a PECVD method.
The conductor 205a was formed using a 5-nm-thick titanium nitride film. The titanium nitride film was formed by a CVD method.
The conductor 205b was formed using a tungsten film. The tungsten film was formed by a CVD method. After the tungsten film was formed, surfaces of the conductors 205a and 205b were planarized by CMP.
The insulator 220 was formed using a 10-nm-thick silicon oxynitride film. The silicon oxynitride film was formed by a PECVD method.
The insulator 222 was formed using a 20-nm-thick hafnium oxide film. The hafnium oxide film was formed by an ALD method.
The insulator 224 was formed using a 30-nm-thick silicon oxynitride film.
The silicon oxynitride film was formed by a PECVD method.
After the insulator 224 was formed, heat treatment at 550° C. was performed in an oxygen atmosphere for one hour.
The oxide semiconductor 230a was formed using a 40-nm-thick In—Ga—Zn oxide film. The oxide semiconductor 230a was formed by a DC sputtering method using a target of an In—Ga—Zn oxide containing In, Ga, and Zn at an atomic ratio of 1:3:4. The sputtering method was performed at a substrate temperature of 200° C. in a mixed gas of argon and oxygen.
The oxide semiconductor 230b was formed using a 20-nm-thick In—Ga—Zn oxide film. The oxide semiconductor 230b was formed by a DC sputtering method using a target of an In—Ga—Zn oxide containing In, Ga, and Zn at an atomic ratio of 1:1:1. The sputtering method was performed at a substrate temperature of 300° C. in a mixed gas of argon and oxygen. The oxide semiconductor 230b was formed using the CAAC-OS film described in the above embodiment.
After the oxide semiconductor 230b was formed, heat treatment at 550° C. was performed in a nitrogen atmosphere for one hour and in an oxygen atmosphere for one hour.
The conductors 240a and 240b were each formed using a 50-nm-thick tungsten film. The tungsten film was formed by a sputtering method.
The oxide semiconductor 230c was formed using a 5-nm-thick In—Ga—Zn oxide film. The oxide semiconductor 230c was formed by a DC sputtering method using a target of an In—Ga—Zn oxide containing In, Ga, and Zn at an atomic ratio of 1:3:2. The sputtering method was performed at a substrate temperature of 200° C. in a mixed gas of argon and oxygen.
The insulator 250 was formed using a 13-nm-thick silicon oxynitride film. The silicon oxynitride film was formed by a PECVD method.
The conductor 260 was formed using a stack including a 30-nm-thick titanium nitride film and a 135-nm-thick tungsten film. The titanium nitride film and the tungsten film were formed by a sputtering method.
The insulator 280 was formed using a stack including a 40-nm-thick aluminum oxide film and an 800-nm-thick silicon oxide film. The 40-nm-thick aluminum oxide film was formed by a sputtering method until a thickness of 30 nm was reached, and then by an ALD method until a thickness of 40 nm was reached. Note that after the aluminum oxide film was formed, heat treatment at 400° C. was performed in an oxygen atmosphere for one hour. The silicon oxide film was formed by a PECVD method. After the silicon oxide film was formed, planarization was performed by a CMP method.
The results in
The results in
The above results show that the channel lengths of the transistors M11, M12, and M14 used in the voltage holding circuit in Embodiment 1 are preferably long. In particular, the channel lengths are preferably 10 μm or longer.
Example 2In this example, device simulation shows that the cutoff current of a transistor including an In—Ga—Zn oxide semiconductor in a channel formation region can be low when the ratio of the number of Ga atoms to the number of In atoms is high.
The transistor structure assumed in this device simulation is illustrated in
The simulation is performed using device simulation software “Atlas” produced by Silvaco, Inc. The parameters assumed in this device simulation are listed in Table 3. The semiconductor SEM is assumed to be an In—Ga—Zn oxide semiconductor.
In this example, three types of transistors whose semiconductors SEM (IGZO(111), IGZO(134), and IGZO(164)) have different physical property values are assumed.
IGZO(111) is assumed to be a semiconductor layer formed by a sputtering method using an In—Ga—Zn oxide semiconductor target having a ratio of In:Ga:Zn=1:1:1. The bandgap is assumed to be 3.2 eV.
IGZO(134) is assumed to be a semiconductor layer formed by a sputtering method using an In—Ga—Zn oxide semiconductor target having a ratio of In:Ga:Zn=1:3:4. The bandgap is assumed to be 3.4 eV.
IGZO(164) is assumed to be a semiconductor layer formed by a sputtering method using an In—Ga—Zn oxide semiconductor target having a ratio of In:Ga:Zn=1:6:4. The bandgap is assumed to be 3.8 eV.
The calculation results are shown in
The calculation results in
This application is based on Japanese Patent Application serial no. 2015-247680 filed with Japan Patent Office on Dec. 18, 2015, the entire contents of which are hereby incorporated by reference.
Claims
1. A semiconductor device comprising:
- a first transistor;
- a second transistor; and
- a circuit,
- wherein the first transistor comprises a first gate and a second gate,
- wherein the first transistor comprises a first semiconductor in a channel formation region,
- wherein the first gate and the second gate overlap with each other in a region with the first semiconductor between the first gate and the second gate,
- wherein the second transistor comprises a second semiconductor in a channel formation region,
- wherein a gate of the second transistor is electrically connected to a first terminal of the second transistor,
- wherein the first terminal of the second transistor is electrically connected to the second gate,
- wherein a second terminal of the second transistor is electrically connected to the circuit, and
- wherein the circuit is configured to generate a negative potential.
2. The semiconductor device according to claim 1, wherein the second semiconductor has a wider bandgap than the first semiconductor.
3. The semiconductor device according to claim 1,
- wherein the first semiconductor is a first oxide semiconductor,
- wherein the second semiconductor is a second oxide semiconductor,
- wherein the first oxide semiconductor comprises In and M,
- wherein M is Ga, Al, B, Si, Ti, Zr, La, Ce, Y, Hf, Ta, Nb, or Sc,
- wherein the second oxide semiconductor comprises In and M, and
- wherein a ratio of the number of M atoms to the number of In atoms in the second oxide semiconductor is higher than a ratio of the number of M atoms to the number of In atoms in the first oxide semiconductor.
4. A memory device comprising the semiconductor device according to claim 1.
5. An electronic device comprising:
- the semiconductor device according to claim 1; and
- a display device, a microphone, a speaker, an operation key, or a housing.
6. A semiconductor device comprising:
- a first transistor;
- a second transistor;
- a third transistor;
- a capacitor; and
- a circuit,
- wherein the first transistor comprises a first gate and a second gate,
- wherein the first transistor comprises a first semiconductor in a channel formation region,
- wherein the first gate and the second gate overlap with each other in a region with the first semiconductor between the first gate and the second gate,
- wherein the second transistor comprises a second semiconductor in a channel formation region,
- wherein a gate of the second transistor is electrically connected to a gate of the third transistor,
- wherein the gate of the third transistor is electrically connected to a first terminal of the capacitor,
- wherein a first terminal of the second transistor is electrically connected to the second gate,
- wherein a second terminal of the second transistor is electrically connected to the circuit, and
- wherein the circuit is configured to generate a negative potential.
7. The semiconductor device according to claim 6, wherein a bandgap of the second semiconductor is greater than or equal to 2.2 eV.
8. The semiconductor device according to claim 7, wherein the second semiconductor has a wider bandgap than the first semiconductor.
9. The semiconductor device according to claim 6,
- wherein the first semiconductor is a first oxide semiconductor, and
- wherein the second semiconductor is a second oxide semiconductor.
10. The semiconductor device according to claim 9,
- wherein the first oxide semiconductor comprises In and M,
- wherein M is Ga, Al, B, Si, Ti, Zr, La, Ce, Y, Hf, Ta, Nb, or Sc,
- wherein the second oxide semiconductor comprises In and M, and
- wherein a ratio of the number of M atoms to the number of In atoms in the second oxide semiconductor is higher than a ratio of the number of M atoms to the number of In atoms in the first oxide semiconductor.
11. A memory device comprising the semiconductor device according to claim 1.
12. An electronic device comprising:
- the semiconductor device according to claim 1; and
- a display device, a microphone, a speaker, an operation key, or a housing.
13. A semiconductor device comprising:
- a first transistor;
- a second transistor; and
- a circuit,
- wherein the first transistor comprises a first gate and a second gate,
- wherein the first transistor comprises a first semiconductor in a channel formation region,
- wherein the first gate and the second gate overlap with each other in a region with the first semiconductor between the first gate and the second gate,
- wherein the second transistor comprises a third gate and a fourth gate,
- wherein the second transistor comprises a second semiconductor in a channel formation region,
- wherein the third gate and the fourth gate overlap with each other in a region with the second semiconductor between the third gate and the fourth gate,
- wherein the fourth gate and the second semiconductor overlap with each other in a region with a charge accumulation layer between the fourth gate and the second semiconductor,
- wherein the third gate is electrically connected to a first terminal of the second transistor,
- wherein the first terminal of the second transistor is electrically connected to the second gate,
- wherein a second terminal of the second transistor is electrically connected to the circuit, and
- wherein the circuit is configured to generate generating a negative potential.
14. The semiconductor device according to claim 13, wherein the second semiconductor has a wider bandgap than the first semiconductor.
15. The semiconductor device according to claim 13,
- wherein the first semiconductor is a first oxide semiconductor,
- wherein the second semiconductor is a second oxide semiconductor,
- wherein the first oxide semiconductor comprises In and M,
- wherein M is Ga, Al, B, Si, Ti, Zr, La, Ce, Y, Hf, Ta, Nb, or Sc,
- wherein the second oxide semiconductor comprises In and M, and
- wherein a ratio of the number of M atoms to the number of In atoms in the second oxide semiconductor is higher than a ratio of the number of M atoms to the number of In atoms in the first oxide semiconductor.
16. A memory device comprising the semiconductor device according to claim 13.
17. An electronic device comprising:
- the semiconductor device according to claim 13; and
- a display device, a microphone, a speaker, an operation key, or a housing.
Type: Application
Filed: Dec 15, 2016
Publication Date: Jun 22, 2017
Patent Grant number: 10522688
Inventors: Kiyoshi KATO (Atsugi), Tomoaki ATSUMI (Hadano), Shunpei YAMAZAKI (Takyo), Haruyuki BABA (Isehara), Shinpei MATSUDA (Atsugi)
Application Number: 15/380,502
