Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240250181
    Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
    Type: Application
    Filed: March 5, 2024
    Publication date: July 25, 2024
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Keisuke MURAYAMA
  • Publication number: 20240250184
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Publication number: 20240250182
    Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.
    Type: Application
    Filed: April 2, 2024
    Publication date: July 25, 2024
    Inventors: Tatsuya ONUKI, Kiyoshi KATO, Tomoaki ATSUMI, Shunpei YAMAZAKI
  • Publication number: 20240250183
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Inventors: Tatsuya HONDA, Masashi TSUBUKU, Yusuke NONAKA, Takashi SHIMAZU, Shunpei YAMAZAKI
  • Patent number: 12046679
    Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.
    Type: Grant
    Filed: August 3, 2023
    Date of Patent: July 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kenichi Okazaki, Yukinori Shima, Shinpei Matsuda, Haruyuki Baba, Ryunosuke Honda
  • Patent number: 12048207
    Abstract: A first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: July 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masakatsu Ohno, Hiroki Adachi, Satoru Idojiri, Koichi Takeshima
  • Patent number: 12046604
    Abstract: A display device is manufactured with five photolithography steps: a step of forming a gate electrode, a step of forming a protective layer for reducing damage due to an etching step or the like, a step of forming a source electrode and a drain electrode, a step of forming a contact hole, and a step of forming a pixel electrode. The display device includes a groove portion which is formed in the step of forming the contact hole and separates the semiconductor layer.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: July 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Publication number: 20240243204
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor, With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Application
    Filed: November 29, 2023
    Publication date: July 18, 2024
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
  • Patent number: 12040009
    Abstract: A sense amplifier and a semiconductor device which are less likely to be influenced by a variation in transistor characteristics and their operation methods are provided. An amplifier circuit in a sense amplifier includes a first circuit and a second circuit, each including an inverter, a first transistor, a second transistor, and a capacitor. A first terminal and a second terminal of the capacitor are electrically connected to a first bit line and an input terminal of the inverter, respectively. The first transistor and the second transistor function as a switch that switches conduction and non-conduction between the input terminal and an output terminal of the inverter, and a switch that switches conduction and non-conduction between the output terminal of the inverter and the second bit line, respectively. The first circuit and the second circuit are initialized by a potential obtained when conduction is established between the input terminal and the output terminal of the inverter.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura
  • Patent number: 12041366
    Abstract: An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeya Hirose, Seiichi Yoneda, Hiroki Inoue, Takayuki Ikeda, Shunpei Yamazaki
  • Patent number: 12040653
    Abstract: The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 16, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Takanori Matsuzaki, Kei Takahashi, Mayumi Mikami, Shunpei Yamazaki
  • Patent number: 12040042
    Abstract: An object of one embodiment of the present invention is to propose a memory device in which a period in which data is held is ensured and memory capacity per unit area can be increased. In the memory device of one embodiment of the present invention, bit lines are divided into groups, and word lines are also divided into groups. The word lines assigned to one group are connected to the memory cell connected to the bit lines assigned to the one group. Further, the driving of each group of bit lines is controlled by a dedicated bit line driver circuit of a plurality of bit line driver circuits. In addition, cell arrays are formed on a driver circuit including the above plurality of bit line driver circuits and a word line driver circuit. The driver circuit and the cell arrays overlap each other.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: July 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Publication number: 20240233677
    Abstract: To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n?3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.
    Type: Application
    Filed: January 4, 2024
    Publication date: July 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroyuki Miyake, Kouhei Toyotaka, Shunpei Yamazaki
  • Publication number: 20240234423
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Application
    Filed: December 13, 2023
    Publication date: July 11, 2024
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20240237445
    Abstract: One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential can be supplied stably is provided. Further, a bendable display device to which a signal or a power supply potential can be supplied stably is provided. The display device includes, over a flexible substrate, a display portion, a plurality of connection terminals to which a signal from an outside can be input, and a plurality of wirings. One of the plurality of wirings electrically connects one of the plurality of connection terminals to the display portion. The one of the plurality of wirings includes a first portion including a plurality of separate lines and a second portion in which the plurality of lines converge.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Shunpei YAMAZAKI, Kensuke YOSHIZUMI
  • Publication number: 20240237464
    Abstract: A high-definition or high-resolution display apparatus is provided. The display apparatus includes a first light-emitting device, a second light-emitting device, a first insulating layer, and a second insulating layer. The first light-emitting device includes a first pixel electrode, a first light-emitting layer over the first pixel electrode, and a common electrode over the first light-emitting layer. The second light-emitting device includes a second pixel electrode, a second light-emitting layer over the second pixel electrode, and the common electrode over the second light-emitting layer. Each of an end portion of the first pixel electrode and an end portion of the second pixel electrode is covered with the first insulating layer. The second insulating layer is positioned over the first insulating layer. The second insulating layer covers each of a side surface of the first light-emitting layer and a side surface of the second light-emitting layer.
    Type: Application
    Filed: February 9, 2022
    Publication date: July 11, 2024
    Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Daiki NAKAMURA, Rai SATO
  • Patent number: 12035061
    Abstract: An imaging device having a memory function is provided. Alternatively, an imaging device suitable for taking images of a moving object is provided. The imaging device includes a first to third layers; the second layer is provided between the first and the third layer; the first layer includes a photoelectric conversion device; the second layer includes a first and a second circuit; the third layer includes a third and a fourth circuit; the first circuit and the photoelectric conversion device have a function of generating imaging data; the third circuit has a function of reading the imaging data; the second circuit has a function of storing the imaging data read by the third circuit; the fourth circuit has a function of reading the imaging data stored in the second circuit; and the first circuit and the second circuit include a transistor including a metal oxide in a channel formation region.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda
  • Patent number: 12034064
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 12035487
    Abstract: A light-emitting device can be folded in such a manner that a flexible light-emitting panel is supported by a plurality of housings which are provided spaced from each other and the light-emitting panel is bent so that surfaces of adjacent housings are in contact with each other. Furthermore, in the light-emitting device, in which part or the whole of the housings have magnetism, the two adjacent housings can be fixed to each other by a magnetic force when the light-emitting device is used in a folded state.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Yasuhiro Jinbo, Shunpei Yamazaki
  • Patent number: 12033694
    Abstract: A semiconductor device that restores degraded data is provided. The semiconductor device includes a first circuit, a storage portion, and an arithmetic portion. The first circuit includes a current source and a first switch. The storage portion includes a first transistor and a first capacitor. The arithmetic portion includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. When data retained in the arithmetic portion is restored, the first transistor is turned on, and the data retained in the storage portion is supplied to the control terminal of the first switch through the first transistor.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: July 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takayuki Ikeda, Yoshiyuki Kurokawa