Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210233769
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A metal oxide is formed over a substrate by the steps of: introducing a first precursor into a chamber in which the substrate is provided; introducing a first oxidizer after the introduction of the first precursor; introducing a second precursor after the introduction of the first oxidizer; and introducing a second oxidizer after the introduction of the second precursor.
    Type: Application
    Filed: May 31, 2019
    Publication date: July 29, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tetsuya KAKEHATA, Yuji EGI, Yasuhiro JINBO, Yujiro SAKURADA
  • Publication number: 20210230740
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tetsunori MARUYAMA, Yuki IMOTO, Hitomi SATO, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Takashi SHIMAZU
  • Publication number: 20210234112
    Abstract: A novel light-emitting device is provided. A light-emitting device or a display device having high display quality is provided. An electronic device including a display portion with high display quality is provided. Provided is a light-emitting device including a first pixel which includes a first light-emitting element and a light-scattering layer; and a second pixel which includes a second light-emitting element and a first color conversion layer, in which an emission center substance in each of the first light-emitting element and the second light-emitting element is an organic compound, the light-scattering layer includes a first substance that scatters light emitted from the first light-emitting element, the first color conversion layer includes a second substance that emits light by absorbing light emitted from the second light-emitting element, and the first light-emitting element and the second light-emitting element have a microcavity structure.
    Type: Application
    Filed: May 31, 2019
    Publication date: July 29, 2021
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Shunpei YAMAZAKI
  • Patent number: 11075255
    Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a display region, and the display region includes a first group of pixels, a second group of pixels, a third group of pixels, a fourth group of pixels, a first scan line, a second scan line, a first signal line, and a second signal line. The first group of pixels include a first pixel and are arranged in a row direction. The second group of pixels include a second pixel and are arranged in the row direction. The third group of pixels include a first pixel and are arranged in a column direction that intersects the row direction. The fourth group of pixels include a second pixel and are arranged in the column direction. The first signal line is electrically connected to the third group of pixels and the second signal line is electrically connected to the fourth group of pixels.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kei Takahashi, Hideaki Shishido, Shunpei Yamazaki
  • Patent number: 11074890
    Abstract: To provide a display device that achieves both smooth input and a high detection sensitivity on a touch sensor unit. The display device includes a display unit and the touch sensor unit. The display device has three operation modes: normal display in which the entire display region is rewritten, partial IDS driving in which part of the display region is rewritten, and IDS driving in which the entire display region is not rewritten. The detection operation by the touch sensor unit is performed at a time different from the time of performing the rewriting operation of the display region, so that a high detection sensitivity is achieved. Furthermore, a period of performing the detection operation in each of the partial IDS driving and the IDS driving is set longer than a period of performing the detection operation in the normal display, which enables smooth input.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Shunpei Yamazaki
  • Patent number: 11074953
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Shunpei Yamazaki
  • Patent number: 11075232
    Abstract: A display device in which a peripheral circuit portion has high operation stability is provided. The display device includes a first substrate and a second substrate. A first insulating layer is provided over a first surface of the first substrate. A second insulating layer is provided over a first surface of the second substrate. The first surface of the first substrate and the first surface of the second substrate face each other. An adhesive layer is provided between the first insulating layer and the second insulating layer. A protective film in contact with the first substrate, the first insulating layer, the adhesive layer, the second insulating layer, and the second substrate is formed in the vicinity of a peripheral portion of the first substrate and the second substrate.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiharu Hirakata, Takashi Hamada, Kohei Yokoyama, Yasuhiro Jinbo, Tetsuji Ishitani, Daisuke Kubota
  • Patent number: 11074962
    Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Takanori Matsuzaki, Kiyoshi Kato, Shunpei Yamazaki
  • Patent number: 11075300
    Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ? or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ? or less.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 11075075
    Abstract: Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 27, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20210226060
    Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.
    Type: Application
    Filed: February 23, 2021
    Publication date: July 22, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Publication number: 20210225882
    Abstract: A highly flexible display device and a method for manufacturing the display device are provided. A transistor including a light-transmitting semiconductor film, a capacitor including a first electrode, a second electrode, and a dielectric film between the first electrode and the second electrode, and a first insulating film covering the semiconductor film are formed over a flexible substrate. The capacitor includes a region where the first electrode and the dielectric film are in contact with each other, and the first insulating film does not cover the region.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20210226061
    Abstract: It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20210227061
    Abstract: A light-emitting device or a display device that is less likely to be broken is provided. Provided is a light-emitting device including an element layer and a substrate over the element layer. At least a part of the substrate is bent to the element layer side. The substrate has a light-transmitting property and a refractive index that is higher than that of the air. The element layer includes a light-emitting element that emits light toward the substrate side. Alternatively, provided is a light-emitting device including an element layer and a substrate covering a top surface and at least one side surface of the element layer. The substrate has a light-transmitting property and a refractive index that is higher than that of the air. The element layer includes a light-emitting element that emits light toward the substrate side.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 22, 2021
    Inventors: Shunpei YAMAZAKI, Yoshiharu HIRAKATA, Tomoya AOYAMA, Akihiro CHIDA
  • Publication number: 20210226063
    Abstract: A semiconductor device that stably operates even at high temperature is provided. The semiconductor device includes a metal oxide, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The metal oxide includes a first region, a second region, and a third region. The first region overlaps with the first conductive layer. The second region overlaps with the second conductive layer. The third region overlaps with the third conductive layer with the insulating layer interposed therebetween. The value of the ratio of the carrier concentration in the first region to the carrier concentration in the third region is 100 or more. The value of the ratio of the carrier concentration in the second region to the carrier concentration in the third region is 100 or more.
    Type: Application
    Filed: August 1, 2019
    Publication date: July 22, 2021
    Inventors: Shunpei YAMAZAKI, Naoki OKUNO, Ryunosuke HONDA
  • Publication number: 20210226062
    Abstract: A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M.
    Type: Application
    Filed: June 25, 2019
    Publication date: July 22, 2021
    Inventors: Shunpei YAMAZAKI, Haruyuki BABA, Naoki OKUNO, Yoshihiro KOMATSU, Toshikazu OHNO
  • Patent number: 11066739
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Patent number: 11071224
    Abstract: A novel, highly convenient or reliable functional panel is provided. A novel, highly convenient or reliable method for manufacturing a functional panel is provided. The functional panel includes a first base; a second base having a region overlapping with the first base; a bonding layer that bonds the first base to the second base; and an insulating layer in contact with the first base, the second base, and the bonding layer. With this structure, an opening which is formed easily in a region where the bonding layer is in contact with the first base or the second base can be filled with the insulating layer, which can prevent impurities from being diffused into the functional layer located in a region surrounded by the first base, the second base, and the bonding layer that bonds the first base to the second base.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kohei Yokoyama, Yoshiharu Hirakata
  • Patent number: 11069717
    Abstract: To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: July 20, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20210217898
    Abstract: It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 15, 2021
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinari Higaki, Masayuki SAKAKURA, Shunpei YAMAZAKI