Patents by Inventor Shunpei Yamazaki

Shunpei Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200251547
    Abstract: A first organic resin layer is formed over a first substrate; a first insulating film is formed over the first organic resin layer; a first element layer is formed over the first insulating film; a second organic resin layer is formed over a second substrate; a second insulating film is formed over the second organic resin layer; a second element layer is formed over the second insulating film; the first substrate and the second substrate are bonded; a first separation step in which adhesion between the first organic resin layer and the first substrate is reduced; the first organic resin layer and a first flexible substrate are bonded with a first bonding layer; a second separation step in which adhesion between the second organic resin layer and the second substrate is reduced; and the second organic resin layer and a second flexible substrate are bonded with a second bonding layer.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Inventors: Shunpei YAMAZAKI, Masakatsu OHNO, Hiroki ADACHI, Satoru IDOJIRI, Koichi TAKESHIMA
  • Publication number: 20200251685
    Abstract: An object of one embodiment of the present invention is to provide a more convenient highly reliable light-emitting device which can be used for a variety of applications. Another object of one embodiment of the present invention is to manufacture, without complicating the process, a highly reliable light-emitting device having a shape suitable for its intended purpose. In a manufacturing process of a light-emitting device, a light-emitting panel is manufactured which is at least partly curved by processing the shape to be molded after the manufacture of an electrode layer and/or an element layer, and a protective film covering a surface of the light-emitting panel which is at least partly curved is formed, so that a light-emitting device using the light-emitting panel has a more useful function and higher reliability.
    Type: Application
    Filed: April 16, 2020
    Publication date: August 6, 2020
    Inventors: Shunpei YAMAZAKI, Kaoru HATANO
  • Publication number: 20200250521
    Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.
    Type: Application
    Filed: August 28, 2018
    Publication date: August 6, 2020
    Inventors: Takahiko ISHIZU, Takayuki IKEDA, Atsuo ISOBE, Atsushi MIYAGUCHI, Shunpei YAMAZAKI
  • Patent number: 10734530
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 10734413
    Abstract: A novel metal oxide is provided. The metal oxide has a plurality of energy gaps, and includes a first region having a high energy level of a conduction band minimum and a second region having an energy level of a conduction band minimum lower than that of the first region. The second region comprises more carriers than the first region. A difference between the energy level of the conduction band minimum of the first region and the energy level of the conduction band minimum of the second region is 0.2 eV or more. The energy gap of the first region is greater than or equal to 3.3 eV and less than or equal to 4.0 eV and the energy gap of the second region is greater than or equal to 2.2 eV and less than or equal to 2.9 eV.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Haruyuki Baba
  • Publication number: 20200243514
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a first conductor and a second insulator over a first insulator; a third insulator over the first conductor and the second insulator; a fourth insulator over the third insulator; a first oxide over the fourth insulator; a second oxide and a third oxide over the first oxide; a second conductor in contact with a top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the second oxide, and a top surface of the second oxide; a third conductor in contact with the top surface of the third insulator, a side surface of the fourth insulator, a side surface of the first oxide, a side surface of the third oxide, and a top surface of the third oxide; a fourth oxide over the first oxide; a fifth insulator over the fourth oxide; and a fourth conductor over the fifth insulator.
    Type: Application
    Filed: November 26, 2019
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tatsuya ONUKI, Katsuaki TOCHIBAYASHI
  • Publication number: 20200243689
    Abstract: Provided are a transistor which has electrical characteristics requisite for its purpose and uses an oxide semiconductor layer and a semiconductor device including the transistor. In the bottom-gate transistor in which at least a gate electrode layer, a gate insulating film, and the semiconductor layer are stacked in this order, an oxide semiconductor stacked layer including at least two oxide semiconductor layers whose energy gaps are different from each other is used as the semiconductor layer. Oxygen and/or a dopant may be added to the oxide semiconductor stacked layer.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Shunpei YAMAZAKI, Satoshi SHINOHARA
  • Publication number: 20200243654
    Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle ?1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle ?2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Daisuke Kawae
  • Publication number: 20200243686
    Abstract: An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: Shunpei YAMAZAKI, Motoki NAKASHIMA, Tatsuya HONDA
  • Publication number: 20200243685
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device which includes a first insulator provided over a substrate; an oxide provided over the first insulator; a second insulator provided over the oxide; a conductor provided over the second insulator; a third insulator provided in contact with a side surface of the second insulator and a side surface of the conductor; a fourth insulator provided in contact with at least a top surface of the oxide and in contact with a side surface of the third insulator and a top surface of the conductor; a fifth insulator provided over the fourth insulator; a sixth insulator provided over the fifth insulator; and a seventh insulator provided over the sixth insulator, in which the sixth insulator contains oxygen and the sixth insulator and the first insulator include a region where the sixth insulator and the first insulator are in contact with each other.
    Type: Application
    Filed: February 23, 2018
    Publication date: July 30, 2020
    Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Hajime KIMURA
  • Publication number: 20200243626
    Abstract: A flexible input/output device and an input/output device having high resistance to repeated bending are provided. The input/output device includes a first flexible substrate, a first insulating layer over the first substrate, a first transistor over the first insulating layer, a light-emitting element over and electrically connected to the first transistor and including an EL layer between first and second electrodes, a first bonding layer over the light-emitting element, a sensing element and a second transistor over the first bonding layer and electrically connected to each other, a second insulating layer over the sensing element and the second transistor, and a second flexible substrate over the second insulating layer. In the input/output device, B/A is greater than or equal to 0.7 and less than or equal to 1.7, where A is a thickness between the EL layer and the first insulating layer and B is a thickness between the EL layer and the second insulating layer.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo EGUCHI, Shunpei YAMAZAKI
  • Publication number: 20200241624
    Abstract: A method for operating an electronic device with lower power consumption is provided. The electronic device includes a display device and a touch sensor. In the case where the touch sensor senses no touch, the touch sensor is brought into a resting state or operated so as to perform a sensing operation at a reduced drive frequency. Also in the case where the touch sensor constantly senses touches and an image on the display device is not changed, the touch sensor is brought into the resting state or operated so as to perform the sensing operation at a reduced drive frequency.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Yuji IWAKI, Shunpei YAMAZAKI
  • Patent number: 10727465
    Abstract: To provide a novel structure of a separator in a secondary battery. A nonaqueous secondary battery includes a positive electrode, a negative electrode, an electrolyte solution, a first separator, and a second separator. The first separator and the second separator are provided between the positive electrode and the negative electrode. The first separator is provided with a first pore, the second separator is provided with a second pore, and the size of the first pore is different from the size of the second pore. Furthermore, the proportion of the volume of the first pores in the first separator is different from the proportion of the volume of the second pores in the second separator.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10725502
    Abstract: An electronic device includes a housing and a display panel. The housing includes a flat surface, a first side surface including a curved surface, second and third side surfaces adjacent to the first side surface and including a curved surface, and a fourth side surface opposite to the first side surface and including a curved surface. The display panel includes a first region overlapping with the flat surface, a second region overlapping with the first side surface and including a curved surface, a third region overlapping with the second side surface and including a curved surface, and a fourth region overlapping with the third side surface and including a curved surface.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Shunpei Yamazaki
  • Patent number: 10727355
    Abstract: A semiconductor device includes first and second insulators over a substrate, a semiconductor over the second insulator, first and second conductors over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor and the second conductor. The semiconductor includes first, second, and third regions. The first region overlaps with the third conductor with the third insulator and the fourth insulator positioned therebetween. The second region overlaps with the third conductor with the first conductor, the fourth insulator, and the fifth insulator positioned therebetween. The third region overlaps with the third conductor with the second conductor, the fourth insulator, and the fifth insulator positioned therebetween. The fourth insulator is in contact with a side surface of the fifth insulator in a region overlapping with the semiconductor.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10727356
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; a first oxide over the first insulator; a second oxide in contact with at least a portion of the top surface of the first oxide; a second insulator over the second oxide; a first conductor over the second insulator; a second conductor over the first conductor; a third insulator over the second conductor; a fourth insulator in contact with side surfaces of the second insulator, the first conductor, the second conductor, and the third insulator; and a fifth insulator in contact with the top surface of the second oxide and a side surface of the fourth insulator. The top surface of the fourth insulator is substantially aligned with the top surface of the third insulator.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20200235137
    Abstract: To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20200235136
    Abstract: To provide a novel resistor. To provide a display device having a novel structure that can improve its reliability. To provide a display device having a novel structure that can reduce electrostatic discharge damages. The resistor includes a semiconductor layer and an insulating layer formed over the semiconductor layer, and the semiconductor layer is an oxide represented by an In-M-Zn oxide that contains at least indium (In), zinc (Zn), and M (M is a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) and the insulating layer contains at least hydrogen.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20200235100
    Abstract: A semiconductor device having high frequency characteristics and high reliability is provided. Part of metal elements included in the oxide semiconductor including indium is replaced with cerium (Ce). When indium (In) included in the oxide semiconductor is replaced with cerium, electrons serving as carriers are released. Thus, by adjusting the ratio of cerium included in the oxide semiconductor, the carrier density of the oxide semiconductor can be controlled. In the case where the transistor is used for a memory element or the like, a cerium atom may be greater than or equal to 0.01 atomic % and less than or equal to 1.0 atomic % of metal atoms included in the oxide semiconductor.
    Type: Application
    Filed: November 15, 2018
    Publication date: July 23, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Tomonori NAKAYAMA, Haruyuki BABA
  • Patent number: 10720532
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa