VERTICAL TRANSISTOR AND THE FABRICATION METHOD
A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.
The present application is a divisional application of the U.S. application Ser. No. 15/003,809 filed on Jan. 22, 2016, which claims the priority to Chinese Patent Applications No. 201510703700.1, filed with the Chinese State Intellectual Property Office on Oct. 26, 2015, which is incorporated herein by reference in its entirety.
BACKGROUNDAs a typical representative of third-generation semiconductor materials, wide-band gap semiconductors, including GaN, possess a plurality of outstanding performances capabilities which silicon (Si) materials lack. GaN is an excellent semiconductor material for high-frequency, high-voltage, high-temperature, and high-power applications, with great prospects for application in civil and military fields. Due to advances in GaN technology, especially the gradual maturity and commercialization of large-diameter silicon-based GaN epitaxial technology, the technology of GaN power semiconductors is expected to be a technical solution of high-performance and low success rate. Thus the GaN power devices have drawn the attention of famous international semiconductor manufacturers and research institutes.
SUMMARYThe present invention aims to provide a vertical transistor and its fabrication method. The vertical transistor is a GaN junction-less power transistor, reducing the power consumption of the transistor.
To solve the above technical problem, the present invention is a vertical transistor, comprising: a first surface and a second surface opposite to said first surface; a drift region of the first doping type and said drift region being located between said first surface and the second surface; at least one source region of said first doping type and the source region being located between said drift region and said first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, with a gate provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer located between said gate electrode and said drift region, a second dielectric layer being positioned between said gate electrode and said second surface.
Optionally, it also includes the source electrode on said first surface and the drain electrode on said second surface.
Optionally, said first doping type is N-type.
Optionally, the drift region is N-type doped GaN, with a thickness of 2-50 μm.
Optionally, the source region is the heavily doped N-type GaN and said drain region is heavily doped N-type GaN.
Optionally, the gate electrode is one of Ti, TiN, Ta, TaN, W, Al, Cu, Ag, Ni, Au, Cr and polycrystalline silicon.
Optionally, the gate dielectric layer is silicon oxide and said silicon oxide is 2-50 nm thick.
Optionally, the first dielectric layer is one of silicon oxide, SiON or GaN. Said first dielectric layer is 20-100 nm thick.
Optionally, the second dielectric layer is one of silicon oxide, SiON or GaN. Said second dielectric layer is 20-100 nm thick.
Accordingly, the present invention also provides a method for preparing a vertical transistor comprising: providing a patterned semiconductor substrate; forming a first dielectric layer on one portion of the patterned semiconductor substrate and forming a source region on the remaining portion of patterned semiconductor substrate, said source region having the first doping type; forming a drift layer and the drain region film layer, the drift layer covering the first dielectric layer and the drain region, said drain region film layer overlaying said drift layer, said drift layer and drain region film layer having the first doping type; etching said drain region film layer and said drift layer to form a trench, the trench exposing the drift layer, the remaining drift layer forming the drift region, the remaining drain region film layer forming a drain region; forming the gate dielectric layer and the gate electrode, the gate dielectric layer overlaying the bottom and side walls of the trench, said gate electrode overlaying the gate dielectric layer and filling some portions of said trench; forming the second dielectric layer, said second dielectric layer overlaying said gate electrode, and filling the remaining portion of the trench.
Optionally, the steps to form said gate dielectric layer and gate electrode comprise: forming a dielectric layer and an electrode film layer, the dielectric layer covering the bottom and side walls of the trench and the drain region, said electrode film layer overlaying said dielectric film layer; planarizing the electrode film layer, the electrode layer is set flush with the dielectric film layer; etching said dielectric film layer to form a gate dielectric layer, said gate dielectric layer exposing said drain region; removing some portions of the electrode film layer to form the gate electrode.
Optionally, they further comprise forming a drain electrode, the drain electrode overlaying the second dielectric layer, said gate dielectric layer and said drain region; removing the patterned semiconductor substrate; forming a source electrode, said source electrode overlaying the first dielectric layer and the source region.
Optionally, the surface of the patterned semiconductor substrate is provided with a hemispherical or polygonal pattern.
The present invention provides a vertical transistor comprising a source region, a drift region, a drain region and a gate electrode, wherein the source region, the drain region and the drift region have the first doping type, so that the transistor is a junction-less transistor, thereby reducing power consumption of the transistor. Moreover, the voltage applied to the gate is used to control the passage of carriers in the drift region into the depletion region between gates, so as control the switch of transistor.
The vertical transistor and its fabrication method are described in more detail in conjunction with schematic views as follows. Wherein the preferred embodiment of the present invention is illustrated, it should be understood that those skilled in the art may modify the invention and may still realize the advantageous effects of the invention. Thus, the following description should be understood to be widely known by the skills in the art and should not be regarded as a limitation of the present invention.
The core idea of the present invention is to provide a vertical transistor, comprising: a first surface and a second surface opposite to the first surface; a drift region with the first doping type, said drift region is located between said first surface and the second surface; at least one source region with said first doping type and the source region is located between said drift region and said first surface, with the first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region is located between said drift region and said second surface, with a gate provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer located between said gate electrode and said drift region, the second dielectric layer is positioned between said gate electrode and said second surface. In the present invention, the source region, drain region and drift region all have the first doping type so that the transistor is the junction-less power transistor, thereby reducing the power consumption of the transistor.
The vertical transistor and its fabrication method in the present invention are described with reference to the drawings below.
Referring to
In addition, the vertical transistor further comprises a source electrode 290 on the first surface 201 and a drain electrode 280 on the second surface 202. The source electrode 290 is of Ti, Ni, Al, or Au. The thickness of the source electrode 290 is 50-200 nm. The drain electrode 280 is of Ti, Ni, Al, or Au. The thickness of the drain electrode 280 is 50-200 nm.
Accordingly, the present invention also provides a method for preparing a vertical transistor.
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The source region 220, the drift region 230, and drain region 240 in the vertical transistor of the present invention all have the first doping type and are N-type doped GaN. As a junction-less power transistor, it can be used to reduce power consumption. Furthermore, due to the contact of metal-oxide-semiconductor formed between the gate electrode 260 and the drift region 230 as well as the work function difference between GaN and the metal, a depletion region is formed between the gate dielectric layers 250. When the depletion region runs through the region between the gate dielectric layers 250, carriers fail to pass through them. However the application of a voltage on the gate enables carriers to pass through regions between the gate dielectric layers 250. The voltage is Vt, the threshold voltage of the vertical transistor, so that the vertical transistor of the present invention can control the switch of transistor through controlling the voltage value on the gate.
When reference to
In summary, the vertical transistor of the present invention includes a drift region, a source region, a drain region, and a gate. The drift region, the source region, and the drain region are of the first doping type, so that the vertical transistor is a junction-less transistor, reducing the power consumption of the transistor.
Obviously, those skilled in the art may make various modifications and variations of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall in the claims of the invention and within the scope of equivalents technology, the present invention is also intended to encompass such changes and variations.
Claims
1. A vertical transistor comprising:
- a first surface and a second surface positioned opposite to the first surface;
- a drift region with a first doping type, the drift region being located between the first surface and the second surface;
- at least one source region with the first doping type and the source region located between the drift region and the first surface, the first dielectric layer being located between adjacent source regions;
- at least one drain region with the first doping type and the drain region being located between said drift region and said second surface;
- and a gate being provided between adjacent drain regions; the gate including a gate electrode and a gate dielectric layer located between the gate electrode and the drift region, and the second dielectric layer being positioned between the gate electrode and the second surface.
2. The vertical transistor of claim 1 further comprising a source electrode located on said first surface and the drain electrode on the second surface.
3. The vertical transistor of claim 1, wherein the the first doping type is N-type.
4. The vertical transistor of claim 3, wherein the drift region is N-type doped GaN, with a thickness of 2-50 μm.
5. The vertical transistor of claim 3, wherein the source region is heavily doped N-type GaN and the drain region is with heavily doped N-type GaN.
6. The vertical transistor of claim 1, wherein the gate electrode is selected from one of Ti, TiN, Ta, TaN, W, Al, Cu, Ag, Ni, Au, Cr, and polycrystalline silicon.
7. The vertical transistor of claim 1, wherein the gate dielectric layer comprises silicon oxide and the thickness of the gate dielectric layer is about 2-50 nm.
8. The vertical transistor of claim 1, wherein the dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm.
9. The vertical transistor of claim 1, wherein the second dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100nm.
10. A system comprising:
- an integrated circuit having:
- a vertical transistor comprising: a first surface and a second surface positioned opposite to the first surface, a drift region with a first doping type, the drift region being located between the first surface and the second surface, at least one source region with the first doping type and the source region located between the drift region and the first surface, the first dielectric layer being located between adjacent source regions, at least one drain region with the first doping type and the drain region being located between said drift region and said second surface, and a gate being provided between adjacent drain regions; the gate including a gate electrode and a gate dielectric layer located between the gate electrode and the drift region, and the second dielectric layer being positioned between the gate electrode and the second surface.
12. The system of claim 10, further comprising a source electrode located on said first surface and the drain electrode on the second surface.
13. The system of claim 10, wherein the first doping type is N-type.
14. The system of claim 13, wherein the drift region is N-type doped GaN, with a thickness of 2-50 μm.
15. The system of claim 13, wherein the source region is heavily doped N-type GaN and the drain region is with heavily doped N-type GaN.
16. The system of claim 10, wherein the gate electrode is selected from one of Ti, TiN, Ta, TaN, W, Al, Cu, Ag, Ni, Au, Cr, and polycrystalline silicon.
17. The system of claim 10, wherein the gate dielectric layer comprises silicon oxide and the thickness of the gate dielectric layer is about 2-50 nm.
18. The system of claim 10, wherein the dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm.
19. The vertical transistor of claim 1 wherein the second dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm.
19. The system of claim 10, wherein the second dielectric layer comprises silicon oxide, SiON, or GaN, and the thickness of the first dielectric layer is about 20-100 nm.
20. A method for implementing a vertical transistor, the method comprising:
- providing a first surface and a second surface;
- positioning the second surface opposite to the first surface;
- providing a drift region with a first doping type;
- positioning the drift region between the first surface and the second surface, wherein at least one source region with the first doping type and the source region located between the drift region and the first surface, the first dielectric layer being located between adjacent source regions, and at least one drain region with the first doping type and the drain region being located between said drift region and said second surface; and
- positioning a gate being between adjacent drain regions, wherein the gate includes a gate electrode and a gate dielectric layer located between the gate electrode and the drift region, and the second dielectric layer being positioned between the gate electrode and the second surface.
Type: Application
Filed: Apr 20, 2017
Publication Date: Aug 3, 2017
Inventors: Deyuan Xiao (Shanghai), Richard Chang (Shanghai)
Application Number: 15/491,985