MOSFET Having Source Region Formed in a Double Wells Region
A transistor includes a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region, a first source region and the drain region on opposite sides of the first gate electrode, a second source region and the drain region on opposite sides of the second gate electrode, a first doped well formed under the first source region, a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well and a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.
This is a divisional application of U.S. patent application Ser. No. 13/541,539, entitled “MOSFET Having Source Region Formed in a Double Wells Region” which was filed on Jul. 3, 2012 and is incorporated herein by reference.
BACKGROUNDThe semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20nm node). As semiconductor devices are scaled down, new techniques are needed to maintain the electronic components' performance from one generation to the next. For example, low gate-to-drain capacitance and high breakdown voltage of transistors may be desirable for power applications.
As semiconductor technologies evolve, metal oxide semiconductor field effect transistors (MOSFET) have been widely used in today's integrated circuits. MOSFETs are voltage controlled devices. When a control voltage is applied to the gate a MOSFET and the control voltage is greater than the threshold of the MOSFET, a conductive channel is built between the drain and the source of the MOSFET. As a result, a current flows between the drain and the source of the MOSFET. On the other hand, when the control voltage is less than the threshold of the MOSFET, the MOSFET is turned off accordingly.
MOSFETs may include two major categories. One is n-channel MOSFETs; the other is p-channel MOSFETs. According to the structure difference, MOSFETs can be further divided into two sub-categories, namely trench power MOSFETs and lateral power MOSFETs.
As process nodes keep shrinking, the physical size of MOSFETs is scaled down. The scaled down structure of MOSFETs may lead to the change of the electrical characteristics of MOSFETs due to short channel effects. For example, in order to obtain a low on resistance MOSFET, a shorter channel length is employed to reduce the on resistance. However, such a shorter channel length may cause the short channel effect. More particularly, as the drain region and the source region of the MOSFET get closer, the risk of punch-through failures may increase as a result.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTIONThe making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the disclosure, and do not limit the scope of the disclosure.
The present disclosure will be described with respect to embodiments in a specific context, a lateral metal oxide semiconductor (MOS) device with superimposed wells. The embodiments of the disclosure may also be applied, however, to a variety of semiconductor devices.
A P+ region 132 and a first N+ region 122 are formed in the second P-type region 106. A second N+ region 124 and a second P+ region 132 are formed in the substrate 102. As shown in
In order to improve the performance of the MOS transistor 100, two lightly doped drain/source (LDD) regions 126 are formed adjacent to their respective N+ regions (first N+ region 122 and second N+ region 124). In accordance with an embodiment, the first N+ region 122 functions as a source region of the MOS transistor 100; the second N+ region 124 functions a drain region the MOS transistor 100. The LDD regions 126 function as extensions of their corresponding drain region 124 and source region 122. The MOS transistor 100 further comprises a gate dielectric layer 127 and the gate electrode 128 formed over the gate dielectric 127.
The substrate 102 may be formed of silicon, silicon germanium, silicon carbide or the like. Alternatively, the substrate 102 may be a silicon-on-insulator (SOI) substrate. The SOI substrate may comprise a layer of a semiconductor material (e.g., silicon, germanium and the like) formed over an insulator layer (e.g., buried oxide and the like), which is formed in a silicon substrate. Other substrates that may be used include multi-layered substrates, gradient substrates, hybrid orientation substrates and the like.
The first P-type region 104 and second P-type region 106 may be formed by implanting p-type doping materials such as boron, gallium, aluminum, indium, combinations thereof, or the like. Alternatively, the P-type region 106 can be formed by a diffusion process. In accordance with an embodiment, a 5V complementary metal oxide semiconductor (CMOS) process is employed to form the first P-type well 104. A 1.8V CMOS process is employed to form the second P-type well 106.
As the second P-type well 106 is embedded in the first P-type well 104, the combined doping density is higher than the conventional P-well formed by a single 5V CMOS process. The combined doping density of the P-wells is in range from about 1017/cm3 to about 1018/cm3. It should be noted that the formation processes of the first P-type region 104 and the second P-type region 106 are compatible with the existing fabrication process of MOS transistors. In other words, the superimposed wells shown in
The first N+ region 122 is formed over the second P-type well 106. In accordance with an embodiment, the first N+ region 122 functions as the source of the MOS transistor 100. The source region may be formed by implanting an n-type dopant such as phosphorous at a concentration of between about 1019/cm3 and about 1020/cm3. Furthermore, a source contact (not shown) may be formed over the first N+ region 122.
The second N+ region 124 is formed in the substrate 102. In accordance with an embodiment, the second N+ region 124 may be the drain of the MOS transistor 100. The drain region may be formed by implanting an n-type dopant such as phosphorous at a concentration of between about 1019/cm3and about 1020/cm3. As shown in
The P+ region 132 shown in
The P+ region 132 may be formed by implanting a p-type dopant such as boron at a concentration of between about 1019/cm3 and about 1020/cm3. The P+ region 132 may be coupled to the p-type body (the substrate 102) of the MOS transistor 100 through the second P-type well 106 and the first P-type well 104. In order to eliminate the body effect, the P+ region 132 may be coupled to the source 122 directly through the source contact (not shown).
The gate dielectric layer 127 is formed between the first N+ region 122 and the second N+ region 124. The gate dielectric layer 127 may be formed of silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide or the like. In accordance with an embodiment, the gate dielectric layer 127 is of a thickness of between about 100 Å and about 200 Å. A gate electrode 128 is formed on the gate dielectric layer 127. The gate electrode 128 may be formed of polysilicon, polysilicon germanium, nickel silicide or other metal, metal alloy materials and the like.
As shown in
A curve 202 and a curve 204 illustrate the doping density difference between a traditional MOS transistor with a 5V p-well and the MOS transistor with superimposed p-wells. As shown in
In accordance with an embodiment, the traditional MOS transistor's doping density shown in
In addition,
The source and drain regions of
A curve 402 and a curve 404 illustrate the doping density difference between a traditional MOS transistor with a 5V p-well and the MOS transistor 300 with superimposed n-wells. As shown in
In accordance with an embodiment, the traditional MOS transistor's doping density shown in
Likewise, the second MOS transistor includes a gate electrode 516, a source region formed by a plurality of N+ regions such as 522, 526 and 530. The second MOS transistor further comprises a body contact formed by a plurality of P+ regions such as 524 and 528. It should be noted that the N+ regions (e.g., N+ region 502) and the P+ regions (e.g., P+ region 504) are not drawn to scale. In accordance with an embodiment, the actual ratio between an N+ region (e.g., N+ region 502) and its adjacent P+ region (e.g., N+ region 502) is in a range from about 10:1 to about 2:1.
The MOS transistor array further comprises a P+ pickup ring 532 surrounding the first MOS transistor and the second MOS transistor. The P+ pickup ring 532 may be coupled to the sources of the MOS transistor array. The P+ pickup ring 532 helps to reduce the body effect of the MOS transistor array.
In comparison with traditional MOS transistors, the top view of
The first MOS transistor includes a gate electrode 812, a source region formed by a plurality of P+ regions such as 804 and 808, and a body contact formed by a plurality of N+ regions such as 802, 806 and 810. Likewise, the second MOS transistor includes a gate electrode 816, a source region formed by a plurality of P+ regions such as 824 and 828, and a body contact formed by a plurality of N+ regions such as 822, 826 and 830. It should be noted that the N+ regions (e.g., N+ region 802) and the P+ regions (e.g., P+ region 804) are not drawn to scale. The actual dimensional ratio between an N+ region and its adjacent P+ region is in a range from about 1:2 to about 1:10.
The MOS transistor array further comprises an N+ pickup ring 832 surrounding the first MOS transistor and the second MOS transistor. The N+ pickup ring 832 may be coupled to a high voltage potential (not shown) of the MOS transistor array. The N+ pickup ring 832 helps to reduce the body effect of the MOS transistor array.
Similar to the structure of
Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A semiconductor device comprising:
- a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region;
- a first source region and the drain region on opposite sides of the first gate electrode;
- a second source region and the drain region on opposite sides of the second gate electrode;
- a first body contact region adjacent to the first source region;
- a plurality of source regions and a plurality of body contact regions adjacent to the first body contact region, wherein the first source region, the first body contact region, the plurality of body contact regions and the plurality of source regions are formed in an alternating manner from a top view; and
- a pickup ring surrounding the first source region, the second source region, the first gate electrode, the second gate electrode and the drain region.
2. The semiconductor device of claim 1, wherein the first source region formed in a first stacked well region, wherein the first stacked well region comprises:
- a first region over the substrate; and
- a second region embedded in the first region, and wherein a doping density of the second region is greater than a doping density of the first region.
3. The semiconductor device of claim 1, wherein the second source region formed in a second stacked well region, wherein the second stacked well region comprises:
- a third region over the substrate; and
- a fourth region embedded in the third region, and wherein a doping density of the fourth region is greater than a doping density of the third region.
4. The semiconductor device of claim 1, wherein:
- the first source region, the first body contact region, the plurality of body contact regions and the plurality of source regions form a region rectangular in shape from the top view.
5. The semiconductor device of claim 4, wherein:
- the region and the first gate electrode are parallel from the top view.
6. The semiconductor device of claim 1, wherein:
- the first source region is an n-type region; and
- the first body contact region is a p-type region.
7. The semiconductor device of claim 1, wherein:
- each body contact region is in direct contact with two source regions.
8. The semiconductor device of claim 1, wherein:
- the first source region and the pickup ring are separated by an isolation region; and
- the first body contact region and the pickup ring are separated by the isolation region.
9. The semiconductor device of claim 1, wherein:
- the pickup ring has a first sidewall in direct contact with a first isolation region and a second sidewall in direct contact with a second isolation region.
10. The semiconductor device of claim 9, wherein:
- a bottom of the first isolation region is in direct contact with a first well; and
- a bottom of the second isolation region is in direct contact with a second well, and wherein: the second well is embedded in the first well; and a doping density of the second well is greater than a doping density of the first well.
11. A device comprising:
- a first gate electrode and a second gate electrode over a substrate and on opposite sides of a drain region;
- a first source region and the drain region on opposite sides of the first gate electrode;
- a second source region and the drain region on opposite sides of the second gate electrode;
- a first doped well formed under the first source region;
- a second doped well formed under the first source region, wherein the first doped well is embedded in the second doped well, and wherein a doping density of the first doped well is greater than a doping density of the second doped well; and
- a body contact region adjacent to the first source region, wherein sidewalls of the body contact region are aligned with sidewalls of the first source region from a top view.
12. The device of claim 11, further comprising:
- a third doped well formed under the second source region; and
- a fourth doped well formed under the second source region, wherein the third doped well is embedded in the fourth doped well, and wherein a doping density of the third doped well is greater than a doping density of the fourth doped well.
13. The device of claim 12, wherein:
- a bottom of the third doped well is substantially level with a bottom of the first doped well; and
- a bottom of the fourth doped well is substantially level with a bottom of the second doped well.
14. The device of claim 11, further comprising:
- a pickup ring surrounding a first transistor formed by the first source region, the first gate electrode and the drain region, and a second transistor formed by the second source region, the second gate electrode and the drain region.
15. The device of claim 14, wherein:
- the first source region, the second source region and the drain region are n-type regions; and
- the body contact region and the pickup ring are p-type regions.
16. An apparatus comprising:
- a first transistor comprising a first gate, a first source, a drain and a first body contact, wherein: the first body contact and the first source form a first column from a top view; and the first source formed in a first stacked well region, wherein the first stacked well region comprises: a first region formed over a substrate; and a second region embedded in the first region;
- a second transistor comprising a second gate, a second source, the drain and a second body contact, and wherein: the second body contact and the second source form a second column from the top view; and the second source formed in a second stacked well region, wherein the second stacked well region comprises: a third region over the substrate; and a fourth region embedded in the third region; and
- a pickup ring surrounding the first transistor and the second transistor.
17. The apparatus of claim 16, wherein:
- a doping density of the second region is greater than a doping density of the first region; and
- a doping density of the fourth region is greater than a doping density of the third region.
18. The apparatus of claim 16, further comprising:
- a first lightly doped source/drain region adjacent to the first source in the second region.
19. The apparatus of claim 16, further comprising:
- a second lightly doped drain/source region adjacent to the drain and formed in the substrate.
20. The apparatus of claim 16, wherein:
- the first source, the second source and the drain are n-type regions; and
- the first body contact, the second body contact and the pickup ring are p-type regions.
Type: Application
Filed: May 15, 2017
Publication Date: Aug 31, 2017
Inventors: Hsueh-Liang Chou (Jhubei City), Chun-Wai Ng (Hsinchu), Po-Chih Su (New Taipei City), Ruey-Hsin Liu (Hsinchu)
Application Number: 15/595,022