Abstract: An intelligent power module packaging structure includes an insulated heat dissipation substrate, a plurality of power devices, a control chip, a lead frame, and an encapsulant. The insulated heat dissipation substrate has a first surface and a second surface opposite to the first surface. The power devices are disposed on the first surface. The control chip is disposed on the first surface. The control chip provides a gate driver function for driving the power devices and a pulse width modulation function. The lead frame is bonded onto the first surface. The power devices are electrically connected to the control chip and the lead frame. The encapsulant at least encapsulates the power devices, the control chip, and a portion of the lead frame, and the second surface is entirely or partially exposed outside the encapsulant.

Abstract: An intelligent power module packaging structure includes an insulated heat dissipation substrate, a plurality of power devices, a control chip, a lead frame, and an encapsulant. The insulated heat dissipation substrate has a first surface and a second surface opposite to the first surface. The power devices are disposed on the first surface. The control chip is disposed on the first surface. The control chip provides a gate driver function for driving the power devices and a pulse width modulation function. The lead frame is bonded onto the first surface. The power devices are electrically connected to the control chip and the lead frame. The encapsulant at least encapsulates the power devices, the control chip, and a portion of the lead frame, and the second surface is entirely or partially exposed outside the encapsulant.

Abstract: A power device package structure including a first substrate, a second substrate, at least one power device, and a package is provided. A heat conductivity of the first substrate is greater than 200 Wm?1K?1. The power device is disposed on the first substrate, and the second substrate is disposed under the first substrate. A heat capacity of the second substrate is greater than that of the first substrate. The package encapsulates the first substrate, the second substrate, and the power device.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation baseplate, and a thermal interface layer. The heat dissipation insulating substrate has a first surface and a second surface which are opposite to each other, and the power devices are coupled to the first surface of the heat dissipation insulating substrate. The heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate, wherein at least one of a surface of the heat dissipation baseplate and the second surface of the heat dissipation insulating substrate has at least one plateau, and the plateau is at least disposed within a projected area of the plurality of power devices. The thermal interface layer is disposed between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation baseplate.

Abstract: A chip packaging structure includes a heat dissipation substrate, a pre-molded chipset, an interconnection and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate. The interconnection is located in the packaging structure and electrically connects the heat dissipation substrate and the pre-molded chipset. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset. The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The patterned circuit is located in the pre-molded chipset. At least two chips are electrically connected by the patterned circuit. The first encapsulant covers at least two chips and part or all of the patterned circuit. A manufacturing method of a chip packaging structure is also provided.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation baseplate, and a thermal interface layer. The heat dissipation insulating substrate has a first surface and a second surface which are opposite to each other, and the power devices are coupled to the first surface of the heat dissipation insulating substrate. The heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate, wherein at least one of a surface of the heat dissipation baseplate and the second surface of the heat dissipation insulating substrate has at least one plateau, and the plateau is at least disposed within a projected area of the plurality of power devices. The thermal interface layer is disposed between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation baseplate.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, at least one conductive clip, and a heat dissipation baseplate. The heat dissipation insulating substrate has a first surface and a second surface opposite thereto, and the power devices form a bridge circuit topology and are disposed on the first surface, wherein active regions of at least one of the power devices are flip-chip bonded to the first surface. The conductive clip is configured to electrically connect at least one of the power devices to the first surface, and the heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate.

Abstract: A package structure is provided. The package structure includes a leadframe including a plurality of connection portions; a device including a substrate, an active layer disposed on the substrate and a plurality of electrodes disposed on the active layer, wherein the electrodes of the device are connected to the connection portions of the leadframe; a conductive unit having a first side and a second side, wherein the first side of the conductive unit connects to the substrate of the device and the conductive unit connects to at least one of the connection portions of the leadframe; and an encapsulation material covering the device and the leadframe, wherein the second side of the conductive unit is exposed from the encapsulation material.

Abstract: A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Abstract: A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.

Abstract: A power device package structure including a first substrate, a second substrate, at least one power device, and a package is provided. A heat conductivity of the first substrate is greater than 200 Wm?1K?1. The power device is disposed on the first substrate, and the second substrate is disposed under the first substrate. A heat capacity of the second substrate is greater than that of the first substrate. The package encapsulates the first substrate, the second substrate, and the power device.

Abstract: A power device for a rectifier includes a first terminal and a second terminal for connecting an external circuit, and a circuit system located between the first terminal and the second terminal. The circuit system is electrically connected to the first terminal and the second terminal. The circuit system includes a pre-molded chip and a control device. The pre-molded chip includes a transistor and a first encapsulant for encapsulating the transistor, wherein the transistor has a first electrode, a second electrode, and a third electrode. The first terminal, the second terminal and the control device are respectively electrically connected to the first electrode, the second electrode and the third electrode of the transistor.

Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.