EMBEDDED ENDPOINT FIN REVEAL
A method for fabricating a semiconductor structure includes forming a cut mask over a set of fin hard masks formed on a substrate. At least one gap defined at least in part by the cut mask is formed, and a first dielectric layer is formed within the at least one gap. A plurality of fins is formed, and the first dielectric layer is recessed to form an isolation region. A liner is deposited along exposed surfaces of the recessed first dielectric layer and the plurality of fins. A second dielectric layer is formed within a region defined by the liner and the plurality of fins. At least a portion of the second dielectric layer is removed to reveal the plurality of fins, wherein the portion of the second dielectric layer that is removed is based on the liner serving as an endpoint layer.
Semiconductor structures or devices may be embodied as field-effect transistors (FETs), such as metal-oxide-semiconductor FETs (MOSFETs). A FinFET is a nonplanar MOSFET that may be built on a silicon substrate, such as a silicon-on-insulator (SOI) substrate. FinFETs may provide advantages over planar MOSFETS. For example, FinFETS utilize vertical fins that allow for larger areal densities, thereby increasing the number of structures that may be built on an integrated circuit, or chip. Accordingly, FinFETS provide improved areal density over planar MOSFETs.
SUMMARYIllustrative embodiments of the invention provide techniques for fabricating FET structures, such as, e.g., FinFET structures. While illustrative embodiments are well-suited to improve operations of FinFET structures, alternative embodiments may be implemented with other types of semiconductor structures.
For example, in one illustrative embodiment, a method for fabricating a semiconductor structure comprises forming a cut mask over a set of fin hard masks formed on a substrate. At least one gap defined at least in part by the cut mask is formed, and a first dielectric layer is formed within the at least one gap. A plurality of fins is formed from the set of fin hard masks and the substrate by etching down through the cut mask, and the first dielectric layer is recessed via an etching process to form an isolation region. A liner is deposited along exposed surfaces of the recessed first dielectric layer and the plurality of fins. A second dielectric layer is formed within a region defined by the liner and the plurality of fins. At least a portion of the second dielectric layer is removed to reveal the plurality of fins, wherein the portion of the second dielectric layer that is removed is based on the liner serving as an endpoint layer.
In another embodiment, a semiconductor structure comprises a plurality of fins formed from a substrate. The structure also comprises at least one liner segment formed along a portion of the substrate. Further, the structure comprises a first dielectric layer formed on the substrate and bounded by the liner segment, and a second dielectric layer formed within an interior of the liner segment.
In a further embodiment, an integrated circuit comprises a plurality of fins formed from a substrate. The integrated circuit also comprises at least one liner segment formed along a portion of the substrate. Further, the integrated circuit comprises a first dielectric layer formed on the substrate and bounded by the liner segment, and a second dielectric layer formed within an interior of the liner segment.
These and other exemplary embodiments of the invention will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
In illustrative embodiments, techniques are provided for fabricating semiconductor devices comprised of one or more FinFETs. More particularly, illustrative embodiments provide techniques for fabricating semiconductor devices with uniform fin reveal. As will be explained in illustrative embodiments, such fabrication techniques are advantageous over conventional fabrication techniques.
Furthermore, it is to be understood that embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to fabrication (forming or processing) steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the steps that may be used to form a functional integrated circuit device. Rather, certain steps that are commonly used in fabricating such devices are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. It is to be understood that the terms “about,” “approximately” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present such as, by way of example only, 1% or less than the stated amount. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.
Uniform fin reveal is highly desired to minimize device variability. In fabricating a conventional FinFET structure, fin reveal depth may not be easy to control. For example, a dense fin region may have many variations. It would be advantageous to control fin reveal in a dense fin region. In one embodiment, a fin liner may be implemented as an embedded endpoint layer to increase control of the fin reveal in a dense fin region.
Semiconductor structure 100 in
As referenced previously with respect to
After completion of this stage, further conventional fabrication steps may take place to form remaining features of semiconductor structure 100, such as gate formation, etc.
It is to be understood that the methods discussed herein for fabricating semiconductor structures can be incorporated within semiconductor processing flows for fabricating other types of semiconductor devices and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with embodiments can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein.
Furthermore, various layers, regions, and/or structures described above may be implemented in integrated circuits (chips). The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Although illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention.
Claims
1. A method for fabricating a semiconductor structure, the method comprising:
- forming a cut mask over a set of fin hard masks formed on a substrate;
- forming at least one gap defined at least in part by the cut mask, and forming a first dielectric layer within the at least one gap;
- forming a plurality of fins from the set of fin hard masks and the substrate by etching down through the cut mask, and recessing the first dielectric layer via an etching process to form an isolation region;
- depositing a liner along exposed surfaces of the recessed first dielectric layer and the plurality of fins;
- forming a second dielectric layer within a region defined by the liner and the plurality of fins; and
- removing at least a portion of the second dielectric layer to reveal the plurality of fins, wherein the portion of the second dielectric layer that is removed is based on the liner serving as an endpoint layer.
2. The method of claim 1, further comprising forming the set of fin hard masks by applying at least one iteration of a self-aligned double patterning (SADP) process.
3. The method of claim 1, wherein the substrate is comprised of silicon (Si).
4. The method of claim 1, wherein the liner is comprised of silicon mononitride (SiN).
5. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are comprised of a same material.
6. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are comprised of different materials.
7. The method of claim 1, further comprising performing a first chemical mechanical planarization (CMP) process after forming the first dielectric layer, and a second CMP process after forming the second dielectric layer.
8. The method of claim 1, further comprising removing the hard mask and a portion of the liner formed on an exposed surface of the first dielectric layer.
9-20. (canceled)
21. The method of claim 2, further comprising forming a layer of silicon mononitride (SiN) on the substrate, wherein the set of fin hard masks is formed by applying the at least one iteration of the SADP process to the layer of SiN.
22. The method of claim 2, wherein forming the set of fin hard masks comprises applying one iteration of the SADP process.
23. The method of claim 2, wherein forming the set of fin hard masks comprises applying two iterations of the SADP process resulting in a self-aligned quadruple patterning (SAQP) process.
24. The method of claim 1, wherein the etching process comprises an anisotropic etching process.
25. The method of claim 1, wherein the etching process comprises an isotropic etching process.
26. The method of claim 1, wherein the first dielectric layer comprises an oxide.
27. The method of claim 26, wherein the oxide comprises silicon dioxide (SiO2).
28. The method of claim 1, wherein the second dielectric layer comprises an oxide.
29. The method of claim 28, wherein the oxide comprises silicon dioxide (SiO2).
30. The method of claim 1, wherein removing the portion of the second dielectric layer to reveal the plurality of fins comprises using a second etching process.
31. The method of claim 30, wherein the second etching process comprises an anisotropic etching process.
32. The method of claim 31, wherein the second etching process comprises anisotropic reactive ion etching.
Type: Application
Filed: Sep 9, 2016
Publication Date: Mar 15, 2018
Inventors: Kangguo Cheng (Schenectady, NY), Peng Xu (Guilderland, NY)
Application Number: 15/261,055