Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

Abstract: A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.

Abstract: Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.

Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.

Abstract: Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.

Abstract: Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer and a second eviction condition. In response to detecting the eviction event, a descriptor list from the set of candidate descriptor lists is selected for eviction. The selected descriptor list can be evicted from the cache memory.

Abstract: An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data. The stream selector circuit inserts compute circuit type identifiers within the output trace data. Each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data of the output trace data. The high-speed debug trace circuit includes an output transmitter circuit configured to output the output trace data.

Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

Abstract: Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.

Abstract: Embodiments herein describe techniques for preparing and executing tasks related to a database query in a database accelerator. In one embodiment, the database accelerator is separate from a host CPU. A database management system (DBMS) can offload tasks corresponding to a database query to the database accelerator. The DBMS can request data from the database relevant to the query and then convert that data into one or more data blocks that are suitable for processing by the database accelerator. In one embodiment, the database accelerator contains individual hardware processing units (PUs) that can process data in parallel or concurrently. In order to process the data concurrently, the data block includes individual PU data blocks that are each intended for a respective PU in the database accelerator.

Abstract: An integrated circuit (IC) device includes a controller circuitry having an input connected to a photodiode of an optoelectronic circuitry and an output connected to a biasing circuitry, the biasing circuitry having an input connected to the output of the controller circuitry, the controller circuitry configured to transmit a transimpedance control signal code to the biasing circuitry configured to cause the biasing circuitry to offset a DC current component of the output of the photodiode.

Abstract: In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Abstract: An emulation system can include a first integrated circuit (IC) including first circuitry and a first transceiver. The first circuitry is configured to emulate a first partition of a circuit design. The first circuitry is clocked by an emulation clock and the first transceiver is clocked by a transceiver clock asynchronous with the emulation clock. The transceiver clock has a higher frequency than the emulation clock. The emulation system can include a second IC configured to emulate a second partition of the circuit design. The second IC includes a second transceiver. The first transceiver is configured to generate multiplexed emulation data by multiplexing a plurality of nets that cross from the first partition to the second partition of the circuit design. The first transceiver is configured to send the multiplexed emulation data over a serial communication channel to the second transceiver. The multiplexed emulation data includes a clock signal of the first transceiver embedded therein.

Abstract: Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.

Abstract: Handling port resets in a multi-port system includes monitoring, using a plurality of firewall circuits, a plurality of controllers corresponding to different communication ports for a reset condition. The plurality of controllers are coupled to a direct memory access (DMA) system through a plurality of bridge circuits. A selected firewall circuit detects a reset condition on a selected controller coupled thereto. The selected controller is coupled to a selected bridge circuit of the plurality of bridge circuits. In response to detecting the reset condition, the selected firewall circuit implements a firewall operating mode. While operating in the firewall operating mode, the selected firewall circuit is configured to control operation of the selected bridge circuit thereby isolating the selected controller from the DMA system. Firewall operating mode of firewall circuits also may be initiated by a management processor in a proactive manner.

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

Abstract: A multi-core architecture in some examples may have hundreds of “cores”, each core comprising a digital signal processor (DSP) and various functional computing units. A method of implementing a multi-core graph compiler for a system-on-chip (SOC) having a data processing engine (DPE) array is disclosed herein. An Adaptive Intelligence Engine (AIE) compiler is one example of a multi-core graph compiler. An compiler is used to mitigate performance degradation due to memory stalls (collisions) when executing an AIE compiler-accelerated application on an AI Engine. The method disclosed here addresses phase order issues to mitigate the memory collisions.

Abstract: Embodiments herein describe techniques for expressing the layers of a neural network in a software model. In one embodiment, the software model includes a class that describes the various functional blocks (e.g., convolution units, max-pooling units, rectified linear units (ReLU), and scaling functions) used to execute the neural network layers. In turn, other classes in the software model can describe the operation of each of the functional blocks. In addition, the software model can include conditional logic for expressing how the data flows between the functional blocks since different layers in the neural network can process the data differently. A compiler can convert the high-level code in the software model (e.g., C++) into a hardware description language (e.g., register transfer level (RTL)) which is used to configure a hardware system to implement a neural network accelerator.

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.