Abstract: A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear activation function from a memory. The PNL activation engine is capable of performing a polynomial approximation of the first non-linear activation function on the input data using the first set of coefficients. The PNL activation engine is capable of outputting a result from the polynomial approximation of the first non-linear activation function.

Abstract: A machine learning-based process includes identifying a first set of features that includes features of a reference implementation of a circuit design and features of a synthesized version of a modified version of the circuit design. A first classification model is applied to the first set of features, and the first classification model indicates a full implementation flow or an incremental implementation flow. The full implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the full implementation flow, and the incremental implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the incremental implementation flow. The full and incremental implementation flows generate implementation data that is suitable for making an integrated circuit (IC).

Abstract: An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

Abstract: Automatically generating a hardware image based on programming model types includes determining by a design tool, types of programming models used in specifications of blocks of a circuit design, in response to a user control input to generate a hardware image to configure a programmable integrated circuit (IC). The design tool can generate a model-type compiler script for each of the types of programming models. Each compiler script initiates compilation of blocks having specifications based on one of the types of programming model into an accelerator representation. The design tool can generate a build script configured to execute the compiler scripts and link the accelerator representations into linked accelerator representations. Execution of the build script builds a hardware image from the linked accelerator representations for configuring the programmable IC to implement a circuit according to the circuit design.

Abstract: Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from the respective memory bank. A second switching circuit (304) routes tuples based on row indices of the tuples. Each tuple includes a product output by the one of the N multipliers and a row index output by an output port of the first switching circuit. N accumulator circuits (307) sum products of tuples having equal row indices.

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

Abstract: An inference server is capable of receiving a plurality of inference requests from one or more client systems. Each inference request specifies one of a plurality of different endpoints. The inference server can generate a plurality of batches each including one or more of the plurality of inference requests directed to a same endpoint. The inference server also can process the plurality of batches using a plurality of workers executing in an execution layer therein. Each batch is processed by a worker of the plurality of workers indicated by the endpoint of the batch.

Abstract: A rearranger circuit rearranges data elements of each raw image of a plurality of raw images according to a plurality of raw color channel arrays. The data elements of each raw image are input to the rearranger circuit according to instances of a pattern of color channels of a color filter array (CFA). The data elements specify values of the color channels in the instances of the pattern, and each raw color channel array has the data elements of one color channel of the color channels in the instances of the pattern. The rearranger circuit can be used in neural network training or in generating raw color channel arrays for performing neural network inference.

Abstract: Remote kernel execution in a heterogeneous computing system can include executing, using a device processor of a device communicatively linked to a host processor, a device runtime and receiving from the host processor within a hardware submission queue of the device, a command. The command requests execution of a software kernel and specifies a descriptor stored in a region of a memory of the device shared with the host processor. In response to receiving the command, the device runtime, as executed by the device processor, invokes a runner program associated with the software kernel. The runner program can map a physical address of the descriptor to a virtual memory address corresponding to the descriptor that is usable by the software kernel. The runner program can execute the software kernel. The software kernel can access data specified by the descriptor using the virtual memory address as provided by the runner program.

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.

Abstract: A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.

Abstract: Various noise isolation structures and methods for fabricating the same are presented. In one example, a substrate for chip package is provided. The substrate includes a core region, top build-up layers and bottom build-up layers. The top build-up layers are formed on a first side of the core region and the bottom build-up layers are formed on a second side of the core region that is opposite the first side. Routing circuitry formed in the bottom build-up layers is coupled to routing circuitry formed in the top build-up layers by vias formed through the core region. A void is formed in the bottom build-up layers. The void is configured as a noise isolation structure. The void has a sectional area that is different in at least two different distances from the core region.

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

Abstract: N key generation circuits are arranged in a pipeline having N stages. Each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant. Output signal lines that carry the round key from a key generation circuit in a stage of the pipeline, except the key generation circuit in a last stage of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input key.

Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).

Abstract: Phase-locked loop circuitry generates an output signal based on transformer based voltage controlled oscillator (VCO) circuitry. The VCO circuitry includes upper band circuitry including first oscillation circuitry, a first harmonic filter circuitry coupled to the first oscillation circuitry, and a first selection transistor coupled to the first harmonic filter circuitry and a current source. The first harmonic filter circuitry filters the output signal. The lower band circuitry includes second oscillation circuitry, a second harmonic filter circuitry coupled to the second oscillation circuitry, and a second selection transistor coupled to the second harmonic filter circuitry and the current source. The second harmonic filter circuitry filters the output signal.

Abstract: A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.