Abstract: Redundant data storage includes performing a first data transfer to a first storage device as part of a redundant write operation. A first error detection code is generated for the first data transfer. A second data transfer is performed to a second storage device as part of the redundant write operation. A second error detection code is generated for the second data transfer. The first error detection code is compared with the second error detection code for a match indicating that data of the first data transfer matches data of the second data transfer.

Abstract: Examples herein describe memory lifecycle state sensors. A memory lifecycle state sensor includes a memory and a processor. The processor is configured to write a first value to a cell of the memory at a first voltage, and the cell is storing a second value written to the cell at a second voltage that is greater than the first voltage. A value is read from the cell and compared with the first value. An indication of a lifecycle state for the cell is generated based on comparing the value with the first value, the first voltage, and the second voltage.

Abstract: Application code is compiled to generate code to be executed by the cores of a multi-core architecture. Generating the code includes mapping kernels of the application onto the DPEs, and generating main code for cores of the DPEs. The main code is generated by initializing locks for each kernel associated with the cores the DPEs. The locks are associated with input ports and output ports of the kernels. Further, buffers are initialized for the kernels. The buffers are associated with the locks and data streams. Subsequent to initializing the locks and initializing the buffers, the kernels are executed to generate data samples from the data streams. Subsequent to executing the kernels, the locks are released for subsequent calls of the kernels.

Abstract: A device may include an array of data processing engines (DPEs) on a die and an event broadcast network. Each of the DPEs includes a core, a memory module, event logic in at least one of the core or the memory module, and an event broadcast circuitry coupled to the event logic. The event logic is capable of detecting an occurrence of one or more events in the core or the memory module. The event broadcast circuitry is capable of receiving an indication of a detected event detected by the event logic. The event broadcast network includes interconnections between the event broadcast circuitry of the DPEs. Detected events can trigger or initiate various responses, such as debugging, tracing, and profiling.

Abstract: Devices, systems, and methods manage activity in die-to-die links. A link controller places a die-to-die link in a partially active state, with some lane groups active and others idle, adapting to changing conditions without full link retraining. Lane groups can independently enter an electrical idle state, reducing power consumption without interrupting data transmission over active lanes. Idle lanes can be retrained and reactivated without affecting active lanes. Control messages, may manage lane group states, ensuring synchronized transitions between active and idle states. This approach optimizes power management and maintains data transmission efficiency in die-to-die interconnects.

Abstract: Disclosed devices, systems, and methods may enhance communication protocols for low latency applications. Systems may include a device and a host interconnected by a high-performance interconnect and/or communication link. The device may comprise a transmitter, a receiver, and a control unit that may manage a credit-based flow control mechanism. In some aspects, the device may initiate a push write request, send a data header with an identifier (UQID) matching the push write request identifier (CQID), and transmit the data payload. The host may receive the push write request, match the UQID with the CQID, perform the write operation, and send a completion message back to the device. The method may involve ensuring sufficient credits before initiating the push write transaction, which may help prevent data loss and ensure reliable delivery. The push write mechanism may reduce the number of link traversals required for device-to-host memory writes, potentially lowering overall latency.

Abstract: Model level debugging of a machine learning design includes compiling the machine learning design for execution on target hardware using a compiler. Metadata for the machine is generated. The metadata specifies a mapping of buffers of the machine learning design to a plurality of memory levels of a memory architecture of the target hardware correlated with boundaries of the machine learning design. While running the machine learning design, debug data is dumped from the plurality of memory levels of the memory architecture based on the boundaries. The debug data is correlated with the boundaries of the machine learning design based on the metadata.

Abstract: High-level synthesis generation of multiplexer logic includes generating, using computer hardware, an intermediate representation of a design for an integrated circuit. The design is specified in high-level programming language source code. Selected logic within the intermediate representation is detected by the computer hardware and converted into a sparsemux node. A selected core is chosen from a plurality of cores to implement the sparsemux node. The computer hardware is capable of choosing the selected core based on a label encoding format and a default input of the sparsemux node. A circuit design is generated by the computer hardware. One or more operations of the selected core are scheduled based on a timing model corresponding to the selected core.

Abstract: Disclosed herein is a package substrate and a method for fabricating the same. In one example, a package substrate includes a core having an outer edge and a first plurality of first interconnect layers disposed on the core. The first plurality of interconnect layers disposed on the core include an outermost dielectric layer disposed farthest from the core. The outermost dielectric layer has an edge that is recessed from the edge of the core.

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

Abstract: An electronic system includes a key memory circuit capable of storing a plurality of keys and outputting an address for a key of the plurality of keys matched to a search key. The electronic system includes a memory manager circuit capable of tracking free memory addresses in the key memory circuit. The electronic system includes a state tracker circuit including a value memory circuit. The value memory circuit is capable of storing values of state information and is separate from the key memory circuit. The electronic system includes an insert-delete circuit capable of passing the address from the key memory circuit to the state tracker circuit, performing insert and delete operations on the key memory circuit, and providing free memory addresses of the key memory circuit to the memory manager circuit.

Abstract: A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.

Abstract: Embodiments herein describe a 3D splintered physical unclonable function (3D-sPUF). In an example, an integrated circuit (IC) device includes multiple dies in a stacked configuration, and a PUF circuit generates a set of bits that is unique to the PUF circuit based on physical variations of elements of the PUF circuit, where the PUF circuit is distributed amongst two or more of the dies.

Abstract: Bi-directional dynamic function exchange (DFX) can include receiving a circuit design for a programmable integrated circuit (IC). The circuit design includes a plurality of DFX partitions coupled by a signal path. The circuit design can be placed using a first plurality of DFX modules for the plurality of DFX partitions, in part, by selecting a flip-flop of a connection block as a boundary flip-flop of the signal path for each DFX module of the plurality of DFX modules. The circuit design including the signal path can be routed through the selected flip-flops of the connection blocks using a bi-directional routing resource coupling the plurality of connection blocks. The bi-directional routing resource is used as a partition pin placement constraint (PPLOC) node for DFX.

Abstract: Systems and methods for performing multiple locally stored artificial neural network (ANN) computations are provided. An example method comprises receiving, by one or more processing units, an ANN dataset associated with at least one ANN of a plurality of ANNs; storing, by processing units, the ANN dataset in a memory coupled to the processing units; associating, by the processing units, a base address with the at least one ANN, wherein the base address is to be used to locate the ANN dataset in the memory; keeping, by the processing units, the ANN dataset in the memory; receiving, by the processing units, an input dataset and the base address; determining, by the processing units and based on the base address, a location of the ANN dataset in the memory; and performing, by the processing units, ANN computation using the ANN dataset and input dataset.

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

Abstract: Optimizing timing margins across conditions is described. In one or more implementations, a computing system may include an interface circuitry configured to adjust a timing alignment of first and second signals between a central processing unit (CPU) of the system and a device coupled with the CPU and to measure and store one or more margins between the timing alignment and misalignments of the first and second signals. The interface circuitry may be configured to measure and store the timing margins at first and second conditions. The first and second conditions may be different voltages, temperatures, etc. The system may be configured to force the first and/or second condition. The system may be configured to calculate a coefficient from differences in between the margins and between the first and second conditions.

Abstract: In-system electrical connectivity detection. In one or more implementations, a computing device includes a transmitter and a receiver in a package, the transmitter to transmit a signal to a separate device, the receiver to receive and measure a reflection of the transmitted signal, and the measured reflection for characterizing (e.g., testing or detecting) an electrical connection between the computing and separate devices. The computing device may characterize (e.g., detect a discontinuity in) the electrical connection by comparing a magnitude of the transmitted signal with a magnitude of the measured reflection. The computing device may be coupled with the separate device by multiple electrical connections, and the multiple electrical connections may be tested by corresponding transmitters and receivers.

Abstract: Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.

Abstract: Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and/or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.