Patents Assigned to Xilinx, Inc.
  • Publication number: 20190181863
    Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.
    Type: Application
    Filed: December 8, 2017
    Publication date: June 13, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ilya K. Ganusov, Brian C. Gaide, Henri Fraisse
  • Patent number: 10320386
    Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Brian C. Gaide, Henri Fraisse
  • Patent number: 10320516
    Abstract: Apparatus and method for communication is disclosed. In an apparatus, at least one transmission circuit is configured to provide an output alignment marker representing an exclusive disjunction of an orthogonal sequence and an input alignment marker. A multiplexer is configured to multiplex the output alignment marker with payload data for transmission via a communication lane of a plurality of communication lanes.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventor: Ben. J. Jones
  • Patent number: 10317464
    Abstract: An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventor: Partho Tapan Chaudhuri
  • Patent number: 10319606
    Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a package substrate having a plurality of solder balls coupled to a plurality of contact pads. The package substrate includes a solder mask having a plurality of stepped openings, a plurality of contact pads, and circuitry disposed in the package substrate and coupled to the plurality of contact pads. The solder mask defines a top side of the package substrate. The stepped openings expose the contact pads through solder mask.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Tien-Yu Lee, Henley Liu, Ivor G. Barber, Suresh Ramalingam
  • Patent number: 10320918
    Abstract: In an example, an integrated circuit (IC) includes a receive circuit, a transmit circuit, and a control circuit. The receive circuit includes a receive data path and a receive control interface, the receive data path coupled to store received transmission control protocol (TCP) data for a plurality of TCP sessions in a respective plurality of receive buffers in an external memory circuit external to the IC. The transmit circuit includes a transmit data path and a transmit control interface, the transmit data path coupled to read TCP data to be transmitted for the plurality of TCP sessions from a respective plurality of transmit buffers in the external memory circuit. The control circuit is coupled to the receive control interface and the transmit control interface, the control circuit configured to maintain data structures to maintain TCP state information for the plurality of TCP sessions.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Michaela Blott, David A. Sidler, Kimon Karras, Raymond Carley, Kornelis A. Vissers
  • Patent number: 10318681
    Abstract: Leakage current estimation for a circuit can include generating a cell leakage library including cell-level leakage current geometry data for different states of cells of a cell library, wherein the cells are specified as transistor-level netlists, and determining, using a processor, gate-level leakage current geometry data for gates of a gate-level netlist for the circuit based upon states of the gates for a selected operating state of the circuit and the cell-level leakage current geometry data. Total leakage current geometry data can be determined, using the processor, for the gate-level netlist by aggregating the gate-level leakage current geometry data.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Fu-Hing Ho, Johnie Au
  • Patent number: 10318699
    Abstract: Disclosed approaches for fixing a hold time violation in a circuit design include determining a first hold budget that is an amount to fix a first hold time violation on a first path of the circuit design. For each connection of a first plurality of connections on the first path, a respective projected setup slack of the connection in allocating the first hold budget to fixing the first hold time violation on the connection is determined. For each connection of the first plurality of connections, a respective connection hold budget based on the first hold budget and the respective projected setup slack is determined. Each connection of the first plurality of connections is adjusted according to the respective connection hold budget.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Satish B. Sivaswamy, Parivallal Kannan
  • Patent number: 10320401
    Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Augusto R. Ximenes, Bob W. Verbruggen, Christophe Erdmann
  • Publication number: 20190170816
    Abstract: Methods and apparatus are described relating to a probe assembly having a probe head securing mechanism that includes a lock ring housing and a lock ring disposed in the lock ring housing. In an example, a probe assembly includes a rigid substrate, a circuit board coupled to the rigid substrate, and a probe head securing mechanism. The probe head securing mechanism includes a lock ring housing and a lock ring disposed within the lock ring housing. The circuit board has a surface. The lock ring housing is coupled to the rigid substrate. The circuit board is disposed between the lock ring housing and the rigid substrate. The lock ring is rotatable relative to the lock ring housing. Rotation of the lock ring is configured to move the lock ring in a direction perpendicular to the surface of the circuit board.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Applicant: Xilinx, Inc.
    Inventors: Mohsen H. Mardi, Lik Huay Lim, King Yon Lew, Andy Widjaja
  • Publication number: 20190172504
    Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Applicant: Xilinx, Inc.
    Inventors: Umanath R. Kamath, John K. Jennings, Edward Cullen, Ionut C. Cical, Darragh Walsh
  • Patent number: 10310014
    Abstract: Methods and apparatus are described for converting a pre-silicon Open Verification Methodology or Universal Verification Methodology (OVM/UVM) device under test (DUT) into a design implementable on a programmable integrated circuit (IC) and for converting the pre-silicon OVM/UVM stimulus from the driver and expected response from the scoreboard into timing aware stimulus-response vectors that can be applied through the tester onto the pads of the programmable IC that contains the implemented design. This approach can handle the clock and other input stimuli changing concurrently in the pre-silicon testbench, and the vectors generated therefrom will be in the proper form so as to work deterministically on the silicon on the tester.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: June 4, 2019
    Assignee: XILINX, INC.
    Inventors: Subodh Kumar, Aniruddha Talukder, Kameswari SB Angada
  • Patent number: 10314163
    Abstract: An integrated circuit device having a vertical connection interfaces for coupling stacked components are provided that improve communication between the stacked components. The techniques described herein allow for increased signal connection density while reducing potential for crosstalk. For example, a ground to signal ratio of connections between components in a vertical interface configured to carry ground signals relative to connections configured to carry data signals within a bank of connections has an edge to center gradient which reduces the amount of ground connections needed to meet crosstalk thresholds, while increasing the amount of signal connections available for communication between components across the vertical interface.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 4, 2019
    Assignee: XILINX, INC.
    Inventors: Hong Shi, Siow Chek Tan
  • Patent number: 10303385
    Abstract: Modifying initialization data for a memory array of a circuit design can include providing, using a processor, portions of an incoming stream of data for initializing the memory array to emulation objects of a memory array emulator. The memory array emulator is configured to emulate an implementation of the memory array and the emulation objects represent block random access memories (block RAMs) of the memory array. Using the processor, the data can be formatted using the emulation objects to generate initialization data, wherein the data is formatted based upon configuration settings of the block RAMs emulated by the respective emulation objects. A configuration bitstream can be updated, using the processor, with the initialization data.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Michael Keilson, Stephen P. Rozum, Ryan A. Linderman, Pradip Kar
  • Patent number: 10303833
    Abstract: Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Aman Gayasen, Surya Pratik Saha, Elliott Delaye, Shangzhi Sun, Ashish Sirasao
  • Patent number: 10305511
    Abstract: Decompressing a data set includes inputting data units to a decompression circuit and comparing each input data unit to a run value and to a substitute value. In response to the data unit being not equal to the run value or the substitute value, the decompression circuit outputs the value of the input data unit; in response to the input data unit having the run value and a succeeding data unit having a value N not equal to zero or one, the decompression circuit outputs multiple data units having the run value based on the value N; in response to input data unit having the substitute value, the decompression circuit outputs one data unit having the run value; and in response to one input data unit having the run value and a succeeding data unit equal to zero or one, the decompression circuit outputs one data unit of the substitute value.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: David P. Schultz, Weiguang Lu, Priyanka Agrawal, Jun Liu, Sourabh Goyal, David Robinson
  • Patent number: 10302698
    Abstract: Disclosed approaches of determining an estimated glitch toggle rate at an output of a logic circuit include inputting functional static probabilities of combinations of states of the plurality of inputs and a generated glitch toggle rate of the logic circuit. Each functional static probability indicates a probability of the states of the inputs of the combination. For each input of the plurality of inputs to the logic circuit, a Boolean Difference Function (BDF) of the input is generated. A maximum glitch rate, which is the estimated glitch toggle rate, is determined based on the generated glitch toggle rate and the functional static probabilities associated with selected combinations of states of the BDF.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Fan Zhang, Anup K. Sultania
  • Patent number: 10302504
    Abstract: The disclosure provides simple, low-cost but accurate systems and related methods for on-die temperature sensing typically using calibration and without the need for precision voltage references. In some implementations, the system utilizes two user selectable temperature sensing elements and two user selectable DACs to provide a digital code for the sensed temperature. In some implementations, the two sensing elements can be used to calibrate against each other. For example, calibration can be useful to account for silicon local/global variation. Typically, one of the temperature sensors is diode-based, while the other is resistor-based. However, those of skill in the art will recognize that, in accordance with the disclosure, more than two sensors can be provided that can be calibrated against one another.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Suresh P. Parameswaran, Boon Y. Ang, Ankur Jain
  • Patent number: 10303648
    Abstract: Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 28, 2019
    Assignee: XILINX, INC.
    Inventors: Sabyasachi Das, Zhiyong Wang, Niyati Shah
  • Patent number: 10296699
    Abstract: Implementing a circuit design for partial reconfiguration can include routing, using a processor, a net of the circuit design that connects an endpoint within a reconfigurable module with an endpoint within static circuitry external to the reconfigurable module and forming, using the processor, a set of candidate nodes including nodes used to route the net. A node from the set of candidate nodes is determined as the partition pin for partial reconfiguration.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 21, 2019
    Assignee: XILINX, INC.
    Inventors: Hao Yu, Raymond Kong, Jun Liu