Patents Assigned to Xilinx, Inc.
  • Publication number: 20250147799
    Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: Xilinx, Inc.
    Inventors: Thomas Calvert, Ripduman Sohan, Dmitri Kitariev, Kimon Karras, Stephan Diestelhorst, Neil Turton, David Riddoch, Derek Roberts, Kieran Mansley, Steven Pope
  • Publication number: 20250148179
    Abstract: A memory includes a read circuit having a first primitive configured to output a first data item based on least significant bits (LSBs) of a read address and a multiplexer coupled to the primitive. The multiplexer outputs a selected bit from the first data item as read data based on most significant bits (MSBs) of the read address. The memory includes a write circuit having a second primitive that outputs a second data item based on LSBs of a write address and a modifier circuit that generates a third data item by modifying a bit of the second data item to correspond to write data. The bit is at a location within the second data item selected based on MSBs of the write address. The modifier circuit writes the third data item to a location in the write primitive based on the LSBs of the write address.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 8, 2025
    Applicant: Xilinx, Inc.
    Inventors: Pradip Kar, Chaithanya Dudha, Nithin Kumar Guggilla
  • Publication number: 20250142735
    Abstract: A method of attaching a chip package to a printed circuit board (“PCB”) is provided, along with an electronic device fabricated using the method. The method includes measuring a warpage parameter of the chip package and selecting a stencil configured to compensate for warpage corresponding to the measured warpage parameter. The stencil includes a plurality of apertures. The selected stencil is positioned above the PCB, and solder paste is applied on the PCB via the plurality of apertures of the stencil. Thereafter, the PCB is moved away from the stencil. The chip package is positioned on the solder paste on the PCB, thereby attaching the chip package to the PCB.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Applicant: XILINX, INC.
    Inventor: Gamal REFAI-AHMED
  • Patent number: 12273106
    Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventors: David P. Schultz, Richard W. Swanson
  • Patent number: 12273668
    Abstract: A non-blocking crossbar switch architecture circumvents the problem present in prior art crossbar switches where input signals may oversubscribe the available inter-die bandwidth. The new non-blocking crossbar switch architecture is split across a plurality of semiconductor dice, including a plurality of interleaved crossbar switch segments. Only one crossbar switch segment is implemented on each semiconductor die. A plurality of input ports and output ports are coupled to the crossbar switch. The crossbar switch is non-blocking, i.e., any one output port not currently receiving data may receive data from any one input port.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventor: Ephrem Wu
  • Patent number: 12271818
    Abstract: Embodiments herein describe a learnable transform block disposed before, or in between, the neural network layers to transform received data into a more computational-friendly domain while preserving discriminative features required for the neural network to generate accurate results. In one embodiment, during a training phase, an AI system learns parameters for the transform block that are then used during the inference phase to transform received data into the computational-friendly domain that has a reduced size input. The transformed data may require less compute resources or less memory usage to process by the underlying hardware device that hosts the neural network.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventors: Kristof Denolf, Alireza Khodamoradi, Kornelis A. Vissers
  • Patent number: 12271670
    Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: April 8, 2025
    Assignee: Xilinx, Inc.
    Inventors: Rajvinder S. Klair, Dhiraj Kumar Prasad, Saikat Bandyopadhyay, Ashish Kumar Jain, Shiyao Ge, Tapodyuti Mandal, Miti Joshi
  • Patent number: 12271332
    Abstract: A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Publication number: 20250110877
    Abstract: The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: William L. Walker, Scott Thomas Bingham, Pongstorn Maidee, William E. Jones, Richard Carlson
  • Publication number: 20250112933
    Abstract: Described herein are systems and methods for managing error detection in a message. A circuit can identify, based on an error detection configuration of the at least one circuit, a first portion of the message to be checked for errors before a second portion of the message is available to the at least one circuit, the first portion being less than all of the message to be checked for one or more errors. A circuit can analyze a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration. A circuit can, based on analyzing the first portion, determine whether the message includes the one or more errors. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Xilinx, Inc.
    Inventors: David Andrews, David Lawrie, Victor Wu, Po-Ching Sun, Dmitri Kitariev, David Riddoch
  • Publication number: 20250104904
    Abstract: Examples herein describe inductor circuitry including an inductor coil having a helical shape. The inductor coil includes a first turn and a second turn which are disposed within an isolation wall. The isolation wall extends above the inductor coil and below the inductor coil. The inductor circuitry includes an inductor leg which extends through an aperture of the isolation wall. The inductor leg includes a first portion which is disposed within the isolation wall and a second portion that is disposed outside of the isolation wall.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: XILINX, INC.
    Inventors: Jing JING, Shuxian WU
  • Publication number: 20250103360
    Abstract: A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to synchronize the request data from an originator clock domain to a transceiver clock domain operating at a higher frequency than the originator clock domain. The first IC includes a first transceiver circuit configured to convey the request data over a communication link that operates asynchronously to the originator clock domain.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: Ananta S. Pallapothu, Raghukul Bhushan Dikshit
  • Publication number: 20250103783
    Abstract: A system-on-chip (SoC) has programmable logic and a processor. A design tool generates configuration data to implement circuitry for emulation of a design-under-test (DUT) on the programmable logic and generates testbench executable code. The testbench executable code is configured to generate stimuli to the circuitry on the programmable logic. The processor can be configured to execute the testbench executable code and the programmable logic can be configured to implement the circuitry for emulation of the DUT.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Applicant: Xilinx, Inc.
    Inventors: Alok Mistry, Anil Kumar A V
  • Patent number: 12259833
    Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: March 25, 2025
    Assignee: XILINX, INC.
    Inventors: Chandrasekhar S. Thyamagondlu, Tao Yu, Chiranjeevi Sirandas, Nicholas Trank
  • Patent number: 12261603
    Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: March 25, 2025
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Publication number: 20250096136
    Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicants: Advanced Micro Devices, Inc., Xilinx, Inc.
    Inventors: Divya Madapusi Srinivas Prasad, Gabriel H. Loh, Richard Schultz, Jeffrey Richard Rearick, Shidhartha Das, Suresh Ramalingam
  • Patent number: 12254253
    Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: March 18, 2025
    Assignee: Xilinx, Inc.
    Inventors: Suman Kumar Timmireddy, Jaipal Reddy Nareddy, Rahul Kunwar, Adithya Balaji Boda
  • Publication number: 20250086007
    Abstract: Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: Xilinx, Inc.
    Inventors: Sumit Nagpal, Abid Karumannil
  • Patent number: 12248761
    Abstract: Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 11, 2025
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Warren E. Cory
  • Patent number: RE50370
    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventors: Alireza Kaviani, Pongstorn Maidee, Ivo Bolsens