Abstract: A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.

Abstract: Embodiments herein describe a 3D splintered physical unclonable function (3D-sPUF). In an example, an integrated circuit (IC) device includes multiple dies in a stacked configuration, and a PUF circuit generates a set of bits that is unique to the PUF circuit based on physical variations of elements of the PUF circuit, where the PUF circuit is distributed amongst two or more of the dies.

Abstract: Bi-directional dynamic function exchange (DFX) can include receiving a circuit design for a programmable integrated circuit (IC). The circuit design includes a plurality of DFX partitions coupled by a signal path. The circuit design can be placed using a first plurality of DFX modules for the plurality of DFX partitions, in part, by selecting a flip-flop of a connection block as a boundary flip-flop of the signal path for each DFX module of the plurality of DFX modules. The circuit design including the signal path can be routed through the selected flip-flops of the connection blocks using a bi-directional routing resource coupling the plurality of connection blocks. The bi-directional routing resource is used as a partition pin placement constraint (PPLOC) node for DFX.

Abstract: Systems and methods for performing multiple locally stored artificial neural network (ANN) computations are provided. An example method comprises receiving, by one or more processing units, an ANN dataset associated with at least one ANN of a plurality of ANNs; storing, by processing units, the ANN dataset in a memory coupled to the processing units; associating, by the processing units, a base address with the at least one ANN, wherein the base address is to be used to locate the ANN dataset in the memory; keeping, by the processing units, the ANN dataset in the memory; receiving, by the processing units, an input dataset and the base address; determining, by the processing units and based on the base address, a location of the ANN dataset in the memory; and performing, by the processing units, ANN computation using the ANN dataset and input dataset.

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

Abstract: Optimizing timing margins across conditions is described. In one or more implementations, a computing system may include an interface circuitry configured to adjust a timing alignment of first and second signals between a central processing unit (CPU) of the system and a device coupled with the CPU and to measure and store one or more margins between the timing alignment and misalignments of the first and second signals. The interface circuitry may be configured to measure and store the timing margins at first and second conditions. The first and second conditions may be different voltages, temperatures, etc. The system may be configured to force the first and/or second condition. The system may be configured to calculate a coefficient from differences in between the margins and between the first and second conditions.

Abstract: In-system electrical connectivity detection. In one or more implementations, a computing device includes a transmitter and a receiver in a package, the transmitter to transmit a signal to a separate device, the receiver to receive and measure a reflection of the transmitted signal, and the measured reflection for characterizing (e.g., testing or detecting) an electrical connection between the computing and separate devices. The computing device may characterize (e.g., detect a discontinuity in) the electrical connection by comparing a magnitude of the transmitted signal with a magnitude of the measured reflection. The computing device may be coupled with the separate device by multiple electrical connections, and the multiple electrical connections may be tested by corresponding transmitters and receivers.

Abstract: Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.

Abstract: Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and/or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.

Abstract: In pruning weights from a neural network (NN), a design tool selects a dt-ds pair from a plurality of dt-ds pairs supported by a target device. Each dt-ds pair specifies a data type, dt, and an associated circuit structure, ds, that is configurable to compute d×s operations in parallel on a set of input activations and a matrix of weights of the data type, d is a number of rows in a sub-matrix of the matrix of weights, s is a number of columns in the sub-matrix, and d×s?1. The design tool selects as pruned weights, one or more subsets of the weights, based at least on each subset of the one or more subsets including d×s weights in the matrix of weights of the layer. If performance of the pruned NN model is satisfactory, the NN is compiled into an execution graph and configuration data.

Abstract: On chip integrated circuit supply voltage regulator has a reference voltage that varies, based on process and temperature conditions of the integrated circuit. Supply voltage is boosted up if the active transistor load devices operate in a Slow-Slow process condition and/or temperature rises. Higher supply voltage improves the system performance (jitter/delay) if the load network includes switching components. If the active transistor load devices operate in a Fast-Fast process condition then the supply voltage is reduced without loss of performance and a savings in power. The variable reference voltage is generated based on process and temperature conditions of the semiconductor integrated circuit devices (transistors). The voltage regulator will automatically have its variable reference voltage adjusted based upon the process condition fabrication and temperature of the areas of the integrated circuit where the active transistor load devices are located.

Abstract: Chip packages and methods for fabricating the same are provided which utilize a first heat spreader interfaced with a first integrated circuit (IC) die and a second heat spreader separately interfaced with a second IC die. The separate heat spreaders allow the force applied to the first IC die to be controlled independent of the force applied to the second IC die.

Abstract: Embodiments herein describe a configurable engine that is embedded into the cache hierarchy of a processor. The configurable engine can enable efficient data sharing between the main memory, cache memories, and the core. The configurable engine can perform operations that are more efficient to be done in the cache hierarchy. In one embodiment, the configurable engine is controlled (or configured) by software (e.g., the operating system (OS)), adapting to each application domain. That is, the OS can configure the engine according to a data flow profile of a particular application being executed by the processor.

Abstract: Embodiments herein describe a circuit including a user domain configured to execute user functions and a hardened domain configured to communicate with the user domain. The hardened domain includes peripheral component interconnect express (PCIe) function decoding logic having a plurality of register bits and a Trusted Execution Environment (TEE) Device Interface Security Protocol (TDISP) core communicating with the PCIe function decoding logic. The TDISP core supports a plurality of PCIe functions. Each register bit of the plurality of register bits is assigned to a respective PCIe function of the plurality of PCIe functions.

Abstract: Embodiments herein describe techniques for setting and using saliency values to modify how a ML model is trained. In one embodiment, different blocks of data (referred to herein as tiles) are assigned respective saliency values. After performing one or more iterations, a training application can modify the default saliency values assigned to the tiles to reflect the importance of the tile. In one embodiment, the training application evaluates a weight gradient that indicates how a weight (or weights) corresponding to each tile are modified and modifies the saliency values accordingly. The ML training system can then use the saliency values to affect future training iterations to reduce the time required to train the ML model or save power.

Abstract: A system for packing data includes a controller configured to receive compressed data. The compressed data includes data items and qualifier bits for the data items. The controller is configured to discard the data items designated as invalid by the qualifier bits. The controller is configured to generate data type bits specifying data type information for the data items designated as valid by the qualifier bits. The system includes a buffer. The controller is configured to store the data items designated as valid by the qualifier bits and the data type bits in the buffer. A system can include one or more decoders configured to decode encoded data and output literals, lengths, and distances.

Abstract: A system includes a plurality of controller circuits. The system includes a plurality of target circuits. The system includes a communication bus communicatively linking the plurality of controller circuits with the plurality of target circuits. The communication bus includes a plurality of switches. Each switch of the plurality of switches is connected to a different one of the plurality of controller circuits.

Abstract: Embodiments herein describe a hardware accelerator with an array of data processing engines (DPEs) which includes a controller (e.g., a microcontroller) for multiple columns of the array. The controllers can be hardened circuitry that executes software code (or firmware) that controls the hardware accelerator. In one embodiment, the task of the controller is to control and orchestrate the functions performed by the hardware accelerator.

Abstract: Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk?1), generates output z-terms 0 through (Nk/2?1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term 2i and the input r-term. The multiply-and-accumulate circuitry in decimation stages k for k?(V?1) provides the output r-term and one or more output z-terms from decimation stage k as the input r-term and one or more input z-terms to the respective multiply-and-accumulate circuitry of decimation stage k+1.

Abstract: An implementation includes an integrated circuit, a network-on-chip (NoC) a plurality of first circuits, each first circuit may include a compressor and a decompressor, the compressor being configured to compress datastreams, and the decompressor being configured to decompress the compressed datastreams, the compressed datastreams may include symbols, the decompressor may include a plurality of symbol decoders configured to decode in parallel the compressed datastreams. The integrated circuit also includes a memory circuit. The circuit also includes a plurality of switches, the plurality of switches being interconnected and communicatively linking the plurality of first circuits with the memory circuit.