Abstract: A memory circuit includes a memory cell including a plurality of inverter pairs. The plurality of inverter pairs include a first inverter pair and one or more reference inverter pairs. The plurality of inverter pairs are coupled by access transistors to same bit lines and to a same word line. The memory circuit includes a detector circuit coupled to the plurality of inverter pairs. The detector circuit is capable of generating an indicator signal in response to detecting a single-event upset (SEU) in the memory cell by detecting a mismatch in stored states among the plurality of inverter pairs of the memory cell. The memory circuit may include a correction circuit capable of correcting an output of the memory cell.

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

Abstract: Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.

Abstract: A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.

Abstract: Embodiments herein describe CRAM validation using an external device (ED). The ED selects unused addresses of CRAM as challenge registers (CRs), determines challenge bits for the CRs, and provides the selected addresses and the challenge bits to challenge circuitry of the IC device. The challenge circuitry initiates storage of the challenge bits at the selected CRAM addresses and invokes scan circuitry to scan the CRAM. The scan circuitry retrieves contents of CRAM addresses used to store configuration bits and contents of the selected CRAM addresses, and provides the contents or a code determined from the contents to the challenge circuitry (i.e., bypassing validation circuitry of scan logic). The challenge circuitry forwards the contents or the code to the ED as a challenge response, and the ED validates the CRAM based on the challenge response and a golden copy of the configuration bits.

Abstract: Automated verification and generation of coverage data for a circuit design includes generating, by computer hardware, valid value ranges for coverpoint variables of a circuit design based on constraints for the coverpoint variables. A regression test is run on the circuit design using a verification testbench to generate test results and sampled values for the coverpoint variables. The sampled values of the coverpoint variables from the regression test are classified by a machine learning model based on the test results. Coverage data for the regression test is generated by the computer hardware by assigning the sampled values of the coverpoint variables to different ones of a plurality of bins based on the classifying.

Abstract: A method of fabricating a chip package is provided, and a chip package fabricated using the same are provided. The method includes connecting a photonic die to a substrate of the chip package and attaching a protection apparatus to the substrate. The method also includes attaching a photonic connector to the photonic die. At least a portion of the photonic connector is disposed inside a housing of the protection apparatus. A fabrication process is performed on the chip package while the photonic connector is inside the housing. After processing, the photonic connector is removed from the housing.

Abstract: A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit implementing a plurality of data paths coupled to respective ones of the plurality of client circuits for conveying the read completion data as scheduled by the read scheduler circuit.

Abstract: An integrated circuit (IC) device includes functional circuits and multiple communication paths, which may include a first communication path through the functional circuits and a second communication path to permit the functional circuits to share information through a buffer and/or to bypass a subset of the functional circuits and a corresponding portion of the first communication path. The IC device may include a variety of protocol-specific interface circuits (ASIC and/or configurable circuitry) for respective IP blocks, and a controller that selectively directs traffic through the various communication paths. The controller may include a set of domain-specific OpCodes that link various subsets/combinations of the protocol-specific interface circuits as respective communication paths. The IC device may include multiple blocks of circuitry, each including a respective set of domain-specific circuitry (e.g.

Abstract: Preplacement clock resolution for implementing a circuit design includes, prior to placement of the circuit design, determining, using computer hardware, pairs of clocks of the circuit design that clock synchronous inter-clock data paths. Using the computer hardware, a clock group is generated that includes clocks having a common ancestor clock node from the pairs of clocks. A clock delay group property is set, using the computer hardware, for the clocks of the clock group prior to placement. A placed version of the circuit design is generated using the computer hardware. The circuit design is placed using the clock delay group property as set for the clocks of the clock group.

Abstract: Embodiments herein describe a method for selectively filtering different wavelengths of optical signals received from an optical channel using cascaded ring resonators, each of the cascaded ring resonators having a first ring and a second ring. The first ring has a varying waveguide width along its length configured to form a first waveguide width portion and a second waveguide width portion, the first waveguide width portion having a greater width than the second waveguide width portion. The second ring has a varying waveguide width along its length configured to form a third waveguide width portion and a fourth waveguide width portion, the fourth waveguide width portion having a greater width than the third waveguide width portion. The method further connects receivers to respective cascaded ring resonators, each of the receivers having a photodetector configured to differentiate between the optical signals.

Abstract: A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Embodiments herein describe a circuit including a passive intermodulation (PIM) model circuit configured to process first data to generate a PIM interference model output to be concatenated with second data, the second data including a first carrier frequency and a second carrier frequency, and the circuit further including a PIM model adapt circuit configured to receive frequency shifted captured data and frequency shifted PIM models to generate updated values to compensate for PIM interference after the PIM interference model output is concatenated with the second data.

Abstract: Embodiments herein describe optimizing a netlist using machine learning (ML) models that predict which of a plurality of optimization strategies (e.g., a plurality of optimization algorithms) will provide the best results. The netlist can then be optimized using the optimization strategy. Doing so provides significant time and compute resources savings since the netlist can be optimized only once using the selected optimization strategy rather than having to be optimized using each of the plurality of optimization strategies. Moreover, the embodiments herein can permit the addition of more optimization strategies, which could not be considered earlier because of runtime constraints.

Abstract: Levels of cross-correlation between pairs of original filters in the layers of a convolutional neural network (CNN) are determined and used in pruning the filters. The pruning includes, for one or more pairs of the pairs of original filters having a level of cross-correlation that satisfies a pruning threshold, determining a scale factor between first and second filters of the one or more pairs, and storing data that identify the first filter, the second filter, and the scale factor. The pruning further includes modifying the initial CNN into a modified CNN by removing the second filter of the one or more pairs and adjusting convolution logic of the CNN, and adding regeneration logic to the modified CNN. The regeneration logic generates an output channel corresponding to the second filter of the one or more pairs based on the scale factor and an output channel produced by the first filter.

Abstract: Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new initial value for the retimed register can be derived based on initial values of registers in a logic cone of the retimed register, and the new initial value can be assigned to the retimed register.

Abstract: A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies connecting IC dies on adjacent die stacks. In one example, a chip package includes an interconnect routing structure, a first die stack and a second die stack. The first die stack includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The second die stack also includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The first bridge die is electrically and mechanically coupled to the top dies of the first and second die stacks. The first bridge die having solid state circuitry that connects circuitries of the top dies of the first and second die stacks.

Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.

Abstract: Implementing a circuit design for a target integrated circuit includes receiving guide information including placement information for a circuit design from a prior implementation flow. A light incremental flow is performed on the circuit design using the guide information. The light incremental flow generates a placed and routed circuit design that re-uses at least a portion of the placement information from the prior implementation flow.

Abstract: Circuitry for multiplying a sparse matrix by a dense vector includes a first switching circuit (302) for routing input triplets from N input ports to N output ports based on column indices of the triplets. Each triplet includes a non-zero value, a row index, and a column index. N first memory banks (303) store subsets of vector elements and are addressed by the column indices of the triplets. N multipliers (305) multiply the non-zero values of the triplets by the vector element read from the respective memory bank. A second switching circuit (304) routes tuples based on row indices of the tuples. Each tuple includes a product output by the one of the N multipliers and a row index output by an output port of the first switching circuit. N accumulator circuits (307) sum products of tuples having equal row indices.