Abstract: A memory includes a read circuit having a first primitive configured to output a first data item based on least significant bits (LSBs) of a read address and a multiplexer coupled to the primitive. The multiplexer outputs a selected bit from the first data item as read data based on most significant bits (MSBs) of the read address. The memory includes a write circuit having a second primitive that outputs a second data item based on LSBs of a write address and a modifier circuit that generates a third data item by modifying a bit of the second data item to correspond to write data. The bit is at a location within the second data item selected based on MSBs of the write address. The modifier circuit writes the third data item to a location in the write primitive based on the LSBs of the write address.

Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.

Abstract: A method of attaching a chip package to a printed circuit board (“PCB”) is provided, along with an electronic device fabricated using the method. The method includes measuring a warpage parameter of the chip package and selecting a stencil configured to compensate for warpage corresponding to the measured warpage parameter. The stencil includes a plurality of apertures. The selected stencil is positioned above the PCB, and solder paste is applied on the PCB via the plurality of apertures of the stencil. Thereafter, the PCB is moved away from the stencil. The chip package is positioned on the solder paste on the PCB, thereby attaching the chip package to the PCB.

Abstract: A non-blocking crossbar switch architecture circumvents the problem present in prior art crossbar switches where input signals may oversubscribe the available inter-die bandwidth. The new non-blocking crossbar switch architecture is split across a plurality of semiconductor dice, including a plurality of interleaved crossbar switch segments. Only one crossbar switch segment is implemented on each semiconductor die. A plurality of input ports and output ports are coupled to the crossbar switch. The crossbar switch is non-blocking, i.e., any one output port not currently receiving data may receive data from any one input port.

Abstract: A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

Abstract: Embodiments herein describe a learnable transform block disposed before, or in between, the neural network layers to transform received data into a more computational-friendly domain while preserving discriminative features required for the neural network to generate accurate results. In one embodiment, during a training phase, an AI system learns parameters for the transform block that are then used during the inference phase to transform received data into the computational-friendly domain that has a reduced size input. The transformed data may require less compute resources or less memory usage to process by the underlying hardware device that hosts the neural network.

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

Abstract: Described herein are systems and methods for managing error detection in a message. A circuit can identify, based on an error detection configuration of the at least one circuit, a first portion of the message to be checked for errors before a second portion of the message is available to the at least one circuit, the first portion being less than all of the message to be checked for one or more errors. A circuit can analyze a number of bits of the first portion of the message using the at least one circuit and based on the error detection configuration. A circuit can, based on analyzing the first portion, determine whether the message includes the one or more errors. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system-on-chip (SoC) has programmable logic and a processor. A design tool generates configuration data to implement circuitry for emulation of a design-under-test (DUT) on the programmable logic and generates testbench executable code. The testbench executable code is configured to generate stimuli to the circuitry on the programmable logic. The processor can be configured to execute the testbench executable code and the programmable logic can be configured to implement the circuitry for emulation of the DUT.

Abstract: Examples herein describe inductor circuitry including an inductor coil having a helical shape. The inductor coil includes a first turn and a second turn which are disposed within an isolation wall. The isolation wall extends above the inductor coil and below the inductor coil. The inductor circuitry includes an inductor leg which extends through an aperture of the isolation wall. The inductor leg includes a first portion which is disposed within the isolation wall and a second portion that is disposed outside of the isolation wall.

Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.

Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.

Abstract: Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.

Abstract: Scheduling kernels on a system with heterogeneous compute circuits includes receiving, by a hardware processor, a plurality of kernels and a graph including a plurality of nodes corresponding to the plurality of kernels. The graph defines a control flow and a data flow for the plurality of kernels. The kernels are implemented within different ones of a plurality of compute circuits coupled to the hardware processor. A set of buffers for performing a job for the graph are allocated based, at least in part, on the data flow specified by the graph. Different ones of the kernels as implemented in the compute circuits are invoked based on the control flow defined by the graph.

Abstract: Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.

Abstract: Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.

Abstract: Control set optimization for a circuit design includes generating, by a processor, Observability Don't Care (ODC) expressions for registers of the circuit design. Redundant reset pins of the registers of the circuit design are determined by the processor by iteratively checking, on a per-cube and a per-literal basis for each ODC expression, whether a value of a literal causes the ODC expression to evaluate to 1. A modified version of the circuit design is generated by the processor by connecting one or more reset pins of the set of redundant reset pins to one or more constants.

Abstract: Generating low skew clock solutions for local clocks in an integrated circuit includes, for a circuit design, determining a plurality of delay ranges for respective clock pins of a local clock net. Each delay range of the plurality of delay ranges includes an upper bound delay and a lower bound delay. The upper bound delays of the plurality of delay ranges are allocated as setup constraints for the respective clock pins of the local clock net. The lower bound delays are allocated as hold constraints for the respective clock pins of the local clock net. The local clock net is routed using the setup constraints and the hold constraints.

Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.