Patents Assigned to Xilinx, Inc.
  • Patent number: 11409569
    Abstract: A data processing system being configured to select between different hardware resources for the running of an application configured for the sending and receiving of data over a network. The selection of hardware resources may be between resources on the network interface device, and hardware resources on the host. The selection of hardware resources may be between first and second hardware resources on the network interface device. An API is provided in the data processing system that responds to requests from the application irrespective of the hardware on which the application is executing.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 9, 2022
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
  • Patent number: 11403068
    Abstract: Apparatus and associated methods relate to determining a natural exponent from a digital word input by splitting the digital word, and retrieving a precalculated and predetermined value from a data store at an address defined by the first word. In an illustrative example, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by the second word. The hyperbolic sum may be scaled, and summed with the multiplication result to generate a scaled exponential value. The scaled exponential value may be scaled to produce an exponential value representing eX. In various examples, the digital word input may be in a fixed point or a floating point format, or converted therebetween. In various embodiments, the data store may be a lookup table. Various examples may provide a compact and versatile architecture for determining a natural exponent with minimized hardware resources.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 2, 2022
    Assignee: XILINX, INC.
    Inventor: Stefano Cappello
  • Patent number: 11403447
    Abstract: Rebuilding a next compile-time Intellectual Property (IP) core can include determining an IP core included in a runtime design for an integrated circuit (IC) by evaluating metadata of the runtime design. The IP core specifies a circuit configured for implementation in programmable circuitry of the IC. Source code for the IP core may be retrieved automatically based on source data read from the metadata. A new instance of the IP core, including the source code, may be generated in a memory. The new instance of the IP core may be included within a new compile time design.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: August 2, 2022
    Assignee: Xilinx, Inc.
    Inventors: Graham F. Schelle, Patrick Lysaght, Yun Qu
  • Patent number: 11403429
    Abstract: Controlling functionality of a core on a per-instance basis can include implementing, within an accelerator, an instance of a core by configuring the accelerator using configuration data, receiving, within the instance of the core, encrypted authorization data for the instance of the core, generating, using control circuitry of the instance of the core, decrypted authorization data for the instance of the core by decrypting the encrypted authorization data using a core instance identifier stored in a first control register of the instance of the core, and writing the decrypted authorization data to a second control register in the instance of the core, wherein the instance of the core enables core functionality therein based on the decrypted authorization data in the second control register.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 2, 2022
    Assignee: Xilinx, Inc.
    Inventors: David Robinson, Raymond Kong
  • Patent number: 11405617
    Abstract: Methods and systems for improving encoding of a picture or a frame are disclosed. According to one embodiment, a method for encoding video frames includes receiving for a frame, several binarized symbols that include a number of bins corresponding to one or more contexts. For each context from one or more contexts, the method includes entropy encoding in a first pass bins associated with the context using an initial probability distribution for the context; generating counts of zeros and ones in a set of bins associated with the context; updating the initial probability distribution using the respective counts of zeros and ones, to obtain an updated probability distribution; and entropy encoding in a second pass the bins associated with the context using the updated probability distribution, to provide at least a part of an encoded bitstream.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Xilinx, Inc.
    Inventor: Akrum Elkhazin
  • Patent number: 11398469
    Abstract: Examples described herein generally relate to devices that include electrostatic discharge (ESD) protection in a chip stack. In an example, a device includes a chip stack including first and second chips, ground and power supply voltage nodes, and first and second resistor-capacitor (RC) clamps. The second chip is disposed on and attached to the first chip. The ground and power supply voltage nodes are connected between and extend in the first and second chips, and are connected to the ground and power supply voltage exterior connector pads, respectively, of the first chip. The first and second RC clamps are disposed in the first and second chips, respectively. The first and second RC clamps are connected to and between the ground node and the power supply voltage node. An RC-time constant of the second RC clamp is less than an RC-time constant of the first RC clamp.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 26, 2022
    Assignee: XILINX, INC.
    Inventor: James Karp
  • Patent number: 11398934
    Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.
    Type: Grant
    Filed: September 18, 2021
    Date of Patent: July 26, 2022
    Assignee: XILINX, INC.
    Inventors: Ronan Sean Casey, Lokesh Rajendran, Declan Carey, Kevin Zheng, Catherine Hearne, Hongtao Zhang
  • Patent number: 11394664
    Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: July 19, 2022
    Assignee: Xilinx, Inc.
    Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch, Dmitri Kitariev
  • Patent number: 11392429
    Abstract: A data processing system comprising: an operating system providing an application programming interface; an application supported by the operating system and operable to make calls to the application programming interface; an intercept library configured to intercept calls of a predetermined set of call types made by the application to the application programming interface; and a configuration data structure defining at least one action to be performed for each of a plurality of sequences of one or more calls having predefined characteristics, the one or more calls being of the predetermined set of call types; wherein the intercept library is configured to, on intercepting a sequence of one or more calls defined in the configuration data structure, perform the corresponding action(s) defined by the configuration data structure.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 19, 2022
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, David J. Riddoch, Kieran Mansley
  • Patent number: 11394393
    Abstract: A DAC cell includes first and second transistors, drain-source coupled at a first node, a gate of the second transistor coupled to a data input (D), and third and fourth transistors, drain-source coupled at a second node, a gate of the fourth transistor coupled to a complement of the data input (DB). The circuit further includes first and second shadow transistors each coupled between the first node and ground, a gate of the first shadow transistor coupled to a switching input (S) and a gate of the second shadow transistor coupled to a complement of the switching input (SB). The circuit still further includes third and fourth shadow transistors each coupled between the second node and ground, a gate of the third shadow transistor coupled to S and a gate of the fourth shadow transistor coupled to SB.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 19, 2022
    Assignee: XILINX, INC.
    Inventors: Abhirup Lahiri, Roberto Pelliconi
  • Patent number: 11394768
    Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Xilinx, Inc.
    Inventors: Steven L. Pope, Derek Roberts, David J. Riddoch
  • Patent number: 11386644
    Abstract: An example preprocessor circuit includes: a first buffer configured to store rows of image data and output a row thereof; a second buffer, coupled to the first buffer, including storage locations to store respective image samples of the row output by the first buffer; shift registers; an interconnect network including connections, each connection coupling a respective one of the shift registers to more than one of the storage locations, one or more of the storage locations being coupled to more than one of the connections; and a control circuit configured to load the shift registers with the image samples based on the connections and shift the shift registers to output streams of image samples.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: Elliott Delaye, Ashish Sirasao, Aaron Ng, Yongjun Wu, Jindrich Zejda
  • Patent number: 11385287
    Abstract: Examples described herein provide a method for evaluating a programmable logic device (PLD) for compatibility with user designs. The method includes using a processor-based system: obtaining an indication of one or more failure bits of configuration memory of a programmable logic device (PLD); determining whether each of the one or more failure bits corresponds to a configuration memory bit to be used by a first PLD user design; if any of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as unusable for the first PLD user design; and if none of the one or more failure bits corresponds to a configuration memory bit to be used by the first PLD user design, classifying the PLD as usable for the first PLD user design.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: Andreas L. Astuti, Jian Jun Shi, Tho Le La
  • Patent number: 11386020
    Abstract: Some examples described herein relate to programmable devices that include a data processing engine (DPE) array that permits shifting of where an application is loaded onto DPEs of the DPE array. In an example, a programmable device includes a DPE array. The DPE array includes DPEs and address index offset logic. Each of the DPEs includes a processor core and a memory mapped switch. The processor core is programmable via one or more memory mapped packets routed through the respective memory mapped switch. The memory mapped switches in the DPE array are coupled together to form a memory mapped interconnect network. The address index offset logic is configurable to selectively modify which DPE in the DPE array is targeted by a respective memory mapped packet routed in the memory mapped interconnect network.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: Matthew H. Klein, Goran Hk Bilski, Juan Jose Noguera Serra, Ismed D. Hartanto, Sridhar Subramanian, Tim Tuan
  • Patent number: 11386009
    Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: David P. Schultz, Weiguang Lu, Karthy Rajasekharan, Shidong Zhou, Michael Tsivyan, Jing Jing Chen, Sourabh Goyal
  • Patent number: 11387539
    Abstract: The present invention provides an antenna system (100, 200, 211, 300, 400, 500, 600) for attachment to an antenna pole (250, 350), the antenna system (100, 200, 211, 300, 400, 500, 600) comprising a cooling arrangement (101, 201, 212, 301, 401, 501, 601), an active electronic arrangement (102, 202, 213, 302, 402, 502, 602) that comprises a number of antenna elements (103, 104) and a number of receivers and/or transmitters for the antenna elements (103, 104), wherein the active electronic arrangement (102, 202, 213, 302, 402, 502, 602) is releasably attachable to the cooling arrangement (101, 201, 212, 301, 401, 501, 601). Further, the present invention provides a communication system (210) and a method for manufacturing an antenna system (100, 200, 211, 300, 400, 500, 600).
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventor: Peter Meyer
  • Patent number: 11386031
    Abstract: Embodiments herein describe techniques for separating data transmitted between I/O functions in an integrated component and a host into separate data paths. In one embodiment, data packets are transmitted using a direct data path that bypasses a switch in the integrated component. In contrast, configuration packets (e.g., hot-swap, hot-add, hot-remove data, some types of descriptors, etc.) are transmitted to the switch which then forwards the configuration packets to their destination. The direct path for the data packets does not rely on switch connectivity (and its accompanying latency) to transport bandwidth sensitive traffic between the host and the I/O functions, and instead avoids (e.g., bypasses) the bandwidth, resource, store/forward, and latency properties of the switch. Meanwhile, the software compatibility attributes, such as hot plug attributes (which are not latency or bandwidth sensitive), continue to be supported by using the switch to provide a configuration data path.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 12, 2022
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 11386034
    Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Xilinx, Inc.
    Inventors: Sonal Santan, Ravi N. Kurlagunda, Min Ma, Himanshu Choudhary, Manjunath Chepuri, Cheng Zhen, Pranjal Joshi, Sebastian Turullols, Amit Kumar, Kaustuv Manji, Ravinder Sharma, Ch Vamshi Krishna
  • Patent number: 11388270
    Abstract: A physical (PHY) circuit can include a Physical Medium Dependent (PMD) circuit, the PMD circuit having a receiver and a transmitter, a Physical Medium Attachment (PMA) circuit coupled to the PMD circuit, and a plurality of Physical Coding Sublayer (PCS) circuits coupled to the PMA circuit, wherein each PCS circuit is configured to implement a different communication protocol. The PHY circuit can also include an auto-negotiation circuit coupled to the PMD circuit, wherein the auto-negotiation circuit is configured to determine a selected communication protocol compatible with a link partner device from a plurality of communication protocols by configuring the receiver to operate at different data rates over time, the different data rates corresponding to different ones of the plurality of communication protocols.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: July 12, 2022
    Assignee: Xilinx, Inc.
    Inventors: Veerender Kumar Soma, Ajay V. Sharma, Sunil K. Pattanaik
  • Patent number: RE49163
    Abstract: An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 9, 2022
    Assignee: XILINX, INC.
    Inventors: Alireza S. Kaviani, Pongstorn Maidee, Ivo Bolsens