Patents Assigned to Xilinx, Inc.
  • Patent number: 10999303
    Abstract: A data analytical engine receives packets from a number of different network interface devices. The data is a replica of part or all of transmit or receive packets processed in the network interface device. A learning algorithm is applied to data from said different network interface devices and it is determined if an alert is to be generated.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 4, 2021
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
  • Patent number: 10999246
    Abstract: A logic device and method are provided for intercepting a data flow from a network source to a network destination. A data store holds a set of compliance rules and corresponding actions. A packet inspector is configured to inspect the intercepted data flow and identify from the data store a compliance rule associated with the inspected data flow. A packet filter is configured to, when the data flow is identified as being associated with a compliance rule, carry out an action with respect to the data flow corresponding to the compliance rule.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Steven Leslie Pope, Derek Edward Roberts, David James Riddoch
  • Patent number: 10998864
    Abstract: An apparatus for generating an output current including a first distortion current based on a first transconductance and a second distortion current based on a second transconductance is disclosed. The first distortion current may be generated by an amplifier and the second distortion current may be generated by a distortion compensator. The second transconductance may be less than the first transconductance. In some implementations, the second distortion current may reduce the first distortion current output by the apparatus.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc
    Inventors: Roswald Francis, Christophe Erdmann
  • Patent number: 10998904
    Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Sundeep Ram Gopal Agarwal, Brian C. Gaide, Ramakrishna Kishore Tanikella
  • Patent number: 10998307
    Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Kevin Zheng, Chuen-Huei Chou, Hsung Jai Im
  • Publication number: 20210124711
    Abstract: An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Applicant: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Sagheer Ahmad
  • Patent number: 10990555
    Abstract: Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing the data. For less time critical nets, the net can route through the bypass path. This means the route from the hardened block to the PL fabric is determined on the fly by a routing algorithm rather than being fixed.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Aashish Tripathi, Sundeep Ram Gopal Agarwal
  • Patent number: 10990552
    Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Goran Hk Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Philip B. James-Roxby, Christopher H. Dick
  • Patent number: 10991417
    Abstract: A system includes a queue and a controller. The queue receives a transactions from masters to access a memory component. The memory component includes a plurality of rows. The controller issues a command to access a row of the plurality of rows in response to receiving a first issued transaction. The first issued transaction is issued by a first master. The controller is configured to prevent issuing an auto-precharge command to keep the row associated with the first issued transaction open if a subsequent transaction in the queue from the first master accesses a same row as the first transaction. The controller is configured to prevent issuing the auto-precharge command to keep the row associated with the first issued transaction open if the controller receives data associated with keeping the row associated with the first issued transaction open.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventor: Ygal Arbel
  • Patent number: 10990736
    Abstract: Implementing a circuit design can include detecting, using computer hardware, a re-convergent section of a circuit design, masking, using the computer hardware, a sequential circuit element of the re-convergent section located between a start and an end of the re-convergent section, and performing, using the computer hardware, an optimization operation on combinatorial logic of the re-convergent section to create optimized combinatorial logic. Using the computer hardware, the optimized combinatorial logic of the re-convergent section can be mapped. Further, the re-convergent section can be modified subsequent to the mapping to match timing of the re-convergent section prior to the masking.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chaithanya Dudha, Satyaprakash Pareek, Krishna Garlapati, Ashish Sirasao
  • Patent number: 10990547
    Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.
    Type: Grant
    Filed: August 11, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Chandrasekhar S. Thyamagondlu, Ravi Sunkavalli, Ravi N. Kurlagunda, Ellery Cochell
  • Patent number: 10990517
    Abstract: Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores contents associated with the addresses for write requests and returns contents associated with the addresses for a read request to the programmable device. The programmable device returns the received contents to the host for processing.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: April 27, 2021
    Assignee: XILINX, INC.
    Inventors: Hare K. Verma, Jiayou Wang, Vincent Mirian
  • Patent number: 10990826
    Abstract: Detecting objects in video may include receiving object detections for a plurality of selected frames of a video from a still image detector, wherein the plurality of selected frames are non-adjacent frames of the video, propagating the object detections from the plurality of selected frames to sequential frames of the video adjacent to the plurality of selected frames based on a distance metric and vector flow data for the sequential frames, suppressing false positive object detections from the propagating, and outputting resulting object detections for the sequential frames of the video.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Xilinx, Inc.
    Inventors: Mujib Haider, Venkata V. Dhanikonda, Ashish Sirasao
  • Patent number: 10985764
    Abstract: An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: April 20, 2021
    Assignee: XILINX, INC.
    Inventors: Winson Lin, Jin Namkoong, Hongtao Zhang
  • Patent number: 10983920
    Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 20, 2021
    Assignee: XILINX, INC.
    Inventors: Chandrasekhar S Thyamagondlu, Darren Jue, Tao Yu, John West, Hanh Hoang, Ravi Sunkavalli
  • Patent number: 10984500
    Abstract: An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a plurality of memory banks configured to store the image data; multiplexer circuitry coupled to the memory banks; a first plurality of registers coupled to the multiplexer circuitry; a second plurality of registers coupled to the first plurality of registers, outputs of the second plurality of registers configured to provide the plurality of streams of image samples; bank address and control circuitry coupled to control inputs of the plurality of memory banks, the multiplexer circuitry, and the first plurality of registers; output control circuitry coupled to control inputs of the second plurality of registers; and a control state machine coupled to the bank address and control circuitry and the output control circuitry.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 20, 2021
    Assignee: XILINX, INC.
    Inventors: Ashish Sirasao, Elliott Delaye, Aaron Ng, Ehsan Ghasemi
  • Patent number: 10977404
    Abstract: Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Srinivas T. Reddy, Dinesh Gaitonde, Ritesh Mani
  • Patent number: 10979210
    Abstract: Techniques for handling synchronization headers for serial data transmission with multi-level signaling are described. In an example, a transmitter includes a multiplexer circuit configured to serialize an input signal to generate an output bit sequence having a plurality of bits between pairs of synchronization header bits. The transmitter includes a re-ordering circuit, coupled to the multiplexer circuit to receive the output bit sequence, configured to re-order the output bit sequence by moving at least one of the plurality of bits between the synchronization header bits in each of the pairs of synchronization header bits. The transmitter includes an output driver circuit configured to drive the re-ordered output bit sequence onto a transmission medium.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventor: Ben J. Jones
  • Patent number: 10977401
    Abstract: Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 13, 2021
    Assignee: XILINX, INC.
    Inventors: Jeffrey M. Arnold, Stephen L. Bade, Srinivas Beeravolu, Chukwuweta Chukwudebe, Anindita Patra, Nabeel Shirazi
  • Patent number: 10977018
    Abstract: Implementing an application within a heterogeneous device can include receiving an application specifying a plurality of hardware accelerators and having a plurality of sections corresponding to different subsystems of the heterogeneous device, wherein the plurality of sections are specified using different programming models. Compiling each section based on the programming model of the section and the subsystem of the heterogeneous device corresponding to the section into an accelerator representation. Linking the accelerator representations based on a platform of the heterogeneous device, generating a hardware implementation of the application for the heterogeneous device based on the linked accelerator implementations, and automatically generating program code configured to control one or more of the plurality of hardware accelerators of the hardware implementation.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: L. James Hwang, Michael Gill, Tom Shui, Jorge E. Carrillo, Alfred Huang, Sudipto Chakraborty