Abstract: A memory system that splits a data width (W) into N separate memories each of narrower width W/N is described. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. A fault on the WE signal to any of the N memories results in its stored write detection bit being different from the write detection bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the write detection bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.

Abstract: Embodiments herein describe a self-reliant Network Interface Controller (NIC) that can perform the maintenance and control operations part of performing a distributed computation which relies on data received from multiple peers (or nodes) that are connected by a network. Rather than a CPU-driven adaptive compute where the CPU(s) in a host perform maintenance and control operations, the embodiments herein shift these operations to the NIC. The NIC can perform control operations such as determining when data has been received from remote peers, or a compute task has been completed and then inform the host CPU when the operation is complete.

Abstract: The disclosed computer-implemented method for decentralized address translation can include receiving, by at least one processor implemented outside a processor core, a virtual address translation request. The method can additionally include, retrieving, by the at least one processor and in response to the virtual address translation request, a physical address. The method can also include returning, by the at least one processor, the physical address. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

Abstract: Embodiments herein describe a host that polls a network adapter to receive data from a network. That is, the host/CPU/application thread polls the network adapter (e.g., the network card, NIC, or SmartNIC) to determine whether a packet has been received. If so, the host informs the network adapter to store the packet (or a portion of the packet) in a CPU register. If the requested data has not yet been received by the network adapter from the network, the network adapter can delay the responding to the request to provide extra time for the adapter to receive the data from the network.

Abstract: Disclosed approaches for accumulating pre-carry data include initializing hold sum to a sum of a LSB of the first pre-carry word of an input stream and an MSB of a second pre-carry word by a pre-carry processing circuit. For successive pre-carry words, the LSB of pre-carry word i and the MSB of pre-carry word i+1 are summed into a next sum. An FFcount is incremented by an adder circuit if the LSB of the next sum is equal to 0xFF. If the LSB of the next sum is not equal to 0xFF, the pre-carry processing circuit outputs either: the hold sum followed by FFcount consecutive 0xFF values, if the MSB of the next sum is equal to 0x00, or the hold sum plus one, followed by FFcount consecutive 0x00 values, if the MSB of the next sum is not equal to 0x00. If the LSB of the next sum is not equal to 0xFF, the hold sum is updated with the LSB of the next sum, and the FFcount is reset to 0. Processing repeats for successive pre-carry words in the stream.

Abstract: The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.

Abstract: Disclosed herein is a chip package and method for fabricating the same are provided that includes a redistribution layer (RDL) with a plurality of loop and void structures. The chip package includes an integrated circuit (IC) die, and a package substrate. The RDL is disposed between the IC die and the package substrate. The RDL has RDL circuitry that connects the IC die to the package substrate. The RDL circuitry includes a first coil formed in a first metal layer and a second coil formed in a second metal layer. A first end of the second coil is coupled to a second end of the first coil by a first via. A second end of the second coil is the IC die.

Abstract: Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.

Abstract: Described herein are systems and methods for scalable communications. A circuit can receive a request from an application to communicate with a destination over a network. The circuit can identify the destination from information included in the request. In a first case that resources have been allocated for communicating with the destination identified from the request, the circuit can communicate data to the destination over the network using the resources that have been allocated. In a second case that resources have not been allocated for communicating with the destination identified from the request, the circuit can allocate resources for communicating the data with the destination. The circuit can communicate the data to the destination over the network using the resources that have been allocated.

Abstract: Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO memory models during runtime of the simulation of the compiled design. FIFO memory requirements for one or more nets of the design are determined from the FIFO memory usage data and the compiled design.

Abstract: Disclosed approaches for rendering event data from subsystems in different clock domains according to a system-level timeline include, for each of multiple subsystems, sampling a system timer in a first clock domain for a first timestamp by a host processor. A host processor requests a subsystem timestamp from a subsystem timer in each of the subsystems. The subsystem timestamp is associated with the first timestamp, and the subsystem timer operates in a clock domain different from the first clock domain. The host processor translates timestamps in traced event data of the subsystems to a timeline of the system timer using the first timestamp and associated subsystem timestamps.

Abstract: The disclosed computer-implemented method for decentralized address translation can include receiving, by at least one processor implemented outside a processor core, a virtual address translation request. The method can additionally include, retrieving, by the at least one processor and in response to the virtual address translation request, a physical address. The method can also include returning, by the at least one processor, the physical address. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A network-on-chip (NoC) includes a switch. The switch includes a first sub-switch, a second sub-switch, and a synchronization channel coupled to the first sub-switch and the second sub-switch. The first sub-switch and the second sub-switch are coupled to corresponding sub-switches in at least one other switch included in the NoC. Each of the first sub-switch and the second sub-switch includes ports in north, south, east, and west directions. The first sub-switch and the second sub-switch exchange flits of data through an additional port of the first sub-switch coupled to an additional port of the second sub-switch.

Abstract: Mitigation of controls set packing includes generating an Observability Don't Care (ODC) expression for a target register of a circuit design. The target register has an original reset signal that is a constant. A plurality of supports of the ODC expression that are driven by driver registers are grouped into a plurality of groups. Each group of the plurality of groups includes only supports that are driven by driver registers having a same reset signal. A control set of each group is different from a control set of the target register. The reset signal of a selected group of the plurality of groups is designated as a candidate reset signal for the target register based on an evaluation of the ODC expression. The circuit design is modified by connecting the candidate reset signal to the target register in place of the original reset signal.

Abstract: Receiver circuitry for mitigating effects associated with the phase differences between a capture clock signal and the receipt of a data signal includes first data path circuitry, second data path circuitry, and phase alignment circuitry. The first data path circuitry receives a first data signal based on a capture clock signal. The second data path circuitry receives a second data signal based on the capture clock signal. The phase alignment circuitry adjusts the phase of a first launch clock signal and a second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively. The phase alignment circuitry adjusts a phase of the capture clock signal relative to one of the first and the second launch clock signals based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.

Abstract: Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer and a second eviction condition. In response to detecting the eviction event, a descriptor list from the set of candidate descriptor lists is selected for eviction. The selected descriptor list can be evicted from the cache memory.

Abstract: A disclosed method may include initializing a deep learning recommendation model (DLRM) comprising a plurality of embedding tables, each embedding table comprising a plurality of embeddings. The method may also include receiving input data associated with accessing embeddings from the plurality of embedding tables and applying a parallelization strategy to process the plurality of embedding tables, the parallelization strategy configured to improve performance by distributing computational workloads and optimizing memory access. The method may also include processing the embeddings based on the input data in accordance with the parallelization strategy, the processing comprising aggregating embeddings accessed from the plurality of embedding tables. The method may also include generating, for further processing, output data based on the processed embeddings. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Routing a circuit design includes generating a graph of the circuit design where each connected component is represented as a vertex, generating a routing solution for the circuit design by routing packet-switched nets so that the packet-switched nets of a same connected component do not overlap, and, for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge. Cycle detection may be performed on the graph. For each cycle detected on the graph, the cycle may be broken by deleting the edge from the graph and ripping-up a portion of the routing solution corresponding to the deleted edge. The circuit design, or portion thereof, for which the routing solution was ripped up may be re-routed using an increased cost for a shared routing resource freed from the ripping-up.