PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes a first redistribution structure, a chip, an insulation encapsulation and a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.
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This application claims the priority benefit of U.S. provisional application Ser. No. 62/484,907, filed on Apr. 13, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
BACKGROUND OF THE INVENTION 1. Field of the InventionThe present invention generally relates to a package structure and a display, in particular, to a package structure having a protection layer.
2. Description of Related ArtWith advancement of the technology, the electronic product has been designed to achieve being light, slim, short, and small, so as to develop products that are smaller in volume, lighter in weight, higher in integration, and more competitive in the market. As the products gradually shrinkage in volume, the risk of malfunction or failure of the electronic chip due to crack or warpage is increased accordingly. As such, how to miniature the package structure while maintaining the reliability and the functionality of the package, so as to lower the risk of failure of the final products, has become a challenge to those researchers in the field.
SUMMARY OF THE INVENTIONAccordingly, the present invention is directed to a package structure and a manufacturing method thereof, which can lower the risk of malfunction or failure of a package structure of the chip and enhance the reliability thereof.
The present invention provides a package structure including a first redistribution structure, a chip, an insulation encapsulation, a protection layer. The first redistribution structure has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the first redistribution structure and has an active surface and a rear surface opposite to the active surface. The insulation encapsulation encapsulates the chip and the first surface of the first redistribution structure. The protection layer is directly disposed on the rear surface of the chip.
The present invention provides a manufacturing method of a package structure. The method includes at least the following steps. A first carrier substrate is provided. A first redistribution structure having a first surface and a second surface opposite to the first surface is formed on the first carrier substrate. The first surface is attached to the first carrier substrate. A second carrier substrate attached to the second surface of the first redistribution structure is provided. The first redistribution structure is separated from the first carrier substrate. A chip is disposed onto the first surface of the first redistribution structure. The chip has an active surface and a rear surface opposite to the active surface. A protection layer is formed on the rear surface, and the active surface is adhered to the first surface of the first redistribution structure.
Base on the above, the protection layer is formed on the rear surface of the chip. Accordingly, the chip is strengthened to sufficiently alleviate the warpage issues during the manufacturing process of the package structure. Moreover, since the issues of the warpage of the chip are alleviated, the flip-chip bonding yield may be improved to avoid the non-joint issue. As result, the overall strength of the chip having the protection layer disposed thereon is enhanced.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
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Referring to 1I and 1J, the second carrier substrate 80 is detached from the second surface 100b of the first redistribution structure 100 through the release layer 90 to form a package structure 10 as shown in
In the embodiment, a coefficient of thermal expansion (CTE) of the protection layer 600 is smaller than polyimide but larger than molding compound and silicon materials. For example, the CTE of the protection layer 600 ranges between 5 ppm/° C. and 40 ppm/° C. Accordingly, the protection layer 600 can reduce the risk of chip cracking or chipping during the sawing process of the wafer 500′. In addition, the protection layer 600 can be used as a buffer layer to reduce the chip 500 warpage and enhance the flip-chip bonding process yield to avoid non-joint risk, especially for a large-sized chip. Specifically, as the issues of the warpage of the chip 500 is alleviated, the chip 500 may be bonded to the trace layer 121 of the first redistribution structure 100 with fine-pitch line and space patterns by the aid of the alignment processes.
In the present embodiment, the protection layer 600 may be made of materials similar to the insulation encapsulation 700, such as molding compound. Therefore, the protection layer 600 and the insulation encapsulation 700 may have similar properties. As such, the life time of the mold grinding wheel applying in the thinning/grinding process of the insulation encapsulation 700 and the protection layer 600 may be elongated. Furthermore, the protection layer 600 may have good thermal conductivity, which ranges between 2 W/m-k and 5 W/m-k, to enhance the thermal dissipation performance of the package structure 20.
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In light of the foregoing, the package structure may include the first redistribution structure, the second redistribution structure and the chip. The second redistribution structure is disposed above the first redistribution structure. The chip is disposed and encapsulated between the first redistribution structure and the second redistribution structure and has an active surface and a rear surface opposite to each other. In addition, the package structure includes a package layer disposed on the rear surface of the chip.
In the manufacturing process of the package structure, the protection layer can prevent the chip from cracking or chipping during the wafer sawing process. In addition, as the chip is flip-chip bonded to the first redistribution structure, the protection layer can alleviate the issues of chip cracking and chip warpage, and the flip-chip bonding yield may be improved to avoid the non-joint issue, thereby enhancing the overall strength of the package structure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Claims
1. A package structure comprising:
- a first redistribution structure having a first surface and a second surface opposite to the first surface;
- a chip, disposed on the first surface of the first redistribution structure and having an active surface and a rear surface opposite to the active surface;
- an insulation encapsulation, encapsulating the chip and the first surface of the first redistribution structure; and
- a protection layer, directly disposed on the rear surface of the chip.
2. The package structure according to claim 1, wherein the first redistribution structure comprises at least one dielectric layer and a plurality of first conductive elements disposed in the at least one dielectric layer, and the chip is electrically connected to the first conductive elements exposed on the first surface.
3. The package structure according to claim 2, further comprising a plurality of bumps, disposed between the active surface and the first surface of the first redistribution structure and electrically connected to the first conductive elements respectively.
4. The package structure according to claim 3, wherein the surfaces of the bumps facing the first surface are substantially coplanar with a surface of the insulation encapsulation.
5. The package structure according to claim 1, further comprising a second redistribution structure, disposed above the rear surface of the chip, the protection layer, and the insulation encapsulation.
6. The package structure according to claim 5, further comprising a plurality of conductive pillars, surrounding the chip and disposed between the first redistribution structure and the second redistribution structure.
7. The package structure according to claim 6, wherein the second redistribution structure comprises at least one dielectric layer and a plurality of second conductive elements disposed in the at least one dielectric layer, and the chip is electrically connected to the second conductive elements through the first redistribution structure and the conductive pillars.
8. The package structure according to claim 1, further comprising an underfill, disposed between the first surface of the first redistribution structure and the active surface of the chip.
9. The package structure according to claim 1, wherein a thickness of the protection layer ranges between 5 μm and 30 μm.
10. The package structure according to claim 1, wherein the chip is electrically connected to the first redistribution structure through a flip-chip bonding process.
11. A manufacturing method of a package structure, comprising:
- providing a first carrier substrate;
- forming a first redistribution structure having a first surface and a second surface opposite to the first surface on the first carrier substrate, wherein the first surface is attached to the first carrier substrate;
- providing a second carrier substrate attached to the second surface of the first redistribution structure;
- separating the first redistribution structure from the first carrier substrate; and
- disposing a chip on the first surface of the first redistribution structure, wherein the chip has an active surface and a rear surface opposite to the active surface, a protection layer is directly formed on the rear surface, and the active surface of the chip is adhered to the first surface of the first redistribution structure.
12. The method according to claim 11, further comprising forming a first release layer between the first carrier substrate and the first redistribution structure.
13. The method according to claim 11, further comprising forming a second release layer between the second carrier substrate and the second surface of the first redistribution structure for separating the second carrier substrate from the first redistribution structure.
14. The method according to claim 11, wherein the step of forming the first redistribution structure further comprises forming at least one dielectric layer and a plurality of first conductive elements, and the chip is electrically connected to the first conductive elements.
15. The method according to claim 14, further comprising forming a plurality of conductive pillars on the first surface of the first redistribution structure, wherein the conductive pillars surround the chip.
16. The method according to claim 15, further comprising encapsulating the chip, the protection layer, and the conductive pillars by utilizing an insulation encapsulation.
17. The method according to claim 16, wherein the step of encapsulating the chip, the protection layer and the conductive pillars comprises:
- disposing the insulation encapsulation over the chip, the protection layer, and the conductive pillars; and
- reducing a thickness of the insulation encapsulation to expose top surfaces of the conductive pillars.
18. The method according to claim 17, further comprising forming a second redistribution structure above the insulation encapsulation.
19. The method according to claim 18, wherein the step of forming the second redistribution structure comprises forming at least one dielectric layer and a plurality of second conductive elements, and the conductive pillars are electrically connected between the first conductive elements and the second conductive elements respectively.
20. The method according to claim 11, wherein the step of disposing the chip on the first surface of the first redistribution structure comprises forming a plurality of bumps between the active surface of the chip and the first surface of the first redistribution structure.
Type: Application
Filed: Sep 27, 2017
Publication Date: Oct 18, 2018
Applicant: Powertech Technology Inc. (Hsinchu County)
Inventors: Shang-Yu Chang Chien (Hsinchu County), Hung-Hsin Hsu (Hsinchu County), Nan-Chun Lin (Hsinchu County)
Application Number: 15/717,923