MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
A manufacturing method of a semiconductor structure includes the following steps. A first polysilicon layer is formed on a substrate. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.
The present invention relates to a manufacturing method of a semiconductor structure, and more particularly, to a manufacturing method of a semiconductor structure for reducing particle-induced defects.
2. Description of the Prior ArtThe development of semiconductor integrated circuit technology progresses continuously and circuit designs in products of the new generation become smaller and more complicated than those of the former generation. The amount and the density of the functional devices in each chip region are increased constantly according to the requirements of innovated products, and the size of each device has to become smaller accordingly. As the size of the device becomes smaller, influence of defects induced by impurities generated during the manufacturing processes may become more serious, and the manufacturing yield may be affected accordingly.
SUMMARY OF THE INVENTIONAccording to the claimed invention, a manufacturing method of a semiconductor structure is provided. The manufacturing method includes the following steps. A planarization process to the first polysilicon layer is performed. A first etching back process to the first polysilicon layer is performed after the planarization process. A second etching back process to the first polysilicon layer is performed after the first etching back process. A first wet clean process to the first polysilicon layer is performed after the first etching back process and before the second etching back process.
In the manufacturing method of the semiconductor structure in the present invention, two etching back processes are applied for thinning the first polysilicon layer after the planarization process performed to the first polysilicon layer. The first etching back process is configured to expose impurities embedded in the first polysilicon layer after the planarization process, and the first wet clean process performed between the first etching back process and the second etching back process is configured to remove the impurities before the second etching back process which is configured to reduce the thickness of the first polysilicon layer to a target value. Defects induced by the impurities may be reduced, and the manufacturing yield may be enhanced accordingly.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have been described in detail in order to avoid obscuring the invention.
It will be understood that when an element is referred to as being “formed” on another element, it can be directly or indirectly, formed on the given element by growth, deposition, etch, attach, connect, or couple. And it will be understood that when an elements or a layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure.
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To summarize the above descriptions, according to the manufacturing method of the semiconductor structure in the present invention, the etching back process for thinning the first polysilicon layer splits into the first etching back process and the second etching back process. The first etching back process may be used to expose and/or dig out the particles embedded in the first polysilicon layer after the planarization process. The first wet clean process 93 performed after the first etching back process may be used to remove the particles embedded in the first polysilicon layer and at least partially exposed and/or dug out by the first etching back process. The second etching back process performed after the first wet clean process may be used to reduce the thickness of the first polysilicon layer to the target value. The nodule defects formed after the second etching back process and induced by the particles embedded in the first polysilicon layer may be reduced accordingly, and the manufacturing yield may be improved. Additionally, the process conditions of the second etching back process may be modified according to the thickness distribution result of the first polysilicon layer after the first etching back process and the first wet clean process, and the thickness control of the first polysilicon layer may be further improved accordingly.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims
1: A manufacturing method of a semiconductor structure, comprising:
- forming a first polysilicon layer on a substrate;
- performing a planarization process to the first polysilicon layer;
- performing a first etching back process to the first polysilicon layer after the planarization process, wherein the first polysilicon layer has a first thickness after the planarization process and before the first etching process;
- performing a second etching back process to the first polysilicon layer after the first etching back process, wherein the thickness of the first polysilicon layer is reduced by the second etching back process, wherein the first polysilicon layer has a second thickness after the first etching back process and before the second etching back process, the first polysilicon layer has a third thickness after the second etching back process, and the difference between the first thickness and the second thickness is smaller than the difference between the second thickness and the third thickness; and
- performing a first wet clean process to the first polysilicon layer after the first etching back process and before the second etching back process.
2: The manufacturing method according to claim 1, wherein a solution used in the first wet clean process comprises dilute hydrofluoric acid (DHF) or sulfuric acid.
3: The manufacturing method according to claim 1, further comprising:
- performing a first patterning process to the first polysilicon layer after the second etching back process, wherein at least a part of the first polysilicon layer is patterned to be a floating gate.
4: The manufacturing method according to claim 1, further comprising:
- forming a dielectric layer on the first polysilicon layer after the second etching back process; and
- forming a second polysilicon layer on the dielectric layer.
5: The manufacturing method according to claim 4, wherein the dielectric layer comprises an oxide-nitride-oxide (ONO) multilayered structure.
6: The manufacturing method according to claim 4, further comprising:
- performing a second patterning process to the second polysilicon layer, wherein at least a part of the second polysilicon layer is patterned to be a control gate.
7: The manufacturing method according to claim 1, further comprising:
- performing a second wet clean process to the first polysilicon layer after the planarization process and before the first etching back process.
8: The manufacturing method according to claim 7, wherein a solution used in the second wet clean process comprises sulfuric acid and hydrogen peroxide.
9: The manufacturing method according to claim 1, wherein the planarization process comprises a chemical mechanical polishing (CMP) process.
10: The manufacturing method according to claim 1, wherein a particle at least partially embedded in the first polysilicon layer is formed after the planarization process and before the first etching back process.
11: The manufacturing method according to claim 10, wherein the particle at least partially embedded in the first polysilicon layer is further exposed by the first etching back process and removed by the first wet clean process.
Type: Application
Filed: May 24, 2017
Publication Date: Nov 29, 2018
Inventors: Zhi Qiang Mu (Singapore), Chow Yee Lim (Singapore), Hui Yang (Singapore), YONG BIN FAN (Singapore), JIANJUN YANG (Singapore), Chih-Chien Chang (Hsinchu City)
Application Number: 15/603,465