SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
This application is Divisional of U.S. application Ser. No. 15/063,358 filed on Mar. 7, 2016, which claims priority to U.S. Provisional Patent Application 62/273,366 filed Dec. 30, 2015, the entire disclosures of which are incorporated herein by reference.
TECHNICAL FIELDThe disclosure relates to a semiconductor integrated circuit, more particularly to a semiconductor device having metal layers formed by a dual damascene process.
BACKGROUNDAs the semiconductor industry introduces new generations of integrated circuits (ICs) having higher performance and greater functionality, the density of the elements that form the ICs is increased, while the dimensions and spacing between components or elements of the ICs are reduced. The structure of metal wiring layers also becomes complex and minimized. To fabricate the metal wiring layers, a damascene process has been used together with a low-k (low dielectric constant being, e.g., 3.5 or lower) material.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.”
As shown in
An etch-stop layer (ESL) 20 is formed over the lower layer metal structure 10, followed by forming an interlayer dielectric (ILD) layer 30 over the ESL 20. An interlayer dielectric layer may also be called an inter-metal dielectric (IMD) layer. Further, a first mask layer 40 is formed over the ILD layer 30 and a second mask layer 50 is formed over the first mask layer 40.
The ESL 20 is a single layer of an insulating material or multiple layers of different insulating materials. In both cases, at least one layer is made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide. The aluminum-based insulating material includes aluminum oxide, aluminum oxy-carbide (carbo-oxide) and aluminum oxy-nitride. In the present disclosure aluminum oxide is referred to as Alo, the aluminum oxy-carbide (carbo-oxide) is referred to as AlOC and the aluminum oxy-nitride is referred to as ALON. These materials may be stoichiometric or non-stoichiometric.
When the ESL 20 includes more than one layers (i.e., two or more sub-layers), at least one sub-layer is made of silicon based insulating material, such as silicon nitride, silicon carbo-oxide (oxy-carbide), silicon carbo-nitride, silicon oxy-nitride, silicon carbo-oxy-nitride, silicon carbide or silicon oxide. The silicon nitride is referred to as SiN, the silicon carbo-oxide (oxy-carbide) is referred to as SiCO, the silicon carbo-nitride is referred to as SiCN, the silicon oxy-nitride is referred to as SiON, the silicon carbo-oxy-nitride is referred to as SiCON, the silicon carbide is referred to as SiC, and the silicon oxide (dioxide) is referred to as SiO. These materials may be stoichiometric or non-stoichiometric.
The thickness of the ESL 20, when it is a single layer, is in a range from about 1 nm to about 10 nm in some embodiments, and is in a range from about 2 nm to 5 nm in other embodiments. When the ESL 20 include multiple sub-layers, the thickness of each of the sub-layers is in a range from about 2 nm to about 10 nm in some embodiments, and is in a range from about 3 nm to 6 nm in other embodiments.
The ILD layer 30 is made of, for example, one or more layers of low-k dielectric material. Low-k dielectric materials have a k-value (dielectric constant) lower than about 4.0. Some low-k dielectric materials have a k-value lower than about 3.5 and may have a k-value lower than about 2.5.
The materials for the ILD layer 30 include elements of Si, 0, C and/or H, such as SiCOH and SiOC. Organic material such as polymers or porous materials may be used for the ILD layer 30. For example, the ILD layer 30 is made of one or more layers of a carbon-containing material, organo-silicate glass, a porogen-containing material, and/or combinations thereof. Nitrogen may also be included in the ILD layer 30 in some embodiments. The density of the ILD layer 30 is less than about 3 g/cm3 in one embodiment and may be less than about 2.5 g/cm3 in other embodiments. The ILD layer 30 may be formed by using, for example, plasma-enhanced chemical vapor deposition (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), and/or a spin-on technology. In case of PECVD, the film is deposited at a substrate temperature in a range of about 25° C. to about 400° C. and at a pressure of less than 100 Torr.
The thickness of the ILD layer 30 is in a range from about 10 nm to about 200 nm in some embodiments.
The first mask layer 40 is made of a dielectric material, such as the silicon based insulating materials. In one embodiment, SiO is used as the first mask layer 40. The thickness of the first mask layer 40 is in a range from about 10 nm to about 300 nm in some embodiments.
The second mask layer 50 is made of a metal based material, such as TiN, TaN, or TiO2. The thickness of the second mask layer 50 is in a range from about 3 nm to about 100 nm in some embodiments.
As shown in
Then, the ILD layer 30 is etched by using the patterned first and second mask layers as an etching mask. The patterning of the ILD layer 30 includes a dry etching.
In the present embodiment, the etching electivity of the ESL 20 with respect to the ILD layer 30 is set high. For example, an etching selectivity of the ESL 20 with respect to the ILD layer 30 during the ILD etching is about 3 or more in some embodiments, and is about 4 or more in other embodiments. In one embodiment, the etching selectivity of the ESL 20 with respect to the ILD layer 30 is in a range from about 4 to about 6. Since the etching electivity of the ESL 20 is high, the thickness of the ESL 20 can be thin, for example, less than about 5 nm. Accordingly, in the dry etching of the ILD layer 30, the ESL 20 is not substantially etched even after the surface of the ESL is exposed. In other words, the ESL 20 functions as an etch-stop layer for the ILD etching process.
Then, as shown in
The order of the patterning operation of
After the second opening 34 is formed, the second mask layer 50 is removed by a wet etching operation. Further, the ESL 20 at the bottom of the opening 32 is removed by a dry etching operation, as shown in
After the ESL 20 is etched, a second metal layer structure is formed, as shown in
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The aluminum-based insulating material, such as AlO, AlOC and AlON may be formed by the following operations. First, an aluminum layer is formed on the underlying layer (e.g., the lower layer metal structure or another sub-layer of the ESL 20). The aluminum layer is formed by, for example, metal-organic CVD (MOCVD) or ALD using tri-methyl-aluminum (TMA). Then, a plasma treatment using NH3, CO2 and/or CO gases is performed over the aluminum layer, to convert the aluminum layer into AlO, AlOC or AlON. The concentrations of Al, O, C and/or N in the plasma treated aluminum layer are not uniform, in particular, along the vertical direction. The AlON layer may be made of two layers of AlO and AlN. In some embodiments, a thin layer of aluminum having a thickness of less than about 1 nm remains at the bottom of the layer. A chemical oxidation of the aluminum layer using an oxidation solution may be employed. In some embodiments, the AlO, AlOC or AlON layer can be directly formed by CVD, PVD or ALD by using appropriate source gases.
The hafnium oxide, zirconium oxide and titanium oxide can be formed by the similar method as set forth above, or CVD, PVD or ALD, or other suitable film forming methods by using appropriate source gases.
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The various embodiments or examples described herein offer several advantages over the existing art, as set forth above. For example, in the present disclosure, by using an etch-stop layer including at least one sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide, a broader process margin for the etching of the ILD layer can be obtained. Further, since the etching selectivity of these materials is relatively high, he thickness of the etch-stop layer can be reduced, which can reduce a capacitance in the interconnect layers.
It will be understood that not all advantages have been necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer different advantages.
In accordance with one aspect of the present disclosure, a semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure, and an etch-stop layer. A second metal wiring structure is embedded in the interlayer dielectric layer and is connected to the first metal wiring layer. The etch-stop layer is disposed between the first metal wiring and the first interlayer dielectric layer, and includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
In accordance with another aspect of the present disclosure, in the method for manufacturing a semiconductor device, a first metal wiring layer is formed. An etch-stop layer is formed over the first metal wiring layer. An interlayer insulating layer is formed on the etch-stop layer. A mask layer is formed on the interlayer insulating layer. An opening is formed by etching the interlayer insulating layer. A second metal layer is formed in the opening. The etch-stop layer includes a first sub-layer made of at least one of aluminum oxide, aluminum oxy-carbide and aluminum oxy-nitride. The etching for forming the opening includes a first etching process for etching the interlayer dielectric layer and a second etching process performed after the first etching process to expose the first metal wiring layer. The first sub-layer functions as an etch-stop layer for first etching process.
In accordance with another aspect of the present disclosure, in the method for manufacturing a semiconductor device, a first metal wiring layer is formed. An etch-stop layer is formed over the first metal wiring layer. An interlayer insulating layer is formed on the etch-stop layer. A mask layer is formed on the interlayer insulating layer. An opening is formed by etching the interlayer insulating layer. A second metal layer is formed in the opening. The etch-stop layer includes a first sub-layer made of at least one of aluminum oxide, aluminum oxy-carbide and aluminum oxy-nitride and a second sub-layer made of a silicon based insulating material. The etching for forming the opening includes a first etching process for etching the interlayer dielectric layer and a second etching process performed after the first etching process to expose the first metal wiring layer. The second sub-layer functions as an etch-stop layer for first etching process.
The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A semiconductor device, comprising:
- a first metal wiring layer;
- an interlayer dielectric layer formed over the first metal layer;
- a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer; and
- an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer,
- wherein the etch-stop layer consists of a first sub-layer made of a first silicon based insulating material, a second sub-layer made of a second silicon based insulating material different from the first silicon based insulating material, and a third sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
2. The semiconductor device of claim 1, wherein the first sub-layer in direct contact with the first material wiring and the third sub-layer is in direct contact with the interlayer dielectric layer.
3. The semiconductor device of claim 1, wherein the first sub-layer is made of at least one of aluminum oxide, aluminum oxy-carbide and aluminum oxy-nitride.
4. The semiconductor device of claim 1, wherein the first sub-layer is made of at last one from the group consisting of aluminum oxy-carbide and aluminum oxy-nitride having a non-uniform nitrogen concentration in a thickness direction, aluminum oxy-carbide having a non-uniform carbon concentration in the thickness direction, hafnium oxide, zirconium oxide and titanium oxide.
5. The semiconductor device of claim 1, wherein the first and second silicon based insulating materials include one selected from the group consisting of SiCO, SiCN, SiC, SiO, SiON, SiCON or SiN.
6. The semiconductor device of claim 1, wherein the first silicon based insulating material includes one selected from the group consisting of SiCO, SiC and SiO.
7. The semiconductor device of claim 6, wherein the first silicon based insulating material includes one selected from the group consisting of SiCN, SiON, SiCON and SiN.
8. A method for manufacturing a semiconductor device, comprising:
- forming a first metal wiring layer;
- forming an etch-stop layer over the first metal wiring layer;
- forming an interlayer dielectric layer on the etch-stop layer;
- forming a mask layer on the interlayer dielectric layer;
- forming an opening by etching the interlayer dielectric layer; and
- forming a second metal layer in the opening, wherein:
- the etch-stop layer consists of a first sub-layer made of a first silicon based insulating material, a second sub-layer made of a second silicon based insulating material different from the first silicon based insulating material, and a third sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
9. The method of claim 8, wherein the forming an opening includes a first etching process for etching the interlayer dielectric layer and a second etching process performed after the first etching process to expose the first metal wiring layer, and
- the first sub-layer functions as an etch-stop layer for first etching process.
10. The method of claim 8, wherein the forming an opening includes a first etching process for etching the interlayer dielectric layer, which stops on the first sub-layer, a second etching process performed after the first etching process to expose the second sub-layer and a third etching process performed after the second etching process to expose the metal wiring layer.
11. The method of claim 10, wherein the second etching process includes a wet etching process.
12. The method of claim 8, wherein the first sub-layer in direct contact with the first material wiring and the third sub-layer is in direct contact with the interlayer dielectric layer.
13. The method of claim 8, wherein the first sub-layer is made of at least one of aluminum oxide, aluminum oxy-carbide and aluminum oxy-nitride.
14. The method of claim 8, wherein the first sub-layer is made of at last one from the group consisting of aluminum oxy-carbide and aluminum oxy-nitride having a non-uniform nitrogen concentration in a thickness direction, aluminum oxy-carbide having a non-uniform carbon concentration in the thickness direction, hafnium oxide, zirconium oxide and titanium oxide.
15. The method of claim 8, wherein the first silicon based insulating material includes one selected from the group consisting of SiCO, SiC and SiO.
16. The method of claim 15, wherein the first silicon based insulating material includes one selected from the group consisting of SiCN, SiON, SiCON and SiN.
17. A method for manufacturing a semiconductor device, comprising:
- forming a first metal wiring layer;
- forming an etch-stop layer over the first metal wiring layer;
- forming an interlayer dielectric layer on the etch-stop layer;
- forming a mask layer on the interlayer dielectric layer, the mask layer including a first mask layer disposed on the interlayer dielectric layer and a second mask layer disposed on the first mask layer;
- forming an opening by etching the interlayer dielectric layer; and
- forming a second metal layer in the opening, wherein:
- the etch-stop layer consists of a first sub-layer made of a first silicon based insulating material, a second sub-layer made of a second silicon based insulating material different from the first silicon based insulating material, and a third sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide, and
- the first mask layer is made of a metal-based material and the second mask layer is made of a dielectric material.
18. The method of claim 17, wherein the forming the opening includes:
- etching the interlayer dielectric layer by using the second mask layer as an etching mask;
- removing the second mask layer; and
- etching the etch-stop layer by using the first mask layer as an etching mask.
19. The method of claim 18, wherein the etching the etch-stop layer includes a first etching process of etching the third sub-layer, which stops on the second sub-layer and a second etching process performed after the first etching process to expose the metal wiring layer.
20. The method of claim 17, wherein the second mask layer includes at least one selected from the group consisting of TiN, TaN and TiO2.
Type: Application
Filed: Jul 30, 2018
Publication Date: Dec 6, 2018
Patent Grant number: 10867847
Inventors: Hsin-Yen HUANG (New Taipei City), Kai-Fang CHENG (Taoyuan City), Chi-Lin TENG (Taichung City), Shao-Kuan LEE (Hsinchu), Hai-Ching CHEN (Hsinchu City)
Application Number: 16/049,187