Data access device and method applicable to processor
The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.
The present invention relates to a data access device and a data access method, especially to a data access device and a data access method that are applicable to a processor.
2. Description of Related ArtIn conventional art, a processor circuit uses pipeline operation. The stages of the pipeline operation include an instruction fetch stage, a decode stage, an execution stage, a data load/store stage and a register update stage. The above-mentioned stages can function concurrently, though each of the decode stage, the execution stage, the data load/store stage and the register update stage relies on the output of a preceding stage. Since the instruction fetch stage and the data load/store stage can function concurrently, the processor circuit is able to read instructions from an instruction cache memory in the instruction fetch stage and read data from a data cache memory in the data load/store stage simultaneously; however, the processor circuit may read data from the instruction cache memory in the data load/store stage in response to a request of some program execution. In light of the above, the processor circuit may be requested at substantially the same time to read instructions from the instruction cache memory in the instruction fetch stage and read data from the instruction cache memory in the data load/store stage, which leads to the instruction fetch stage and the data load/store stage contending for the opportunity to access the instruction cache memory, and results in one having to wait for the other one finishing accessing the instruction cache memory. Such contention obviously affects operation efficiency.
People who are interested in the related art may refer to the following literature: U.S. Pat. No. 6,430,655.
SUMMARY OF THE INVENTIONAn object of the present invention is to provide a data access device and method applicable to a processor, so as to improve operation efficiency.
The present invention discloses a data access device applicable to a processor. An embodiment of the data access device includes: an instruction cache memory; a data cache memory; a processor circuit; a duplication circuit; and a decision circuit. The types of the instruction cache memory and the data cache memory could be the same or different; for instance, both the two memories are static random access memories (SRAMs). The processor circuit is configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both the N and the M are positive integers and the M is greater than the N. The duplication circuit is configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time. The decision circuit is configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request. Accordingly, the data access device can reduce the chance of contending for the opportunity of accessing the instruction cache memory, and thereby reach better performance.
The present invention also discloses a data access method applicable to a processor. An embodiment of the data access method includes the following steps: reading specific data from an instruction cache memory for the Nth time and read the specific data from a data cache memory for the Mth time, in which both the N and the M are positive integers and the M is greater than the N; copying the specific data from the instruction cache memory to the data cache memory when reading the specific data for the Nth time; and determining whether data requested by a read request are stored in the data cache memory according to the read request. The types of the above-mentioned instruction cache memory and the above-mentioned data cache memory could be the same or different; for instance, both the two memories are static random access memories (SRAMs). Accordingly, the data access method can reduce the chance of contending for the opportunity of accessing the instruction cache memory, and thereby reach better performance.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.
The following description is written by referring to terms acknowledged in this industrial field. If any term is defined in this specification, such term should be explained accordingly.
The present disclosure includes a data access device and a data access method that are applicable to a processor. The device and the method can reduce the chance of different operation stages of a processor circuit contending for the opportunity of accessing the same instruction cache memory, and thereby reach better performance.
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In light of the above, by the duplication operation of the duplication circuit 140 and the decision operation of the decision circuit 150, the data access device 100 of
In addition to the aforementioned data access device, the present invention also discloses a data access method. An embodiment of the method is shown in
- Step S310: reading specific data from an instruction cache memory (e.g., the instruction cache memory 110 of
FIG. 1 or the equivalent thereof) for the Nth time and read the specific data from a data cache memory (e.g., the data cache memory 120 ofFIG. 1 or the equivalent thereof) for the Mth time, in which both the N and the M are positive integers and the M is greater than the N. The above-mentioned instruction cache memory and the above-mentioned data cache memory could be memories of the same type or different types. Step S310 can be carried out by the processor circuit 130 ofFIG. 1 or the equivalent thereof. - Step S320: copying the specific data from the instruction cache memory to the data cache memory when reading the specific data for the Nth time. Step S320 can be carried out by the duplication circuit 140 of
FIG. 1 or the equivalent thereof. - Step S330: determining whether data requested by a read request are stored in the data cache memory according to the read request. Step S330 can be carried out by the decision circuit 150 or the equivalent thereof.
Please refer to
- Step S410: in response to the read request or after determining that the data requested by the read request are not stored in the data cache memory, determining whether the data requested by the read request are stored in the instruction cache memory. Step S410 can be carried out by the decision circuit 150 of
FIG. 1 or the equivalent thereof.
Since people of ordinary skill in the art can appreciate the details and the modifications of the method embodiments of
In summary, the data access circuit and method of the present invention can reduce the chances of different operation stages of a processor circuit contending for the opportunity of accessing the same instruction cache memory, and thereby reach better performance.
The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of present invention are all consequently viewed as being embraced by the scope of the present invention.
Claims
1. A data access device applicable to a processor, comprising:
- an instruction cache memory;
- a data cache memory;
- a processor circuit configured to read specific data from the instruction cache memory for a Nth time and read the specific data from the data cache memory for a Mth time, in which both the N and the M are positive integers and the M is greater than the N;
- a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and
- a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.
2. The data access device of claim 1, wherein both the instruction cache memory and the data cache memory are static random access memories (SRAMs).
3. The data access device of claim 1, wherein the decision circuit determines whether the data requested by the read request are stored in the instruction cache memory according to the read request, or the decision circuit determines whether the data requested by the read request are stored in the instruction cache memory after the decision circuit determines that the data requested by the read request are not stored in the data cache memory.
4. The data access device of claim 1, wherein transmission between the instruction cache memory and the processor circuit is single port transmission.
5. The data access device of claim 1, wherein operation stages of the processor circuit include an instruction fetch stage and a data access stage, the instruction fetch stage and the data access stage are capable of being carried out concurrently, the processor circuit sends the read request in the data access stage so as to access the instruction cache memory after the processor circuit fails to read the data requested by the read request from the data cache memory, and the processor circuit is capable of accessing the instruction cache memory in the instruction fetch stage.
6. The data access device of claim 1, wherein data in the instruction cache memory remain unchanged during a normal operation of the processor circuit, data in the data cache memory remain unchanged or are changed during the normal operation of the processor circuit, and the normal operation starts from the processor circuit finishing a start-up procedure and ends before the processor circuit restarting the start-up procedure.
7. The data access device of claim 1, wherein the decision circuit includes:
- a first decision and access circuit configured to determine whether the data requested by the read request are stored in the data cache memory according to the read request and transmit the data in the data cache memory requested by the read request to the processor circuit after determining the data requested by the read request are stored in the data cache memory, and the first decision and access circuit further configured to output a first decision result after determining the data requested by the read request are not stored in the data cache memory;
- a second decision circuit configured to determine whether the data requested by the read request are stored in the instruction cache memory according to the read request or the first decision result, and thereby output a second decision result; and
- a third decision and access circuit configured to transmit the data in the instruction cache memory requested by the read request to the processor circuit when the first decision result indicates that the data requested by the read request are absent in the data cache memory and the second decision result indicates that the data requested by the read request are stored in the instruction cache memory.
8. A data access method applicable to a processor and carried out by a data access device, the data access method comprising:
- reading specific data from an instruction cache memory for a Nth time and read the specific data from a data cache memory for a Mth time, in which both the N and the M are positive integers and the M is greater than the N;
- copying the specific data from the instruction cache memory to the data cache memory when reading the specific data for the Nth time; and
- determining whether data requested by a read request are stored in the data cache memory according to the read request.
9. The data access method of claim 8, wherein data in the instruction cache memory remain unchanged during a normal operation of the data access device, data in the data cache memory are changed during the normal operation of the data access device, and the normal operation starts from the data access device finishing a start-up procedure and ends before the data access device restarting the start-up procedure.
10. The data access method of claim 8, further comprising:
- after determining the data requested by the read request are stored in the data cache memory, outputting the data in the data cache memory requested by the read request;
- after determining the data requested by the read request are not stored in the data cache memory, outputting a first decision result;
- determining whether the data requested by the read request are stored in the instruction cache memory according to the read request or the first decision result, and thereby outputting a second decision result; and
- when the first decision result indicates that the data requested by the read request are absent in the data cache memory and the second decision result indicates that the data requested by the read request are stored in the instruction cache memory, outputting the data in the instruction cache memory requested by the read request.
Type: Application
Filed: Jul 13, 2018
Publication Date: Jan 17, 2019
Patent Grant number: 10657063
Inventors: Yen-Ju LU (Hsinchu City), Chao-Wei HUANG (Hsinchu County)
Application Number: 16/034,868