TECHNOLOGIES FOR INTERLEAVING MEMORY ACROSS SHARED MEMORY POOLS
Technologies for interleaving memory that is accessible via a shared memory pool include a memory sled. The memory sled includes a memory pool of byte-addressable memory devices. The memory sled also includes a memory pool controller coupled to the memory pool. The memory pool controller receives a request to allocate memory addresses of the memory pool to a compute sled. The memory pool controller determines an interleaving configuration for the compute sled as a function of memory characteristics of the compute sled and configures the memory addresses according to the determined interleaving configuration.
The present application claims the benefit of Indian Provisional Patent Application No. 201741030632, filed Aug. 30, 2017 and U.S. Provisional Patent Application No. 62/584,401, filed Nov. 10, 2017.
BACKGROUNDIn a typical compute device, any byte-addressable memory (e.g., RAM, non-volatile memory) that is to be used during the execution of an application (e.g., a workload) is local to the processor (e.g., physically installed on the compute device) and it is possible for the memory available to the compute device to fall short of the amount of memory requested by the application during one or more operations. As such, an administrator of the compute device may choose to equip the compute device with a relatively large amount of memory to account for situations in which the application may benefit from the large amount of memory (e.g., for memory intensive operations). However, for a majority of the time, a large part of memory onboard the compute device may go unused. In a data center in which multiple compute devices may be assigned workloads to execute, the costs of equipping the compute devices with relatively large amounts memory can be significant.
The concepts described herein are illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device).
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
Referring now to
Referring now to
It should be appreciated that each of the other pods 120, 130, 140 (as well as any additional pods of the data center 100) may be similarly structured as, and have components similar to, the pod 110 shown in and described in regard to
Referring now to
In the illustrative embodiments, each sled of the data center 100 is embodied as a chassis-less sled. That is, each sled has a chassis-less circuit board substrate on which physical resources (e.g., processors, memory, accelerators, storage, etc.) are mounted as discussed in more detail below. As such, the rack 240 is configured to receive the chassis-less sleds. For example, each pair 310 of elongated support arms 312 defines a sled slot 320 of the rack 240, which is configured to receive a corresponding chassis-less sled. To do so, each illustrative elongated support arm 312 includes a circuit board guide 330 configured to receive the chassis-less circuit board substrate of the sled. Each circuit board guide 330 is secured to, or otherwise mounted to, a top side 332 of the corresponding elongated support arm 312. For example, in the illustrative embodiment, each circuit board guide 330 is mounted at a distal end of the corresponding elongated support arm 312 relative to the corresponding elongated support post 302, 304. For clarity of the Figures, not every circuit board guide 330 may be referenced in each Figure.
Each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 configured to receive the chassis-less circuit board substrate of a sled 400 when the sled 400 is received in the corresponding sled slot 320 of the rack 240. To do so, as shown in
It should be appreciated that each circuit board guide 330 is dual sided. That is, each circuit board guide 330 includes an inner wall that defines a circuit board slot 380 on each side of the circuit board guide 330. In this way, each circuit board guide 330 can support a chassis-less circuit board substrate on either side. As such, a single additional elongated support post may be added to the rack 240 to turn the rack 240 into a two-rack solution that can hold twice as many sled slots 320 as shown in
In some embodiments, various interconnects may be routed upwardly or downwardly through the elongated support posts 302, 304. To facilitate such routing, each elongated support post 302, 304 includes an inner wall that defines an inner chamber in which the interconnect may be located. The interconnects routed through the elongated support posts 302, 304 may be embodied as any type of interconnects including, but not limited to, data or communication interconnects to provide communication connections to each sled slot 320, power interconnects to provide power to each sled slot 320, and/or other types of interconnects.
The rack 240, in the illustrative embodiment, includes a support platform on which a corresponding optical data connector (not shown) is mounted. Each optical data connector is associated with a corresponding sled slot 320 and is configured to mate with an optical data connector of a corresponding sled 400 when the sled 400 is received in the corresponding sled slot 320. In some embodiments, optical connections between components (e.g., sleds, racks, and switches) in the data center 100 are made with a blind mate optical connection. For example, a door on each cable may prevent dust from contaminating the fiber inside the cable. In the process of connecting to a blind mate optical connector mechanism, the door is pushed open when the end of the cable enters the connector mechanism. Subsequently, the optical fiber inside the cable enters a gel within the connector mechanism and the optical fiber of one cable comes into contact with the optical fiber of another cable within the gel inside the connector mechanism.
The illustrative rack 240 also includes a fan array 370 coupled to the cross-support arms of the rack 240. The fan array 370 includes one or more rows of cooling fans 372, which are aligned in a horizontal line between the elongated support posts 302, 304. In the illustrative embodiment, the fan array 370 includes a row of cooling fans 372 for each sled slot 320 of the rack 240. As discussed above, each sled 400 does not include any on-board cooling system in the illustrative embodiment and, as such, the fan array 370 provides cooling for each sled 400 received in the rack 240. Each rack 240, in the illustrative embodiment, also includes a power supply associated with each sled slot 320. Each power supply is secured to one of the elongated support arms 312 of the pair 310 of elongated support arms 312 that define the corresponding sled slot 320. For example, the rack 240 may include a power supply coupled or secured to each elongated support arm 312 extending from the elongated support post 302. Each power supply includes a power connector configured to mate with a power connector of the sled 400 when the sled 400 is received in the corresponding sled slot 320. In the illustrative embodiment, the sled 400 does not include any on-board power supply and, as such, the power supplies provided in the rack 240 supply power to corresponding sleds 400 when mounted to the rack 240.
Referring now to
As discussed above, the illustrative sled 400 includes a chassis-less circuit board substrate 602, which supports various physical resources (e.g., electrical components) mounted thereon. It should be appreciated that the circuit board substrate 602 is “chassis-less” in that the sled 400 does not include a housing or enclosure. Rather, the chassis-less circuit board substrate 602 is open to the local environment. The chassis-less circuit board substrate 602 may be formed from any material capable of supporting the various electrical components mounted thereon. For example, in an illustrative embodiment, the chassis-less circuit board substrate 602 is formed from an FR-4 glass-reinforced epoxy laminate material. Of course, other materials may be used to form the chassis-less circuit board substrate 602 in other embodiments.
As discussed in more detail below, the chassis-less circuit board substrate 602 includes multiple features that improve the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602. As discussed, the chassis-less circuit board substrate 602 does not include a housing or enclosure, which may improve the airflow over the electrical components of the sled 400 by reducing those structures that may inhibit air flow. For example, because the chassis-less circuit board substrate 602 is not positioned in an individual housing or enclosure, there is no backplane (e.g., a backplate of the chassis) to the chassis-less circuit board substrate 602, which could inhibit air flow across the electrical components. Additionally, the chassis-less circuit board substrate 602 has a geometric shape configured to reduce the length of the airflow path across the electrical components mounted to the chassis-less circuit board substrate 602. For example, the illustrative chassis-less circuit board substrate 602 has a width 604 that is greater than a depth 606 of the chassis-less circuit board substrate 602. In one particular embodiment, for example, the chassis-less circuit board substrate 602 has a width of about 21 inches and a depth of about 9 inches, compared to a typical server that has a width of about 17 inches and a depth of about 39 inches. As such, an airflow path 608 that extends from a front edge 610 of the chassis-less circuit board substrate 602 toward a rear edge 612 has a shorter distance relative to typical servers, which may improve the thermal cooling characteristics of the sled 400. Furthermore, although not illustrated in
As discussed above, the illustrative sled 400 includes one or more physical resources 620 mounted to a top side 650 of the chassis-less circuit board substrate 602. Although two physical resources 620 are shown in
The sled 400 also includes one or more additional physical resources 630 mounted to the top side 650 of the chassis-less circuit board substrate 602. In the illustrative embodiment, the additional physical resources include a network interface controller (NIC) as discussed in more detail below. Of course, depending on the type and functionality of the sled 400, the physical resources 630 may include additional or other electrical components, circuits, and/or devices in other embodiments.
The physical resources 620 are communicatively coupled to the physical resources 630 via an input/output (I/O) subsystem 622. The I/O subsystem 622 may be embodied as circuitry and/or components to facilitate input/output operations with the physical resources 620, the physical resources 630, and/or other components of the sled 400. For example, the I/O subsystem 622 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In the illustrative embodiment, the I/O subsystem 622 is embodied as, or otherwise includes, a double data rate 4 (DDR4) data bus or a DDRS data bus.
In some embodiments, the sled 400 may also include a resource-to-resource interconnect 624. The resource-to-resource interconnect 624 may be embodied as any type of communication interconnect capable of facilitating resource-to-resource communications. In the illustrative embodiment, the resource-to-resource interconnect 624 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the resource-to-resource interconnect 624 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to resource-to-resource communications.
The sled 400 also includes a power connector 640 configured to mate with a corresponding power connector of the rack 240 when the sled 400 is mounted in the corresponding rack 240. The sled 400 receives power from a power supply of the rack 240 via the power connector 640 to supply power to the various electrical components of the sled 400. That is, the sled 400 does not include any local power supply (i.e., an on-board power supply) to provide power to the electrical components of the sled 400. The exclusion of a local or on-board power supply facilitates the reduction in the overall footprint of the chassis-less circuit board substrate 602, which may increase the thermal cooling characteristics of the various electrical components mounted on the chassis-less circuit board substrate 602 as discussed above. In some embodiments, power is provided to the processors 820 through vias directly under the processors 820 (e.g., through the bottom side 750 of the chassis-less circuit board substrate 602), providing an increased thermal budget, additional current and/or voltage, and better voltage control over typical boards.
In some embodiments, the sled 400 may also include mounting features 642 configured to mate with a mounting arm, or other structure, of a robot to facilitate the placement of the sled 600 in a rack 240 by the robot. The mounting features 642 may be embodied as any type of physical structures that allow the robot to grasp the sled 400 without damaging the chassis-less circuit board substrate 602 or the electrical components mounted thereto. For example, in some embodiments, the mounting features 642 may be embodied as non-conductive pads attached to the chassis-less circuit board substrate 602. In other embodiments, the mounting features may be embodied as brackets, braces, or other similar structures attached to the chassis-less circuit board substrate 602. The particular number, shape, size, and/or make-up of the mounting feature 642 may depend on the design of the robot configured to manage the sled 400.
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The memory devices 720 may be embodied as any type of memory device capable of storing data for the physical resources 620 during operation of the sled 400, such as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include next-generation nonvolatile devices, such as Intel 3D XPoint™ memory or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product. In some embodiments, the memory device may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance.
Referring now to
In the illustrative compute sled 800, the physical resources 620 are embodied as processors 820. Although only two processors 820 are shown in
In some embodiments, the compute sled 800 may also include a processor-to-processor interconnect 842. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the processor-to-processor interconnect 842 may be embodied as any type of communication interconnect capable of facilitating processor-to-processor interconnect 842 communications. In the illustrative embodiment, the processor-to-processor interconnect 842 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the processor-to-processor interconnect 842 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
The compute sled 800 also includes a communication circuit 830. The illustrative communication circuit 830 includes a network interface controller (NIC) 832, which may also be referred to as a host fabric interface (HFI). The NIC 832 may be embodied as, or otherwise include, any type of integrated circuit, discrete circuits, controller chips, chipsets, add-in-boards, daughtercards, network interface cards, other devices that may be used by the compute sled 800 to connect with another compute device (e.g., with other sleds 400). In some embodiments, the NIC 832 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 832 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 832. In such embodiments, the local processor of the NIC 832 may be capable of performing one or more of the functions of the processors 820. Additionally or alternatively, in such embodiments, the local memory of the NIC 832 may be integrated into one or more components of the compute sled at the board level, socket level, chip level, and/or other levels.
The communication circuit 830 is communicatively coupled to an optical data connector 834. The optical data connector 834 is configured to mate with a corresponding optical data connector of the rack 240 when the compute sled 800 is mounted in the rack 240. Illustratively, the optical data connector 834 includes a plurality of optical fibers which lead from a mating surface of the optical data connector 834 to an optical transceiver 836. The optical transceiver 836 is configured to convert incoming optical signals from the rack-side optical data connector to electrical signals and to convert electrical signals to outgoing optical signals to the rack-side optical data connector. Although shown as forming part of the optical data connector 834 in the illustrative embodiment, the optical transceiver 836 may form a portion of the communication circuit 830 in other embodiments.
In some embodiments, the compute sled 800 may also include an expansion connector 840. In such embodiments, the expansion connector 840 is configured to mate with a corresponding connector of an expansion chassis-less circuit board substrate to provide additional physical resources to the compute sled 800. The additional physical resources may be used, for example, by the processors 820 during operation of the compute sled 800. The expansion chassis-less circuit board substrate may be substantially similar to the chassis-less circuit board substrate 602 discussed above and may include various electrical components mounted thereto. The particular electrical components mounted to the expansion chassis-less circuit board substrate may depend on the intended functionality of the expansion chassis-less circuit board substrate. For example, the expansion chassis-less circuit board substrate may provide additional compute resources, memory resources, and/or storage resources. As such, the additional physical resources of the expansion chassis-less circuit board substrate may include, but is not limited to, processors, memory devices, storage devices, and/or accelerator circuits including, for example, field programmable gate arrays (FPGA), application-specific integrated circuits (ASICs), security co-processors, graphics processing units (GPUs), machine learning circuits, or other specialized processors, controllers, devices, and/or circuits.
Referring now to
As discussed above, the individual processors 820 and communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. In the illustrative embodiment, the processors 820 and communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those physical resources are linearly in-line with others along the direction of the airflow path 608. It should be appreciated that, although the optical data connector 834 is in-line with the communication circuit 830, the optical data connector 834 produces no or nominal heat during operation.
The memory devices 720 of the compute sled 800 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the processors 820 located on the top side 650 via the I/O subsystem 622. Because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the processors 820 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Of course, each processor 820 may be communicatively coupled to a different set of one or more memory devices 720 in some embodiments. Alternatively, in other embodiments, each processor 820 may be communicatively coupled to each memory device 720. In some embodiments, the memory devices 720 may be mounted to one or more memory mezzanines on the bottom side of the chassis-less circuit board substrate 602 and may interconnect with a corresponding processor 820 through a ball-grid array.
Each of the processors 820 includes a heatsink 850 secured thereto. Due to the mounting of the memory devices 720 to the bottom side 750 of the chassis-less circuit board substrate 602 (as well as the vertical spacing of the sleds 400 in the corresponding rack 240), the top side 650 of the chassis-less circuit board substrate 602 includes additional “free” area or space that facilitates the use of heatsinks 850 having a larger size relative to traditional heatsinks used in typical servers. Additionally, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602, none of the processor heatsinks 850 include cooling fans attached thereto. That is, each of the heatsinks 850 is embodied as a fan-less heatsinks.
Referring now to
In the illustrative accelerator sled 1000, the physical resources 620 are embodied as accelerator circuits 1020. Although only two accelerator circuits 1020 are shown in
In some embodiments, the accelerator sled 1000 may also include an accelerator-to-accelerator interconnect 1042. Similar to the resource-to-resource interconnect 624 of the sled 600 discussed above, the accelerator-to-accelerator interconnect 1042 may be embodied as any type of communication interconnect capable of facilitating accelerator-to-accelerator communications. In the illustrative embodiment, the accelerator-to-accelerator interconnect 1042 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the accelerator-to-accelerator interconnect 1042 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. In some embodiments, the accelerator circuits 1020 may be daisy-chained with a primary accelerator circuit 1020 connected to the NIC 832 and memory 720 through the I/O subsystem 622 and a secondary accelerator circuit 1020 connected to the NIC 832 and memory 720 through a primary accelerator circuit 1020.
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In the illustrative storage sled 1200, the physical resources 620 are embodied as storage controllers 1220. Although only two storage controllers 1220 are shown in
In some embodiments, the storage sled 1200 may also include a controller-to-controller interconnect 1242. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1242 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1242 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1242 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications.
Referring now to
The storage cage 1252 illustratively includes sixteen mounting slots 1256 and is capable of mounting and storing sixteen solid state drives 1254. Of course, the storage cage 1252 may be configured to store additional or fewer solid state drives 1254 in other embodiments. Additionally, in the illustrative embodiment, the solid state drivers are mounted vertically in the storage cage 1252, but may be mounted in the storage cage 1252 in a different orientation in other embodiments. Each solid state drive 1254 may be embodied as any type of data storage device capable of storing long term data. To do so, the solid state drives 1254 may include volatile and non-volatile memory devices discussed above.
As shown in
As discussed above, the individual storage controllers 1220 and the communication circuit 830 are mounted to the top side 650 of the chassis-less circuit board substrate 602 such that no two heat-producing, electrical components shadow each other. For example, the storage controllers 1220 and the communication circuit 830 are mounted in corresponding locations on the top side 650 of the chassis-less circuit board substrate 602 such that no two of those electrical components are linearly in-line with other along the direction of the airflow path 608.
The memory devices 720 of the storage sled 1200 are mounted to the bottom side 750 of the of the chassis-less circuit board substrate 602 as discussed above in regard to the sled 400. Although mounted to the bottom side 750, the memory devices 720 are communicatively coupled to the storage controllers 1220 located on the top side 650 via the I/O subsystem 622. Again, because the chassis-less circuit board substrate 602 is embodied as a double-sided circuit board, the memory devices 720 and the storage controllers 1220 may be communicatively coupled by one or more vias, connectors, or other mechanisms extending through the chassis-less circuit board substrate 602. Each of the storage controllers 1220 includes a heatsink 1270 secured thereto. As discussed above, due to the improved thermal cooling characteristics of the chassis-less circuit board substrate 602 of the storage sled 1200, none of the heatsinks 1270 include cooling fans attached thereto. That is, each of the heatsinks 1270 is embodied as a fan-less heatsink.
Referring now to
In the illustrative memory sled 1400, the physical resources 620 are embodied as memory controllers 1420. Although only two memory controllers 1420 are shown in
In some embodiments, the memory sled 1400 may also include a controller-to-controller interconnect 1442. Similar to the resource-to-resource interconnect 624 of the sled 400 discussed above, the controller-to-controller interconnect 1442 may be embodied as any type of communication interconnect capable of facilitating controller-to-controller communications. In the illustrative embodiment, the controller-to-controller interconnect 1442 is embodied as a high-speed point-to-point interconnect (e.g., faster than the I/O subsystem 622). For example, the controller-to-controller interconnect 1442 may be embodied as a QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or other high-speed point-to-point interconnect dedicated to processor-to-processor communications. As such, in some embodiments, a memory controller 1420 may access, through the controller-to-controller interconnect 1442, memory that is within the memory set 1432 associated with another memory controller 1420. In some embodiments, a scalable memory controller is made of multiple smaller memory controllers, referred to herein as “chiplets”, on a memory sled (e.g., the memory sled 1400). The chiplets may be interconnected (e.g., using EMIB (Embedded Multi-Die Interconnect Bridge)). The combined chiplet memory controller may scale up to a relatively large number of memory controllers and I/O ports, (e.g., up to 16 memory channels). In some embodiments, the memory controllers 1420 may implement a memory interleave (e.g., one memory address is mapped to the memory set 1430, the next memory address is mapped to the memory set 1432, and the third address is mapped to the memory set 1430, etc.). The interleaving may be managed within the memory controllers 1420, or from CPU sockets (e.g., of the compute sled 800) across network links to the memory sets 1430, 1432, and may improve the latency associated with performing memory access operations as compared to accessing contiguous memory addresses from the same memory device.
Further, in some embodiments, the memory sled 1400 may be connected to one or more other sleds 400 (e.g., in the same rack 240 or an adjacent rack 240) through a waveguide, using the waveguide connector 1480. In the illustrative embodiment, the waveguides are 64 millimeter waveguides that provide 16 Rx (i.e., receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the illustrative embodiment, is either 16 Ghz or 32 Ghz. In other embodiments, the frequencies may be different. Using a waveguide may provide high throughput access to the memory pool (e.g., the memory sets 1430, 1432) to another sled (e.g., a sled 400 in the same rack 240 or an adjacent rack 240 as the memory sled 1400) without adding to the load on the optical data connector 834.
Referring now to
Additionally, in some embodiments, the orchestrator server 1520 may identify trends in the resource utilization of the workload (e.g., the application 1532), such as by identifying phases of execution (e.g., time periods in which different operations, each having different resource utilizations characteristics, are performed) of the workload (e.g., the application 1532) and pre-emptively identifying available resources in the data center 100 and allocating them to the managed node 1570 (e.g., within a predefined time period of the associated phase beginning). In some embodiments, the orchestrator server 1520 may model performance based on various latencies and a distribution scheme to place workloads among compute sleds and other resources (e.g., accelerator sleds, memory sleds, storage sleds) in the data center 100. For example, the orchestrator server 1520 may utilize a model that accounts for the performance of resources on the sleds 400 (e.g., FPGA performance, memory access latency, etc.) and the performance (e.g., congestion, latency, bandwidth) of the path through the network to the resource (e.g., FPGA). As such, the orchestrator server 1520 may determine which resource(s) should be used with which workloads based on the total latency associated with each potential resource available in the data center 100 (e.g., the latency associated with the performance of the resource itself in addition to the latency associated with the path through the network between the compute sled executing the workload and the sled 400 on which the resource is located).
In some embodiments, the orchestrator server 1520 may generate a map of heat generation in the data center 100 using telemetry data (e.g., temperatures, fan speeds, etc.) reported from the sleds 400 and allocate resources to managed nodes as a function of the map of heat generation and predicted heat generation associated with different workloads, to maintain a target temperature and heat distribution in the data center 100. Additionally or alternatively, in some embodiments, the orchestrator server 1520 may organize received telemetry data into a hierarchical model that is indicative of a relationship between the managed nodes (e.g., a spatial relationship such as the physical locations of the resources of the managed nodes within the data center 100 and/or a functional relationship, such as groupings of the managed nodes by the customers the managed nodes provide services for, the types of functions typically performed by the managed nodes, managed nodes that typically share or exchange workloads among each other, etc.). Based on differences in the physical locations and resources in the managed nodes, a given workload may exhibit different resource utilizations (e.g., cause a different internal temperature, use a different percentage of processor or memory capacity) across the resources of different managed nodes. The orchestrator server 1520 may determine the differences based on the telemetry data stored in the hierarchical model and factor the differences into a prediction of future resource utilization of a workload if the workload is reassigned from one managed node to another managed node, to accurately balance resource utilization in the data center 100.
To reduce the computational load on the orchestrator server 1520 and the data transfer load on the network, in some embodiments, the orchestrator server 1520 may send self-test information to the sleds 400 to enable each sled 400 to locally (e.g., on the sled 400) determine whether telemetry data generated by the sled 400 satisfies one or more conditions (e.g., an available capacity that satisfies a predefined threshold, a temperature that satisfies a predefined threshold, etc.). Each sled 400 may then report back a simplified result (e.g., yes or no) to the orchestrator server 1520, which the orchestrator server 1520 may utilize in determining the allocation of resources to managed nodes.
Referring now to
In the illustrative embodiment, in operation, the memory sled 1640 establishes address spaces in the memory pool 1670 for use by each compute sled 1630 in the execution of the workloads. In doing so, the memory sled 1640 may enable multiple of the compute sleds 1630 to access the same memory regions (e.g., memory at the same physical memory address), thereby eliminating the requirement for the compute sleds 1630 to maintain local copies of the data in their local memory. Conversely, the memory sled 1640 may exclude compute sleds 1630 from accessing certain data in the memory that (e.g., data utilized by a given workload that is unrelated to other workloads). As such, the system 1610 enables more efficient use of memory among multiple compute devices (e.g., compute sled 1630) in a data center as compared to typical systems. Further, and as described in more detail herein, the memory pool 1670 and the compute sleds 1630 utilize memory interleaving (e.g., utilizing a contiguous address space that maps to alternate memory devices) to increase the speed at which memory access operations are performed, thereby improving the speed at which workloads are executed.
The compute sled 1632, in the illustrative embodiment, includes central processing units (CPUs) 1680 and 1682, and the compute sled 1634 includes CPUs 1684 and 1686. Illustratively, each of the CPUs 1680, 1682, 1684, and 1686 are connected with the memory pool controller 1660 through a primary link (e.g., a waveguide, an optical fiber connection, or other network link dedicated to memory access operations, etc.) 1690, 1692, 1694, 1696 between the CPU and the memory pool controller 1660. Further, each of the CPUs 1680 and 1682 (and similarly, CPUs 1684 and 1686) may communicate with one another, such as through an interconnect bus. Each compute sled 1630 may determine an interleaving configuration that alternates communication links from a given CPU to the memory pool controller 1660. The interleaving configuration may expose a memory address space local to a given compute sled 1630, where a first memory address uses a first communication link, a second memory address (e.g., immediately following the first memory address) uses a second communication link, a third memory address (e.g., immediately following the second memory address) uses the first communication link, and so on, such that the accesses to sequential memory addresses actually result in data access operations occurring on different communication links.
In addition, the memory pool controller 1660 also may interleave access across the various memory devices of the memory pool 1670. In some embodiments, the orchestrator server 1620 may send a request to the memory pool controller 1660 to allocate one or more memory address ranges to a compute sled 1630. The request may specify various parameters, such as an amount of memory to be allocated to the compute sled 1630, memory characteristics associated with the compute sled 1630, whether to enable memory interleaving, and the like. The memory pool controller 1660, in turn, determines an interleaving configuration based on one or more memory characteristics associated with the compute sled 1630, such as bandwidth characteristics of the CPUs 1680 and 1682 and/or a Quality of Service (QoS) target associated with a group of customers having workloads to be executed on the compute sled 1630. The memory pool controller 1660 may select, as a function of the determined interleaving configuration, a subset of memory devices in the memory pool 1670 for access by the compute sled 1630. Further, the memory pool controller 1660 may then expose a memory address space to the compute sled 1630 that interleaves read/write access to each of the subset of memory devices. Advantageously, the memory devices of the subset may have characteristics that satisfy QoS targets. For instance, for relatively high QoS targets, the subset may include memory devices that provide for relatively quick read/write access. For example, a given memory address may map to a location on a first memory device, followed by a subsequent memory address mapping to a location on a second memory device, and so on, such that each memory address is mapped in an interleaved fashion to each of the subset of memory devices.
Further still, the orchestrator server 1620 may adjust the interleaving configuration set by the memory pool controller 1660 on behalf of the compute sled 1630. For instance, the orchestrator server 1620 may obtain telemetry data associated with the compute sled 1630 to the memory pool 1670 relating to memory access under the present interleaving configuration. The orchestrator server 1620 may then evaluate the data against one or more QoS targets to determine whether the present interleaving configuration satisfies the QoS targets. For example, the orchestrator server 1620 may measure a memory throughput associated with the compute sled 1630 relative to the memory pool 1670. The orchestrator server 1620 may then evaluate whether the memory throughput falls below, is within, or exceeds a QoS target for the memory throughput. The orchestrator server 1620 may, based on the evaluation, modify the interleaving configuration of the memory pool 1670 for the compute sled 1630 such that the memory throughput is within the target QoS. For instance, the orchestrator server 1620 may cause the memory sled 1640 to include additional memory devices in the interleaving configuration, select a subset of memory devices that have a generally higher access speed, select a subset of memory devices that have a generally lower access speed, and the like.
Referring now to
As shown in
The compute engine 1702 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1702 may be embodied as a single device such as an integrated circuit, an embedded system, an FPGA, a system-on-a-chip (SOC), or other integrated system or device. Additionally, in some embodiments, the compute engine 1702 includes or is embodied as a processor 1704 and a memory 1706. The processor 1704 may be embodied as one or more processors, each processor being a type capable of performing the functions described herein. For example, the processor 1704 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, the processor 1704 may be embodied as, include, or be coupled to an FPGA, an ASIC, reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. Illustratively, the processor 1704 includes a memory interleave logic unit 1720, which may be embodied as any device or circuitry (e.g., a processor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.) capable of configuring memory links of the processor 1704 according to a determined interleaving configuration.
The memory 1706 may be embodied as any type of volatile (e.g., dynamic random access memory (DRAM), etc.) or non-volatile memory or data storage capable of performing the functions described herein. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as DRAM or static random access memory (SRAM). One particular type of DRAM that may be used in a memory module is synchronous dynamic random access memory (SDRAM). In particular embodiments, DRAM of a memory component may comply with a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at www.jedec.org). Such standards (and similar standards) may be referred to as DDR-based standards and communication interfaces of the storage devices that implement such standards may be referred to as DDR-based interfaces.
In one embodiment, the memory device is a block addressable memory device, such as those based on NAND or NOR technologies. A memory device may also include future generation nonvolatile devices, such as a three dimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), or other byte addressable write-in-place nonvolatile memory devices. In one embodiment, the memory device may be or may include memory devices that use chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive random access memory (MRAM) memory that incorporates memristor technology, resistive memory including the metal oxide base, the oxygen vacancy base and the conductive bridge Random Access Memory (CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic junction memory based device, a magnetic tunneling junction (MTJ) based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristor based memory device, or a combination of any of the above, or other memory. The memory device may refer to the die itself and/or to a packaged memory product.
In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™ memory) may comprise a transistor-less stackable cross point architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance. In some embodiments, all or a portion of the memory 1706 may be integrated into the processor 1704. In operation, the memory 1706 may store various software and data (e.g., memory map data, interleave policy data) used during operation of the compute sled in the system 1610.
The compute engine 1702 is communicatively coupled with other components of other compute sleds 1630 and the memory sleds 1640 and 1650 via the I/O subsystem 1708, which may be embodied as circuitry and/or components to facilitate input/output operations with the compute engine 1702 (e.g., with the processor 1704 and/or the memory 1706) and other components of the compute sled 1630. For example, the I/O subsystem 1708 may be embodied as, or otherwise include, memory controller hubs, input/output control hubs, integrated sensor hubs, firmware devices, communication links (e.g., point-to-point links, bus links, wires, cables, light guides, printed circuit board traces, etc.), and/or other components and subsystems to facilitate the input/output operations. In some embodiments, the I/O subsystem 1708 may form a portion of a system-on-a-chip (SoC) and be incorporated, along with one or more of the processor 1704, the memory 1706, and other components of the compute sled 1630, into the compute engine 1702.
The communication circuitry 1710 may be embodied as any communication circuit, device, or collection thereof, capable of enabling communications over the network 1612 between the compute sled 1630 and another compute device (e.g., other compute sleds 1630, the orchestrator server 1620, memory sleds 1640 and 1650, etc.). The communication circuitry 1710 may be configured to use any one or more communication technology (e.g., wired or wireless communications) and associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, etc.) to effect such communication.
The illustrative communication circuitry 1710 includes a network interface controller (NIC) 1712, which may also be referred to as a host fabric interface (HFI). The NIC 1712 may be embodied as one or more add-in-boards, daughter cards, network interface cards, controller chips, chipsets, or other devices that may be used by the compute sled 1630 to connect with another compute device (e.g., other compute sleds 1630, the orchestrator server 1620, etc.). In some embodiments, the NIC 1712 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors, or included on a multichip package that also contains one or more processors. In some embodiments, the NIC 1712 may include a local processor (not shown) and/or a local memory (not shown) that are both local to the NIC 1712. In such embodiments, the local processor of the NIC 1712 may be capable of performing one or more of the functions of the compute engine 1702 described herein. Additionally or alternatively, in such embodiments, the local memory of the NIC 1712 may be integrated into one or more components of the compute sled 1630 at the board level, socket level, chip level, and/or other levels.
The one or more illustrative data storage devices 1714, may be embodied as any type of devices configured for short-term or long-term storage of data such as, for example, memory devices and circuits, memory cards, hard disk drives (HDDs), solid-state drives (SSDs), or other data storage devices. Each data storage device 1714 may include a system partition that stores data and firmware code for the data storage device 1714. Each data storage device 1714 may also include an operating system partition that stores data files and executables for an operating system.
Referring now to
As shown in
The compute engine 1802 may be embodied as any type of device or collection of devices capable of performing various compute functions described below. In some embodiments, the compute engine 1802 may be embodied as a single device such as an integrated circuit, an embedded system, a field-programmable gate array (FPGA), a system-on-a-chip (SOC), or other integrated system or device. In the illustrative embodiment, the compute engine 1802 includes or is embodied as the memory pool controller 1660 and the memory pool 1670 (also referred to herein as memory). The memory pool controller 1660 may be embodied as any type of device or circuitry capable of performing the functions described herein. For example, the memory pool controller 1660 may be embodied as a single or multi-core processor(s), a microcontroller, or other processor or processing/controlling circuit. In some embodiments, the memory pool controller 1660 may be embodied as, include, or be coupled to an FPGA, an application specific integrated circuit (ASIC), reconfigurable hardware or hardware circuitry, or other specialized hardware to facilitate performance of the functions described herein. In the illustrative embodiment, the memory pool controller 1660 includes one or more channel interleave logic units 1820, which may be embodied as any device or circuitry (e.g., processor(s), ASICs, FPGAs, etc.) capable of selectively enabling access (e.g., read access and/or write access) to regions of memory addresses of the memory 1670 to each compute sled 1630, each memory address mapping to a memory device of the memory pool 1670 in an interleaved manner The memory 1670 may be embodied as multiple (e.g., a pool of) memory devices of the types described with reference to the memory 1706.
The compute engine 1802 is communicatively coupled to other components of the memory sled 1640 via the I/O subsystem 1804, which is similar to the I/O subsystem 1708 described with reference to
Referring now to
The compute engine 1902 may be embodied as any type of device or collection of devices capable of performing various compute functions described below, and is similar to the compute engine 1702 of
The memory sled 1650 and client device 1614 may have components similar to those described in
As described above, the orchestrator server 1620, the sleds 1630, 1640, 1650, and the client device 1614 are illustratively in communication via the network 1612, which may be embodied as any type of wired or wireless communication network, including global networks (e.g., the Internet), local area networks (LANs) or wide area networks (WANs), cellular networks (e.g., Global System for Mobile Communications (GSM), 3G, Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), etc.), digital subscriber line (DSL) networks, cable networks (e.g., coaxial networks, fiber networks, etc.), or any combination thereof.
Referring now to
In the illustrative environment 2000, the network communicator 2020, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the memory sled 1640, respectively. To do so, the network communicator 2020 is configured to receive and process data packets from one system or computing device (e.g., a compute sled 1630, the orchestrator server 1620, etc.) and to prepare and send data packets to a computing device or system (e.g., a compute sled 1630, the orchestrator server 1620, etc.). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 2020 may be performed by the communication circuitry 1806, and, in the illustrative embodiment, by the NIC 1808.
The memory access manager 2030, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to allocate memory addresses of the memory pool to the compute sled 1630, where the memory addresses are configured according to an interleaving configuration determined as a function of one or more memory characteristics of the compute sled 1630 (e.g., CPU bandwidth, QoS performance targets, and the like). To do so, the memory access manager 2030, in the illustrative embodiment, includes a memory mapper 2032, an interleaver 2034, a data writer 2036, and a data reader 2038.
The memory mapper 2032, in the illustrative embodiment, is configured to receive an allocation request from a remote compute device (e.g., a compute sled 1630 or the orchestrator server 1620) to allocate one or more regions of pooled byte-addressable (e.g., addressable by one or more bytes, less than a block) memory (e.g., the memory 1670) to one or more compute sleds 1630 and produce address space data for each compute sled indicative of the pooled byte-addressable memory accessible to the compute sled. For example, the orchestrator server 1620, on behalf of the compute sled 1630, may specify an amount of memory to be allocated on the compute sled 1630. The pooled byte-addressable memory corresponds to each of the memory devices of the memory pool 1670 (e.g., the entire memory pool 1670). Further, the memory mapper 2032 is configured to verify parameters of any memory access or allocation requests from the compute sled 1630.
The interleaver 2034, in the illustrative embodiment, is configured to evaluate the interleave policy data 2004 and determine, as a function of the evaluation, an interleaving configuration of the address space data produced by the memory mapper 2032. For example, the interleave policy data 2004 may specify subsets of the memory devices in the memory pool 1670 to interleave based on memory characteristics and QoS targets of the compute sled 1630, such as whether to use a given amount of memory devices, a given type of memory, and the like. Once determined, the interleaver 2034 configures the address space data according to the interleaving configuration. For instance, the interleaver 2034 may map the address space data to the one or more compute sleds such that each successive memory address maps to a different memory device via memory channels connecting with the memory devices.
The data writer 2036, in the illustrative embodiment, is configured to write data to the memory 1670 in response to a request (e.g., from a compute sled 1630) to perform a write operation at a memory address associated with the request. Similarly, the data reader 2038, in the illustrative embodiment, is configured to read data from the memory 1670 in response to a request (e.g., from a compute sled 1630) to perform a read operation at a memory address associated with the request.
It should be appreciated that each of the memory mapper 2032, the interleaver 2034, the data writer 2036, and the data reader 2038 may be separately embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof. For example, the memory mapper 2032 and interleaver 2034 may be embodied as hardware components, while the data writer 2036 and the data reader 2038 are embodied as virtualized hardware components or as some other combination of hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof.
Referring now to
In the illustrative environment 2100, the network communicator 2120, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the compute sled 1630, respectively. To do so, the network communicator 2120 is configured to receive and process data packets from one system or computing device (e.g., a compute sled 1630, the orchestrator server 1620, etc.) and to prepare and send data packets to a computing device or system (e.g., memory sleds 1640 and 1650, the orchestrator server 1620, etc.). Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 2120 may be performed by the communication circuitry 1710, and, in the illustrative embodiment, by the NIC 1712.
The memory interleaver 2130, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is to allocate memory addresses of the memory pool to the compute sled 1630, where the memory addresses are mapped according to an interleaving configuration determined as a function of one or more memory characteristics of the compute sled 1630 (e.g., CPU bandwidth, QoS performance targets, and the like). To do so, the memory interleaver 2130 includes a receiver component 2132, an evaluation component 2134, and a configuration component 2136.
The receiver component 2132, in the illustrative embodiment, is configured to obtain an allocation of memory addresses associated with the memory pool 1670. More particularly, the receiver component 2132 may receive a notification from the memory sled 1640 (or 1650) of an allocation of logical memory address regions that provide access to the memory devices of the memory pool 1670. For instance, the memory sled 1640 may allocate the logical memory address regions in response to a request, such as from the orchestrator server 1620 on behalf of the compute sled 1630, or from the compute sled 1630 itself.
The evaluation component 2134, in the illustrative embodiment is configured to evaluate the interleave policy data 2104 to determine an interleaving configuration for accessing each of the allocated memory addresses. For example, the interleave policy data 2104 may specify whether to use an n-way interleaving scheme to satisfy workload requirements. For each interleaving scheme, the interleave policy data 2104 may specify an amount of memory links from a given processor 1704 to use to access the memory devices at the allocated memory addresses.
The configuration component 2136, in the illustrative embodiment, is configured to assign the allocated memory addresses to the memory links according to the evaluated interleave policy data 2104. For example, the evaluation component 2134 may determine that a 2-way interleaving should be used in view of the evaluated interleave policy data 2104 and performance targets (e.g., pursuant to a service level agreement) of one or more workloads to be executed on the compute sled 1630. In such a case, the configuration component 2136 may specify a mapping (e.g., in the memory map data 2102) of a memory link A of the processor 1704 to a first address in the address space, memory link B to a second address, and so on, such that links A and B alternate in mapping for each successive allocated memory address. Once mapped, the memory interleaver 2130 (or other component on the compute sled 1630) may perform memory access operations to the memory addresses of the memory pool 1670 under the present interleaving configuration.
Referring now to
In the illustrative environment 2200, the network communicator 2220, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof as discussed above, is configured to facilitate inbound and outbound network communications (e.g., network traffic, network packets, network flows, etc.) to and from the orchestrator server 1620, respectively. To do so, the network communicator 2220 is configured to receive and process data packets from one system or computing device (e.g., one of the compute sleds 1630, the memory sled 1640 or 1650, etc.) and to prepare and send data packets to a computing device or system. Accordingly, in some embodiments, at least a portion of the functionality of the network communicator 2220 may be performed by the communication circuitry 1910, and, in the illustrative embodiment, by the NIC 1912.
The resource manager 2230, which may be embodied as hardware, firmware, software, virtualized hardware, emulated architecture, and/or a combination thereof, is configured to determine QoS performance targets (e.g., QoS data 2204) associated with a compute sled 1630, determine whether a present interleaving configuration by the memory pool controller 1660 to the compute sled 1630 satisfies the QoS performance targets, and modify the interleaving configuration as a function of the QoS performance targets. To do so, the resource manager 2230 includes an evaluation component 2232, an adjuster component 2234, and an output component 2236.
The evaluation component 2232, in the illustrative embodiment, is configured to evaluate the QoS data 2204 associated with a compute sled 1630 relative to the present interleaving configuration provided by the memory pool controller 1660 to the compute sled 1630. In particular, the evaluation component 2232 may determine whether memory-related QoS targets are satisfied based on the present interleaving configuration. For example, the QoS data 2204 may specify memory throughput targets to be satisfied by the compute sled 1630. The evaluation component 2232 may obtain, via performance monitors executing in the system 1610, telemetry data relating to the execution of a given workload to determine present memory throughput. The evaluation component 2232 may further compare the present throughput value with the QoS data 2204 associated with a throughput target and determine whether the present value is in range of the target, exceeds a target threshold, or falls below a target threshold.
The adjuster component 2234, in the illustrative embodiment, is configured to determine a modification to the interleaving configuration set by the memory pool controller 1660 in response to determining that the present interleaving configuration results in a deviation from targets specified by the QoS data 2204 for the compute sled 1630. For instance, if the evaluation component 2232 determines that a presently observed memory throughput falls below a corresponding QoS performance target by a specified threshold, the adjuster component 2234 may determine that additional memory devices (falling within the bounds of the QoS data 2204) should be included as part of the interleaving configuration. As another example, if the evaluation component 2232 determines that a presented observed memory throughput exceeds a corresponding QoS performance target by another specified threshold, then the adjuster component 2234 may determine that fewer memory devices should form the interleaving configuration. The adjuster component 2234 may determine the configuration as a function of characteristics of the memory devices in the memory pool 1670 (e.g., type, speed, availability, etc.) and the QoS targets for the compute sled 1630.
The output component 2236, in the illustrative embodiment, is configured to generate a notification for the memory sled 1640 (or 1650) to adjust the interleaving configuration according to the determined modification. The notification may include, for example, an instruction for the memory sled 1640 to allocate (or deallocate) memory channels connecting to the memory devices to (or from) the compute sled 1630 and configure the interleaving for the presently allocated memory channels. Further, the output component 2236 is configured to send, to the compute sled 1630, a notification of the modification of the configuration.
Referring now to
In block 2304, the memory sled 1640 determines an interleaving configuration for the compute sled 1630 as a function of the memory characteristics and QoS targets associated with the compute sled 1630. In particular, in block 2306, the memory sled 1640 determines a CPU bandwidth and the QoS targets associated with the compute sled 1630. For instance, the memory sled 1640 may obtain such information from the request sent by the orchestrator server 1620. Once determined, in block 2308, the memory sled 1640 identifies one or more available memory channels connecting to the memory devices of the memory pool 1670 to interleave as a function of the determination. To do so, the memory sled 1640 may evaluate memory devices of the memory pool 1670 that are available to service the request. Further, the memory sled 1640 may determine, from the available memory devices, a subset of the available memory devices that potentially satisfy QoS performance targets (e.g., based on predefined characteristics of the memory device, such as input/output speed, memory capacity, etc.).
In block 2310, the memory sled 1640 configures memory pool resources (e.g., logical memory addresses each corresponding to a physical location on a given memory device in the memory pool 1670) according to the determined interleaving configuration. In particular, in block 2312, the memory sled 1640 exposes a logical address space having memory addresses corresponding to an interleaving of memory channels to the memory devices of the memory pool 1670. For example, the determined interleaving configuration may include channels connecting with a memory device A, a memory device B, or a memory device C. A first logical address may be mapped to memory device A, a second logical address may be mapped to memory device B, a third logical address may be mapped to memory device C, and so on, such that successive logical addresses alternative between memory devices A, B, and C.
In block 2314, the memory sled 1640 sends a notification of the allocation of the memory addresses to the compute sled 1630. The memory sled 1640 may also send the notification the orchestrator server 1620 in response to the request. Once allocated, in block 2316, the memory sled 1640 performs memory access operations on behalf of the compute sled 1630. For instance, in block 2318, the memory sled 1640 writes to the memory at addresses to which the compute sled 1630 has write permission. In block 2320, the memory sled 1640 reads from the memory at addresses to which the compute sled 1630 has read permission. Advantageously, the interleaving configuration allows the memory sled 1640 to access the memory at requested locations at a relatively faster rate than if the memory address space was allocated such that contiguous memory addresses were located on a single memory device due to possible waiting times on the memory device for subsequent memory operations.
Referring now to
In block 2404, the compute sled 1630 determines whether memory interleaving is currently enabled for use within the compute sled 1630. For instance, memory interleaving may be enabled as part of a service level agreement (SLA) for a given user or group of users having workloads to be executed on the compute sled 1630. If memory interleaving for use within the compute sled 1630 is not enabled, then the method 2400 ends. Otherwise, in block 2406, the compute sled 1630 determines a configuration for memory interleaving across one or more links of a given processor (e.g., a CPU 1680, 1682). In particular, in block 2408, the compute sled 1630 evaluates one or more interleaving policies associated with the processor. For example, an interleaving policy may indicate that, based on present workloads to be executed on the compute sled 1630, a given n-way interleaving should be used.
In block 2410, the compute sled 1630 configures the interleaving as a function of the determination. In particular, in block 2412, the compute sled 1630 assigns each of the allocated memory addresses to one of the processor memory links according to the determined interleaving policy. The assignment is performed in an interleaved manner such that each contiguous address is assigned to a different memory link. Once assigned, in block 2414, the compute sled 1630 performs memory operations to the memory addresses of the memory pool using the configured interleaving. For example, the compute sled 1630 may send requests to the memory sled 1640 that includes the type of memory operation (e.g., read or write operation) and a memory address at which to perform the operation. By interleaving access to the memory pool 1670 by processor memory links for contiguous memory addresses, the compute sled 1630 enables relatively faster operations to be performed on the memory (e.g., by avoiding the wait time involved with using the same memory link to access the memory pool 1670 at contiguous addresses).
Referring now to
In block 2504, the orchestrator server 1620 evaluates a present interleaving configuration of the compute sled 1630. As stated, the memory sled 1640 may send a notification of a present configuration of interleaving for a compute sled 1630 to the orchestrator server 1620 when memory is allocated to the compute sled 1630. Further, the orchestrator server 1620 may observe telemetry data during execution of workloads by the compute sled 1630 (e.g., using a performance monitor executing in the system 1610). The telemetry data may be indicative of memory utilization metrics. In block 2506, the orchestrator server 1620 determines, based on the notification provided by the memory sled 1640 and the present execution of the workloads by the compute sled 1630, whether the present interleaving configuration satisfies the QoS performance targets. For example, the orchestrator server 1620 determines whether presently observed metrics relating to memory fall within a specified target range, exceed a specified threshold, or fall below another specified threshold. If the present configuration satisfies the performance targets, then the method 2500 loops back to block 2504.
Otherwise, in block 2508, the orchestrator server 1620 modifies the interleaving configuration as a function of the QoS performance targets. In particular, in block 2510, the orchestrator server 1620 causes (e.g., sends an instruction to) the memory sled 1640 to allocate (or deallocate) memory channels to the compute sled 1630 such that the QoS performance targets are satisfied. For instance, the orchestrator server 1620 may indicate that additional memory devices (falling within the scope of an SLA) should be included with the interleaving configuration. The orchestrator server 1620 may send an instruction to the memory pool controller 1660 to add those devices (e.g., by providing an identifier associated with the memory devices in the instruction). As another example, the orchestrator server 1620 may indicate that some of the memory devices associated with the interleaving configuration should be removed therefrom. The orchestrator server 1620 may send an instruction to the memory pool controller 1660 to remove the identified devices (e.g., by identifiers associated with the memory devices). Further, in block 2512, the orchestrator server 1620 causes the memory sled 1640 to configure interleaving for the presently allocated channels. In turn, the memory pool controller 1660 may reconfigure the interleaving to reflect the change in memory devices associated with the interleaving configuration. In block 2514, the orchestrator server 1620 may send a notification of the modification of the interleaving configuration to the compute sled 1630. Subsequently, the method 2500 returns to block 2504, in which the orchestrator server 1620 evaluates the modified interleaving configuration during execution of the one or more workloads by the compute sled 1630 and determine whether the modified interleaving configuration satisfies the one or more QoS performance targets.
EXAMPLESIllustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes a memory sled, comprising a memory pool comprising one or more byte-addressable memory devices; a memory pool controller coupled to the memory pool, wherein the memory pool controller is to (i) receive a request to allocate a plurality of memory addresses of the memory pool to a compute sled, (ii) determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices, and (iii) configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.
Example 2 includes the subject matter of Example 1, and wherein to determine the interleaving configuration for the compute sled comprises to determine a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and identify, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein to configure the plurality of memory addresses of the memory pool comprises to expose an address space that includes the one or more memory addresses.
Example 4 includes the subject matter of any of Examples 1-3, and wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices.
Example 5 includes the subject matter of any of Examples 1-4, and wherein the memory pool controller is further to send a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool.
Example 6 includes the subject matter of any of Examples 1-5, and wherein the memory pool controller is further to receive, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and write, in response to the command, to the one or more memory addresses.
Example 7 includes the subject matter of any of Examples 1-6, and wherein the memory pool controller is further to receive, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and read, in response to the command, from the one or more memory addresses.
Example 8 includes the subject matter of any of Examples 1-7, and wherein the interleaved access is to a subset of the one or more memory devices of the memory pool.
Example 9 includes the subject matter of any of Examples 1-8, and wherein the memory pool controller is further to receive, from an orchestrator server, a modification of the determined interleaving configuration.
Example 10 includes the subject matter of any of Examples 1-9, and wherein the modification of the interleaving configuration is determined as a function of a QoS target.
Example 11 includes the subject matter of any of Examples 1-10, and wherein the modification is indicative of an addition of one or more of the memory devices to the interleaving configuration.
Example 12 includes the subject matter of any of Examples 1-11, and wherein the memory pool controller is further to configure one or more additional memory addresses of the memory pool according to the modification of the determined interleaving configuration, wherein each of the one or more additional memory addresses corresponds to an interleaving of additional memory channels connecting with the one or more memory devices.
Example 13 includes the subject matter of any of Examples 1-12, and wherein the modification is indicative of a removal of one or more of the memory devices from the interleaving configuration.
Example 14 includes a method comprising receiving, by a memory sled, a request to allocate a plurality of memory addresses of a memory pool to a compute sled, wherein the memory pool includes one or more byte-addressable memory devices, determining, by the memory sled, an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices; and configuring, by the memory sled, the one or more memory addresses of the memory pool according to the determined interleaving configuration.
Example 15 includes the subject matter of Example 14, and wherein determining the interleaving configuration for the compute sled comprises determining a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and identifying, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.
Example 16 includes the subject matter of any of Examples 14 and 15, and wherein configuring the plurality of memory addresses of the memory pool comprises exposing an address space that includes the one or more memory addresses.
Example 17 includes the subject matter of any of Examples 14-16, and wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices.
Example 18 includes the subject matter of any of Examples 14-17, and further including sending a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool.
Example 19 includes the subject matter of any of Examples 14-18, and further including receiving, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and writing, in response to the command, to the one or more memory addresses.
Example 20 includes the subject matter of any of Examples 14-19, and further including receiving, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and reading, in response to the command, from the one or more memory addresses.
Example 21 includes the subject matter of any of Examples 14-20, and wherein the interleaved access is to a subset of the one or more memory devices of the memory pool.
Example 22 includes the subject matter of any of Examples 14-21, and further including receiving, from an orchestrator server, a modification of the determined interleaving configuration.
Example 23 includes the subject matter of any of Examples 14-22, and wherein the modification of the interleaving configuration is determined as a function of a QoS target.
Example 24 includes the subject matter of any of Examples 14-23, and wherein the modification is indicative of an addition of one or more of the memory devices to the interleaving configuration.
Example 25 includes the subject matter of any of Examples 14-24, and further including configuring one or more additional memory addresses of the memory pool according to the modification of the determined interleaving configuration, wherein each of the one or more additional memory addresses corresponds to an interleaving of additional memory channels connecting with the one or more memory devices.
Example 26 includes the subject matter of any of Examples 14-25, and wherein the modification is indicative of a removal of one or more of the memory devices from the interleaving configuration.
Example 27 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a memory sled to perform the method of any of Examples 14-26.
Example 28 includes a memory sled comprising means for performing the method of any of Examples 14-26.
Example 29 includes a memory sled comprising a compute engine to perform the method of any of Examples 14-26.
Example 30 includes a memory sled comprising a memory pool comprising one or more byte-addressable memory devices; means for receiving a request to allocate a plurality of memory addresses of the memory pool to a compute sled; means for determining an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices; and means for configuring the one or more memory addresses of the memory pool according to the determined interleaving configuration.
Example 31 includes the subject matter of Example 30, and wherein the means for determining the interleaving configuration for the compute sled comprises means for determining a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and means for identifying, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.
Example 32 includes the subject matter of any of Examples 30 and 31, and wherein the means for configuring the plurality of memory addresses of the memory pool comprises means for exposing an address space that includes the one or more memory addresses.
Example 33 includes the subject matter of any of Examples 30-32, and wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices.
Example 34 includes the subject matter of any of Examples 30-33, and further including means for sending a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool.
Example 35 includes the subject matter of any of Examples 30-34, and further including means for receiving, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and means for writing, in response to the command, to the one or more memory addresses.
Example 36 includes the subject matter of any of Examples 30-35, and further including means for receiving, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and means for reading, in response to the command, from the one or more memory addresses.
Example 37 includes the subject matter of any of Examples 30-36, and wherein the interleaved access is to a subset of the one or more memory devices of the memory pool.
Example 38 includes the subject matter of any of Examples 30-37, and further including means for receiving, from an orchestrator server, a modification of the determined interleaving configuration.
Example 39 includes the subject matter of any of Examples 30-38, and wherein the modification of the interleaving configuration is determined as a function of a QoS target.
Example 40 includes the subject matter of any of Examples 30-39, and wherein the modification is indicative of an addition of one or more of the memory devices to the interleaving configuration.
Example 41 includes the subject matter of any of Examples 30-40, and further including means for configuring one or more additional memory addresses of the memory pool according to the modification of the determined interleaving configuration, wherein each of the one or more additional memory addresses corresponds to an interleaving of additional memory channels connecting with the one or more memory devices.
Example 42 includes the subject matter of any of Examples 30-41, and wherein the modification is indicative of a removal of one or more of the memory devices from the interleaving configuration.
Example 43 includes a compute sled comprising a compute engine having a first processor and a second processor, the compute engine to (i) receive, from a memory sled, an allocation of one or more memory addresses of a memory address space of a memory pool, wherein the memory pool includes one or more byte-addressable memory devices, (ii) determine an interleaving configuration that provides access to the one or more memory addresses via one or more memory links that are each coupled with one of the first processor or the second processor, and (iii) configure access to the one or more memory addresses via the one or more memory links according to the determined interleaving configuration.
Example 44 includes the subject matter of Example 43, and wherein to determine the interleaving configuration comprises to evaluate one or more interleaving policies associated with the first processor and the second processor.
Example 45 includes the subject matter of any of Examples 43 and 44, and wherein the one or more interleaving policies are based on bandwidth characteristics of the first processor and the second processor.
Example 46 includes the subject matter of any of Examples 43-45, and wherein the compute engine is further to assign access to each of the memory addresses to one of the memory links as a function of the evaluated interleaving policies.
Example 47 includes the subject matter of any of Examples 43-46, and wherein the compute engine is further to perform a read operation on the one or more memory addresses of the memory pool using the determined interleaving configuration.
Example 48 includes the subject matter of any of Examples 43-47, and wherein the compute engine is further to perform a write operation on the one or more memory addresses of the memory pool using the determined interleaving configuration.
Example 49 includes the subject matter of any of Examples 43-48, and wherein the compute engine is further to determine whether interleaving is enabled for the first processor and the second processor.
Example 50 includes the subject matter of any of Examples 43-49, and wherein the compute engine is further to send a request to the memory sled for the allocation of the one or more memory addresses.
Example 51 includes a method comprising receiving, by a compute sled and from a memory sled, an allocation of one or more memory addresses of a memory address space of a memory pool, wherein the memory pool includes one or more byte-addressable memory devices; determining, by the compute sled, an interleaving configuration that provides access to the one or more memory addresses via one or more memory links that are each coupled with one of a first processor or a second processor; and configuring, by the compute sled, access to the one or more memory addresses via the one or more memory links according to the determined interleaving configuration.
Example 52 includes the subject matter of Example 51, and wherein determining the interleaving configuration comprises evaluating one or more interleaving policies associated with the first processor and the second processor.
Example 53 includes the subject matter of any of Examples 51 and 52, and wherein the one or more interleaving policies are based on bandwidth characteristics of the first processor and the second processor.
Example 54 includes the subject matter of any of Examples 51-53, and further including assigning, by the compute sled, access to each of the memory addresses to one of the memory links as a function of the evaluated interleaving policies.
Example 55 includes the subject matter of any of Examples 51-54, and further including performing, by the compute sled, a read operation on the one or more memory addresses of the memory pool using the determined interleaving configuration.
Example 56 includes the subject matter of any of Examples 51-55, and further including performing, by the compute sled, a write operation on the one or more memory addresses of the memory pool using the determined interleaving configuration.
Example 57 includes the subject matter of any of Examples 51-56, and further including determining, by the compute sled, whether interleaving is enabled for the first processor and the second processor.
Example 58 includes the subject matter of any of Examples 51-57, and further including sending, by the compute sled, a request to the memory sled for the allocation of the one or more memory addresses.
Example 59 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute sled to perform the method of any of Examples 51-58.
Example 60 includes a compute sled comprising means for performing the method of any of Examples 51-58.
Example 61 includes a compute sled comprising a compute engine to perform the method of any of Examples 51-58.
Example 62 includes a compute sled comprising means for receiving, from a memory sled, an allocation of one or more memory addresses of a memory address space of a memory pool, wherein the memory pool includes one or more byte-addressable memory devices; means for determining an interleaving configuration that provides access to the one or more memory addresses via one or more memory links that are each coupled with one of a first processor or a second processor; and means for configuring access to the one or more memory addresses via the one or more memory links according to the determined interleaving configuration.
Example 63 includes the subject matter of Example 62, and wherein the means for determining the interleaving configuration comprises means for evaluating one or more interleaving policies associated with the first processor and the second processor.
Example 64 includes the subject matter of any of Examples 62 and 63, and wherein the one or more interleaving policies are based on bandwidth characteristics of the first processor and the second processor.
Example 65 includes the subject matter of any of Examples 62-64, and further including means for assigning access to each of the memory addresses to one of the memory links as a function of the evaluated interleaving policies.
Example 66 includes the subject matter of any of Examples 62-65, and further including means for performing a read operation on the one or more memory addresses of the memory pool using the determined interleaving configuration.
Example 67 includes the subject matter of any of Examples 62-66, and further including means for performing a write operation on the one or more memory addresses of the memory pool using the determined interleaving configuration.
Example 68 includes the subject matter of any of Examples 62-67, and further including means for determining whether interleaving is enabled for the first processor and the second processor.
Example 69 includes the subject matter of any of Examples 62-68, and further including means for sending a request to the memory sled for the allocation of the one or more memory addresses.
Example 70 includes a compute device comprising a compute engine to (i) determine a target quality of service (QoS) for a compute sled, wherein the compute sled is presently configured with a interleaving configuration that provides access, via a memory sled, to a memory pool having one or more byte-addressable memory devices, (ii) determine whether the interleaving configuration satisfies the target QoS, and (iii) modify, in response to a determination that that the interleaving configuration does not satisfy the target QoS, the interleaving configuration as a function of the target QoS.
Example 71 includes the subject matter of Example 70, and wherein to modify the interleaving configuration comprises to cause the memory sled to allocate memory channels coupled with the memory devices to the compute sled to satisfy the QoS target; and cause the memory sled to configure interleaving for the allocated memory channels.
Example 72 includes the subject matter of any of Examples 70 and 71, and wherein to modify the interleaving configuration comprises to cause the memory sled to deallocate memory channels coupled with the memory devices from the compute sled to satisfy the QoS target; and cause the memory sled to configure interleaving for the allocated memory channels.
Example 73 includes the subject matter of any of Examples 70-72, and wherein the compute engine is further to send, to the compute sled, a notification of the modification of the interleaving configuration.
Example 74 includes the subject matter of any of Examples 70-73, and wherein the interleaving configuration is indicative of a mapping of a plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices.
Example 75 includes the subject matter of any of Examples 70-74, and wherein the interleaving configuration is indicative of a mapping of a plurality of memory addresses of the memory pool to an interleaved access to a first subset of the one or more memory devices.
Example 76 includes the subject matter of any of Examples 70-75, and wherein the modified interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to a second subset of the one or more memory devices.
Example 77 includes a method comprising determining, by a compute device, a target quality of service (QoS) for a compute sled, wherein the compute sled is presently configured with a interleaving configuration that provides access, via a memory sled, to a memory pool having one or more byte-addressable memory devices; determining, by the compute device, whether the interleaving configuration satisfies the target QoS; and modifying, in response to a determination that that the interleaving configuration does not satisfy the target QoS, the interleaving configuration as a function of the target QoS.
Example 78 includes the subject matter of Example 77, and wherein modifying the interleaving configuration comprises causing the memory sled to allocate memory channels coupled with the memory devices to the compute sled to satisfy the QoS target; and causing the memory sled to configure interleaving for the allocated memory channels.
Example 79 includes the subject matter of any of Examples 77 and 78, and wherein modifying the interleaving configuration comprises causing the memory sled to deallocate memory channels coupled with the memory devices from the compute sled to satisfy the QoS target; and causing the memory sled to configure interleaving for the allocated memory channels.
Example 80 includes the subject matter of any of Examples 77-79, and further including sending a notification of the modification of the interleaving configuration to the compute sled.
Example 81 includes the subject matter of any of Examples 77-80, and wherein the interleaving configuration is indicative of a mapping of a plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices.
Example 82 includes the subject matter of any of Examples 77-81, and wherein the interleaving configuration is indicative of a mapping of a plurality of memory addresses of the memory pool to an interleaved access to a first subset of the one or more memory devices.
Example 83 includes the subject matter of any of Examples 77-82, and wherein the modified interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to a second subset of the one or more memory devices.
Example 84 includes one or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute device to perform the method of any of Examples 77-83.
Example 85 includes a compute device comprising means for performing the method of any of Examples 77-83.
Example 86 includes a compute device comprising a compute engine to perform the method of any of Examples 77-83.
Example 87 includes a compute device comprising means for determining a target quality of service (QoS) for a compute sled, wherein the compute sled is presently configured with a interleaving configuration that provides access, via a memory sled, to a memory pool having one or more byte-addressable memory devices; means for determining whether the interleaving configuration satisfies the target QoS; and means for modifying, in response to a determination that that the interleaving configuration does not satisfy the target QoS, the interleaving configuration as a function of the target QoS.
Example 88 includes the subject matter of Example 87, and wherein the means for modifying the interleaving configuration comprises means for causing the memory sled to allocate memory channels coupled with the memory devices to the compute sled to satisfy the QoS target; and means for causing the memory sled to configure interleaving for the allocated memory channels.
Example 89 includes the subject matter of any of Examples 87 and 88, and wherein the means for modifying the interleaving configuration comprises means for causing the memory sled to deallocate memory channels coupled with the memory devices from the compute sled to satisfy the QoS target; and means for causing the memory sled to configure interleaving for the allocated memory channels.
Example 90 includes the subject matter of any of Examples 87-89, and further including means for sending a notification of the modification of the interleaving configuration to the compute sled.
Example 91 includes the subject matter of any of Examples 87-90, and wherein the interleaving configuration is indicative of a mapping of a plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices.
Example 92 includes the subject matter of any of Examples 87-91, and wherein the interleaving configuration is indicative of a mapping of a plurality of memory addresses of the memory pool to an interleaved access to a first subset of the one or more memory devices.
Example 93 includes the subject matter of any of Examples 87-92, and wherein the modified interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to a second subset of the one or more memory devices.
Example 94 includes a system comprising a compute sled; and a memory sled coupled to the compute sled, wherein the memory sled includes a memory pool comprising one or more byte-addressable memory devices; a memory pool controller coupled to the memory pool, wherein the memory pool controller is to (i) receive a request to allocate a plurality of memory addresses of the memory pool to the compute sled, (ii) determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices, and (iii) configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.
Claims
1. A memory sled, comprising:
- a memory pool comprising one or more byte-addressable memory devices;
- a memory pool controller coupled to the memory pool, wherein the memory pool controller is to: (i) receive a request to allocate a plurality of memory addresses of the memory pool to a compute sled, (ii) determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices, and (iii) configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.
2. The memory sled of claim 1, wherein to determine the interleaving configuration for the compute sled comprises to:
- determine a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and
- identify, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.
3. The memory sled of claim 2, wherein to configure the plurality of memory addresses of the memory pool comprises to expose an address space that includes the one or more memory addresses.
4. The memory sled of claim 3, wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices.
5. The memory sled of claim 1, wherein the memory pool controller is further to send a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool.
6. The memory sled of claim 1, wherein the memory pool controller is further to:
- receive, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and
- write, in response to the command, to the one or more memory addresses.
7. The memory sled of claim 1, wherein the memory pool controller is further to:
- receive, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and
- read, in response to the command, from the one or more memory addresses.
8. The memory sled of claim 1, wherein the interleaved access is to a subset of the one or more memory devices of the memory pool.
9. The memory sled of claim 1, wherein the memory pool controller is further to:
- receive, from an orchestrator server, a modification of the determined interleaving configuration.
10. The memory sled of claim 9, wherein the modification of the interleaving configuration is determined as a function of a QoS target.
11. The memory sled of claim 9, wherein the modification is indicative of an addition of one or more of the memory devices to the interleaving configuration.
12. The memory sled of claim 11, wherein the memory pool controller is further to configure one or more additional memory addresses of the memory pool according to the modification of the determined interleaving configuration, wherein each of the one or more additional memory addresses corresponds to an interleaving of additional memory channels connecting with the one or more memory devices.
13. The memory sled of claim 9, wherein the modification is indicative of a removal of one or more of the memory devices from the interleaving configuration.
14. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a memory sled to:
- receive a request to allocate a plurality of memory addresses of a memory pool to a compute sled, wherein the memory pool includes one or more byte-addressable memory devices,
- determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices; and
- configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.
15. The one or more non-transitory machine-readable storage media of claim 14, wherein to determine the interleaving configuration for the compute sled comprises to:
- determine a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and
- identify, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.
16. The one or more non-transitory machine-readable storage media of claim 15, wherein to configure the plurality of memory addresses of the memory pool comprises to expose an address space that includes the one or more memory addresses.
17. The one or more non-transitory machine-readable storage media of claim 16, wherein each of the one or more memory addresses corresponds to an interleaving of the identified one or more memory channels connecting with the one or more memory devices.
18. The one or more non-transitory machine-readable storage media of claim 14, wherein the plurality of instructions further cause the memory sled to send a notification, to a compute device, in response to the request to allocate the plurality of memory addresses of the memory pool.
19. The one or more non-transitory machine-readable storage media of claim 14, wherein the plurality of instructions further cause the memory sled to:
- receive, from the compute sled, a command to write to the one or more memory addresses configured according to the determined interleaving configuration; and
- write, in response to the command, to the one or more memory addresses.
20. The one or more non-transitory machine-readable storage media of claim 14, wherein the plurality of instructions further cause the memory sled to:
- receive, from the compute sled, a command to read from the one or more memory addresses configured according to the determined interleaving configuration; and
- read, in response to the command, from the one or more memory addresses.
21. The one or more non-transitory machine-readable storage media of claim 14, wherein the interleaved access is to a subset of the one or more memory devices of the memory pool.
22. A method comprising:
- receiving, by a memory sled, a request to allocate a plurality of memory addresses of a memory pool to a compute sled, wherein the memory pool includes one or more byte-addressable memory devices,
- determining, by the memory sled, an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices; and
- configuring, by the memory sled, the one or more memory addresses of the memory pool according to the determined interleaving configuration.
23. The method of claim 22, wherein determining the interleaving configuration for the compute sled comprises:
- determining a processor bandwidth and one or more quality of service (QoS) targets associated with the compute sled; and
- identifying, as a function of the determination of the processor bandwidth and the QoS targets, one or more memory channels connecting with the one or more memory devices to interleave.
24. The method of claim 23, wherein configuring the plurality of memory addresses of the memory pool comprises exposing an address space that includes the one or more memory addresses.
25. A system comprising:
- a compute sled; and
- a memory sled coupled to the compute sled, wherein the memory sled includes: a memory pool comprising one or more byte-addressable memory devices; a memory pool controller coupled to the memory pool, wherein the memory pool controller is to: (i) receive a request to allocate a plurality of memory addresses of the memory pool to the compute sled, (ii) determine an interleaving configuration for the compute sled as a function of one or more memory characteristics associated with the compute sled, wherein the interleaving configuration is indicative of a mapping of the plurality of memory addresses of the memory pool to an interleaved access to the one or more memory devices, and (iii) configure the one or more memory addresses of the memory pool according to the determined interleaving configuration.
Type: Application
Filed: Jan 11, 2018
Publication Date: Feb 7, 2019
Inventors: Mark Schmisseur (Phoenix, AZ), Dimitrios Ziakas (Hillsboro, OR), Murugasamy K. Nachimuthu (Beaverton, OR)
Application Number: 15/868,492
