Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A gate structure is formed on a III-V compound semiconductor layer. A gate silicide layer and a source/drain silicide layer are formed by an anneal process. The gate silicide layer is formed on the gate structure, the source/drain silicide layer is formed on the III-V compound semiconductor layer, and a material composition of the gate silicide layer is different from a material composition of the source/drain silicide layer.

Abstract: A gallium nitride (GaN) device with field plate structure, including a substrate, a gate on the substrate and a passivation layer covering on the gate, a source and a drain on the substrate and the passivation layer, a stop layer on the source, the drain and the passivation layer, and dual-damascene interconnects connecting respectively with the source and the drain, wherein the dual-damascene interconnect is provided with a via portion under the stop layer and a trench portion on the stop layer, and the via portion is connected with the source or the drain, and the trench portion of one of the dual-damascene interconnects extends horizontally toward the drain and overlaps the gate below in vertical direction, thereby functioning as a field plate structure for the GaN device.

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

Abstract: A method for forming ohmic contacts on a compound semiconductor device is disclosed. A channel layer is formed on a substrate. A barrier layer is formed on the channel layer. A passivation layer is formed on the barrier layer. A contact area is formed by etching through the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A sacrificial metallic layer is conformally deposited on the contact area. The sacrificial metallic layer is subjected to an annealing process, thereby forming a heavily doped region in the channel layer directly under the sacrificial metallic layer. The sacrificial metallic layer is removed to expose the heavily doped region. A metal silicide layer is formed on the heavily doped region.

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.

Abstract: A semiconductor structure including a first substrate, a first dielectric layer, a first oxygen doped carbide (ODC) bonding layer, a second substrate, a second dielectric layer, and a second ODC bonding layer is provided. The first dielectric layer is located on the first substrate. The first ODC bonding layer is located on the first dielectric layer. The second dielectric layer is located on the second substrate. The second ODC bonding layer is located on the second dielectric layer. The first ODC bonding layer and the second ODC bonding layer are bonded to each other.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A passivation layer is formed on the III-V compound barrier layer. A silicon layer is formed on the passivation layer, the III-V compound barrier layer, and the III-V compound semiconductor layer. A silicon implantation process is performed to the III-V compound semiconductor layer for forming a source doped region and a drain doped region in the III-V compound semiconductor layer under the silicon layer. A source electrode and a drain electrode are formed on the silicon layer. A source silicide layer is formed between the source electrode and the source doped region, and a drain silicide layer is formed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are partly formed on the passivation layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a channel layer, a gate element on the channel layer, and source/drain elements at least partly embedded in the channel layer. The source/drain elements are on opposite sides of the gate element. The source/drain elements include a metal element and a lower silicide element between the metal element and the channel layer. The lower silicide element has a hydrogen content less than 2 at %.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Abstract: A wireless device performs spatial reuse in a wireless local area network. When receiving a packet, the wireless device measures a received signal quality from a first portion of the packet, and determines a required signal quality for correctly decoding a payload of the packet based on information in a packet header. The wireless device compares the received signal quality with the required signal quality. If the received signal quality is lower than the required signal quality, the wireless device transmits a signal that overlaps in time and in frequency with a second portion of the packet. Alternatively, a wireless device may identify a Basic Service Set Identification (BSSID) of a received packet. If the BSSID indicates that the packet is an inter-BSS packet, the wireless device transmits a signal overlapping in time and in frequency with the packet before reception of a frame check sequence (FCS) in the packet.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.