Virtual Ground Non-volatile Memory Array
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
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This application is a continuation of U.S. application Ser. No. 14/935,201, which claims the benefit of U.S. Provisional Application No. 62/078,873, filed Nov. 12, 2014, and which are incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention relates to non-volatile memory arrays.
BACKGROUND OF THE INVENTIONSplit gate non-volatile flash memory cells are well known. For example, U.S. Pat. No. 6,747,310 discloses such memory cells having source and drain regions defining a channel region there between, a select gate over one portion of the channel regions, a floating gate over the other portion of the channel region, and an erase gate over the source region. The memory cells are formed in pairs that share a common source region and common erase gate, with each memory cell having its own channel region in the substrate extending between the source and drain regions (i.e. there are two separate channel regions for each pair of memory cells). The lines connecting all the control gates for memory cells in a given column run vertically. The same is true for the lines connecting the erase gates and the select gates, and the source lines. The bit lines connecting drain regions for each row of memory cells run horizontally.
Given the number of electrodes for each cell (source, drain, select gate, control gate and erase gate), and two separate channel regions for each pair of memory calls, configuring and forming the architecture and array layout with all the various lines connected to these electrodes can be overly complex and difficult to implement, especially as critical dimensions continue to shrink.
BRIEF SUMMARY OF THE INVENTIONThe aforementioned problems and needs are addressed by a memory device that includes a substrate of semiconductor material of a first conductivity type, spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction, where each of the active regions including a plurality of pairs of memory cells. Each of the memory cell pairs includes first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions, a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region, an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions, a first control gate disposed vertically over and insulated from the first floating gate, and a second control gate disposed vertically over and insulated from the second floating gate. The pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region. A plurality of first control gate lines have lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions. A plurality of second control gate lines have lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions. A plurality of bit lines have lengths extending in the second direction and each electrically connected to one of the first regions and one of the second regions in each of the active regions. A plurality of erase gate lines having lengths extending in the first direction and each electrically connected to the erase gates in one of the active regions.
A memory device can include a substrate of semiconductor material of a first conductivity type, spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction, where each of the active regions including a plurality of pairs of memory cells. Each of the memory cell pairs includes first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions, a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region, an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions, a first control gate disposed vertically over and insulated from the first floating gate, and a second control gate disposed vertically over and insulated from the second floating gate. The pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region. A plurality of first control gate lines have lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions. A plurality of second control gate lines have lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions. A plurality of erase gate lines have lengths extending in the second direction and each electrically connected to one of the erase gates in each of the active regions.
A memory device can include a substrate of semiconductor material of a first conductivity type, spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction, where each of the active regions including a plurality of pairs of memory cells. Each of the memory cell pairs includes first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, an word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, a first control gate disposed over and insulated from the first floating gate, a second control gate disposed over and insulated from the second floating gate, a first erase gate disposed over and insulated from the first region, and a second erase gate disposed over and insulated from the second region. The pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
The present invention is a memory cell design, architecture and array layout that utilizes a virtual ground memory cell configuration.
The present invention includes several memory cell array architectures and layouts of the various contacts and voltage lines to achieve the desired operation and performance of CELLS #1, #2 and #3.
Architecture #1In this embodiment, the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends from the first drain region DRA to the second drain region DRB in the same direction (horizontally to the right in
In this embodiment, the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends from the first drain region DRA to the second drain region DRB in the same direction (vertically down in
The components of memory device 50 according to any of the above six described architectures is illustrated in
It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the memory cell array of the present invention. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
Claims
1. A memory device comprising:
- a substrate of semiconductor material of a first conductivity type;
- spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction;
- each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes: first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions, a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region, an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions, a first control gate disposed vertically over and insulated from the first floating gate, and a second control gate disposed vertically over and insulated from the second floating gate;
- wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region;
- a plurality of first control gate lines having lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;
- a plurality of second control gate lines having lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions;
- a plurality of bit lines having lengths extending in the second direction and each electrically connected to one of the first regions and one of the second regions in each of the active regions;
- a plurality of erase gate lines having lengths extending in the first direction and each electrically connected to the erase gates in one of the active regions.
2. The memory device of claim 1, further comprising:
- control circuitry configured to, during a read operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and a zero voltage to the bit lines electrically connected to the memory cells that are not the selected memory cell.
3. The memory device of claim 1, further comprising:
- control circuitry configured to, during a program operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; and a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell.
4. The memory device of claim 3, wherein the control circuitry is configured further to apply:
- a negative voltage to the control gate lines electrically connected to the control gates of a memory cell pair adjacent to the memory cell pair containing the selected memory cell; and
- a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell and not adjacent to the pair of memory cells containing the selected memory cell.
5. The memory device of claim 1, further comprising:
- control circuitry configured to, during an erase operation for a selected one of the memory cells, apply: a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; and a negative voltage to the control gate line electrically connected to the control gate of the selected memory cell.
6. A memory device comprising:
- a substrate of semiconductor material of a first conductivity type;
- spaced apart isolation regions formed on the substrate which are substantially parallel to one another and have lengths that extend in a first direction, with an active region between each pair of adjacent isolation regions also having lengths extending in the first direction;
- each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes: first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending entirely between the first and second regions, a first floating gate disposed vertically over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed vertically over and insulated from a second portion of the channel region adjacent to the second region, an erase gate disposed vertically over and insulated from a third portion of the channel region between the first and second channel region portions, a first control gate disposed vertically over and insulated from the first floating gate, and a second control gate disposed vertically over and insulated from the second floating gate;
- wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends entirely from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region;
- a plurality of first control gate lines having lengths extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;
- a plurality of second control gate lines having lengths extending in the second direction and each electrically connected to one of the second control gates in each of the active regions; and
- a plurality of erase gate lines having lengths extending in the second direction and each electrically connected to one of the erase gates in each of the active regions.
7. The memory device of claim 6, further comprising:
- a plurality of bit lines each having a zig zag configuration that includes: first portions disposed vertically over and electrically connected to some of the first and second regions of a first of the active regions; second portions disposed vertically over and electrically connected to some of the first and second regions of a second of the active regions adjacent to the first of the active regions; and third portions each traversing the isolation region between the first and second active regions.
8. The memory device of claim 7, further comprising:
- control circuitry configured to, during a read operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell.
9. The memory device of claim 7, further comprising:
- control circuitry configured to, during a program operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell.
10. The memory device of claim 9, wherein the control circuitry is further configured to apply:
- a positive voltage to the bit line electrically connected to the pair of memory cells not containing the selected memory cell and sharing the bit line and control gate line electrically connected to the selected memory cell.
11. The memory device of claim 9, wherein the control circuitry is further configured to apply:
- a positive or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell and not sharing the bit line and control gate line electrically connected to the selected memory cell; and
- a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.
12. The memory device of claim 6, further comprising:
- a plurality of bit lines each electrically connected to one of the first regions and one of the second regions in each of the active regions, wherein each of the bit lines is diagonally oriented relative to the first direction.
13. The memory device of claim 6, further comprising:
- a plurality of bit lines each electrically connected to one of the first regions and one of the second regions in each of the active regions, wherein each of the bit lines includes: first segments each having a length extending along one of the active regions, and second segments each traversing across one of the isolation regions from one of the first segments to another of the first segments.
14. The memory device of claim 12, further comprising:
- control circuitry configured to, during a read operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell.
15. The memory device of claim 12, further comprising:
- control circuitry configured to, during a program operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell.
16. The memory device of claim 15, wherein the control circuitry is further configured to apply:
- a positive voltage to the bit line electrically connected to the pair of memory cells not containing the selected memory cell and sharing the bit line and control gate line electrically connected to the selected memory cell; and
- a positive or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell and not sharing the bit line and control gate line electrically connected to the selected memory cell;
17. The memory device of claim 15, wherein the control circuitry is further configured to apply:
- a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.
18. The memory device of claim 6, wherein each of the active regions further comprises:
- a first bit line having a length extending in the first direction and electrically connected to some of the first and second regions in the active region; and
- a second bit line having a length extending in the first direction and electrically connected to others of the first and second regions in the active region.
19. The memory device of claim 18, further comprising:
- control circuitry configured to, during a read operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a positive voltage to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell.
20. The memory device of claim 18, further comprising:
- control circuitry configured to, during a program operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell;
21. The memory device of claim 20, wherein the control circuitry is further configured to apply:
- a positive voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and
- a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.
22. The memory device of claim 6, wherein:
- for each one of the active regions: a first plurality of the first regions in the one active region are electrically connected to a first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction; a second plurality of the first regions in the one active region are electrically connected to a second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction; wherein the first plurality of the first regions alternate with the second plurality of the first regions;
- the memory device further comprising: a first plurality of bit lines each having a length extending along one of a first plurality of the active regions and electrically connected to the first plurality of the first regions therein; and a second plurality of bit lines each having a length extending along one of a second plurality of the active regions and electrically connected to the second plurality of the first regions therein; wherein the first plurality of the active regions alternate with the second plurality of the active regions.
23. The memory device of claim 22, wherein for each one of the active regions:
- the first plurality of the first regions in the one active region are electrically connected to the first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction by diffusion extending across one of the isolation regions; and
- the second plurality of the first regions in the one active region are electrically connected to the second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction by diffusion extending across another one of the isolation regions.
24. The memory device of claim 22, wherein for each one of the active regions:
- the first plurality of the first regions in the one active region are electrically connected to the first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction by metal connectors extending across one of the isolation regions; and
- the second plurality of the first regions in the one active region are electrically connected to the second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction by metal connectors extending across another one of the isolation regions.
25. The memory device of claim 22, further comprising:
- control circuitry configured to, during a read operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a zero voltage to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell.
26. The memory device of claim 22, further comprising:
- control circuitry configured to, during a program operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; and a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell.
27. The memory device of claim 26, wherein the control circuitry is further configured to apply:
- a positive voltage or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and
- a zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell.
28. A memory device, comprising:
- a substrate of semiconductor material of a first conductivity type;
- spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;
- each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes: first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region, a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region, an word line gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions, a first control gate disposed over and insulated from the first floating gate, a second control gate disposed over and insulated from the second floating gate, a first erase gate disposed over and insulated from the first region, and a second erase gate disposed over and insulated from the second region;
- wherein the pairs of memory cells are configured in an array such that for each of the pairs of memory cells, the channel region extends from the first region to the second region in the first direction, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
29. The memory device of claim 28, further comprising:
- a plurality of first control gate lines extending in a second direction orthogonal to the first direction and each electrically connected to one of the first control gates in each of the active regions;
- a plurality of second control gate lines extending in the second direction and each electrically connected to one of the second control gates in each of the active regions;
- a plurality of erase gate lines extending in the second direction and each electrically connected to one of the first and second erase gates in each of the active regions; and
- a plurality of word lines extending in the second direction and each electrically connected to one of the word line gates in each of the active regions.
30. The memory device of claim 29, wherein:
- for each one of the active regions: a first plurality of the erase gates in the one active region are electrically connected to a first plurality of the erase gates in another of the active regions adjacent to the one active region in the second direction; a second plurality of the erase gates in the one active region are electrically connected to a second plurality of the erase gates in another of the active regions adjacent to the one active region in a direction opposite to the second direction; wherein the first plurality of the erase gates alternate with the second plurality of the erase gates.
31. The memory device of claim 30, further comprising:
- a first plurality of electrical contacts each electrically connected between one of the first plurality of the erase gates and one of the erase gate lines; and
- a second plurality of electrical contacts each electrically connected between one of the second plurality of the erase gates and one of the erase gate lines.
32. The memory device of claim 29, wherein:
- for each one of the active regions: a first plurality of the first regions in the one active region are electrically connected to a first plurality of the first regions in another of the active regions adjacent to the one active region in the second direction; a second plurality of the first regions in the one active region are electrically connected to a second plurality of the first regions in another of the active regions adjacent to the one active region in a direction opposite to the second direction; wherein the first plurality of the first regions alternate with the second plurality of the first regions;
- the memory device further comprising: a first plurality of bit lines each extending parallel to one of a first plurality of the active regions and electrically connected to the first plurality of the first regions therein; and a second plurality of bit lines each extending parallel to one of a second plurality of the active regions and electrically connected to the second plurality of the first regions therein; wherein the first plurality of the active regions alternate with the second plurality of the active regions.
33. The memory device of claim 32, wherein each of the first and second pluralities of bits lines extends over one of the isolation regions.
34. The memory device of claim 33, further comprising:
- a plurality of metal bridges each extending in the first direction between a first contact that is electrically connected to one of the first and second regions, and a second contact that is electrically connected to one of the first and second plurality of bit lines.
35. The memory device of claim 32, further comprising:
- control circuitry configured to, during a read operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; a zero voltage to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the word line electrically connected to the word line gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a zero voltage to the control gate lines electrically connected to the control gates of the pairs of memory cells not containing the selected memory cell; and a zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and a zero voltage to the word lines electrically connected to the word line gates of the pairs of memory cells not containing the selected memory cell.
36. The memory device of claim 32, further comprising:
- control circuitry configured to, during a program operation for a selected one of the memory cells, apply: a positive voltage to the bit line electrically connected to the selected memory cell; an electrical current to the bit line electrically connected to the memory cell paired with the selected memory cell; a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the selected memory cell; a positive voltage to the control gate line electrically connected to the control gate of the memory cell paired with the selected memory cell; a positive voltage to the word line electrically connected to the word line gate of the selected memory cell; and a zero voltage to the word lines electrically connected to the word line gates of pairs of the memory cells not containing the selected memory cell.
37. The memory device of claim 36, wherein the control circuitry is further configured to apply:
- a positive voltage or zero voltage to the bit lines electrically connected to the pairs of memory cells not containing the selected memory cell; and
- a positive voltage or zero voltage to the control gate lines electrically connected to the control gates of pairs of the memory cells not containing the selected memory cell;
38. The memory device of claim 29, further comprising:
- control circuitry configured to, during an erase operation for a selected one of the memory cells, apply: a positive voltage to the erase gate line electrically connected to the erase gate of the selected memory cell; and a negative voltage to the control gate line electrically connected to the control gate of the selected memory cell.
Type: Application
Filed: Jan 31, 2019
Publication Date: May 30, 2019
Applicant:
Inventors: Hieu Van Tran (San Jose, CA), Hung Quoc Nguyen (Fremont, CA), Nhan Do (Saratoga, CA)
Application Number: 16/264,349