WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
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The present disclosure relates to a wiring structure and a manufacturing method, and to a wiring structure including at least two conductive structures attached or bonded together by an intermediate layer, and a method for manufacturing the same.
2. Description of the Related ArtAlong with the rapid development in electronics industry and the progress of semiconductor processing technologies, semiconductor chips are integrated with an increasing number of electronic components to achieve improved electrical performance and additional functions. Accordingly, the semiconductor chips are provided with more input/output (I/O) connections. To manufacture semiconductor packages including semiconductor chips with an increased number of I/O connections, circuit layers of semiconductor substrates used for carrying the semiconductor chips may correspondingly increase in size. Thus, a thickness and a warpage of a semiconductor substrate may correspondingly increase, and a yield of the semiconductor substrate may decrease.
SUMMARYIn some embodiments, a wiring structure includes: (a) an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer; (b) a lower conductive structure including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; (c) a lower encapsulant surrounding a lateral peripheral surface of the lower conductive structure; and (d) an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure.
In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a lower substrate including at least one lower conductive structure, wherein the lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) providing a plurality of upper strips, wherein each of the upper strips includes at least one upper conductive structure, and the upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (c) attaching the upper strips to the lower substrate side by side, wherein a position of the upper conductive structure of the upper strip corresponds to a position of the lower conductive structure of the lower substrate; (d) electrically connecting the upper conductive structure of the upper strip and the lower conductive structure of the lower substrate; and (e) conducting a singulation process to form a plurality of wiring structures.
In some embodiments, a method for manufacturing a wiring structure includes: (a) providing a plurality of lower conductive structures, wherein each of the lower conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; (b) forming a lower encapsulant to encapsulate a plurality of known good lower conductive structures to form a lower module; (c) providing a plurality of upper conductive structures, wherein each of the upper conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure; (d) attaching the upper conductive structures to the known good lower conductive structures of the lower module respectively; and electrically connecting the upper conductive structures and the known good lower conductive structures of the lower module; and (f) conducting a singulation process to form a plurality of wiring structures.
Aspects of some embodiments of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It is noted that various structures may not be drawn to scale, and dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
To meet the specification of increasing I/O counts, a number of dielectric layers of a substrate should increase. In some comparative embodiments, a manufacturing process of a core substrate may include the following stages. Firstly, a core with two copper foils disposed on two sides thereof is provided. Then, a plurality of dielectric layers and a plurality of circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one corresponding dielectric layer. Therefore, the core substrate may include a plurality of stacked dielectric layers and a plurality of circuit layers embedded in the dielectric layers on both sides of the core. Since a line width/line space (L/S) of the circuit layers of such core substrate may be greater than or equal to 10 micrometers (μm)/10 μm, the number of the dielectric layers of such core substrate is relatively large. Although the manufacturing cost of such core substrate is low, the manufacturing yield for the circuit layers and the dielectric layers of such core substrate is also low, and, thus, the yield of such core substrate is low. In addition, each dielectric layer is relatively thick, and, thus, such core substrate is relatively thick. In some comparative embodiments, if a package has 10000 I/O counts, such core substrate may include twelve layers of circuit layers and dielectric layers. The manufacturing yield for one layer (including one circuit layer and one dielectric layer) of such core substrate may be 90%. Thus, the yield of such core substrate may be (0.9)12=28.24%. In addition, warpage of the twelve layers of circuit layers and dielectric layers may be accumulated, and, thus, the top several layers may have severe warpage. As a result, the yield of such core substrate may be further reduced.
To address the above concerns, in some comparative embodiments, a coreless substrate is provided. The coreless substrate may include a plurality of dielectric layers and a plurality of fan-out circuit layers. In some embodiments, a manufacturing process of a coreless substrate may include the following stages. Firstly, a carrier is provided. Then, a plurality of dielectric layers and a plurality of fan-out circuit layers are formed or stacked on a surface of the carrier. One fan-out circuit layer may be embedded in one corresponding dielectric layer. Then, the carrier is removed. Therefore, the coreless substrate may include a plurality of stacked dielectric layers and a plurality of fan-out circuit layers embedded in the dielectric layers. Since a line width/line space (L/S) of the fan-out circuit layers of such coreless substrate may be less than or equal to 2 μm/2 μm, the number of the dielectric layers of such coreless substrate can be reduced. Further, the manufacturing yield for the fan-out circuit layers and the dielectric layers of such coreless substrate is high. For example, the manufacturing yield for one layer (including one fan-out circuit layer and one dielectric layer) of such coreless substrate may be 99%. However, the manufacturing cost of such coreless substrate is relatively high.
At least some embodiments of the present disclosure provide for a wiring structure which has an advantageous compromise of yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure through an intermediate layer. At least some embodiments of the present disclosure further provide for techniques for manufacturing the wiring structure.
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The upper conductive structure 2a has a top surface 21 and a bottom surface 22 opposite to the top surface 21, and defines at least one through hole 23, each of which is a single, continuous through hole. The upper conductive structure 2a includes a plurality of dielectric layers (e.g., the two first dielectric layers 20 and the second dielectric layer 26), a plurality of circuit layers (e.g., the three first circuit layers 24 and the second circuit layer 28) and at least one inner via 25. The dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) are stacked on one another. For example, the second dielectric layer 26 is disposed on the first dielectric layers 20, and, thus, the second dielectric layer 26 is the topmost dielectric layer. In some embodiments, a material of the dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) is transparent, and can be seen through by human eyes or machine. That is, a mark disposed adjacent to the bottom surface 22 of the upper conductive structure 2a can be recognized or detected from the top surface 21 of the upper conductive structure 2a by human eyes or machine. In some embodiments, a transparent material of the dielectric layers has a light transmission for a wavelength in the visible range (or other pertinent wavelength for detection of a mark) of at least about 60%, at least about 70%, or at least about 80%.
In addition, each of the first dielectric layers 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201, and defines a through hole 203 having an inner surface 2031. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261, and defines a through hole 263 having an inner surface 2631. The bottom surface 262 of the second dielectric layer 26 is disposed on and contacts the top surface 201 of the adjacent first dielectric layer 20. Thus, the top surface 21 of the upper conductive structure 2a is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2a is the bottom surface 202 of the bottommost first dielectric layer 20.
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The first circuit layers 24 may be fan-out circuit layers or redistribution layers (RDLs), and an L/S of the first circuit layers 24 may be less than or equal to about 2 μm/about 2 μm, or less than or equal to about 1.8 μm/about 1.8 μm. Each of the first circuit layers 24 has a top surface 241 and a bottom surface 242 opposite to the top surface 241. In some embodiments, the first circuit layer 24 is embedded in the corresponding first dielectric layer 20, and the top surface 241 of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, each first circuit layer 24 may include a seed layer 243 and a conductive metallic material 244 disposed on the seed layer 243. As shown in
The upper conductive structure 2a includes a plurality of inner vias 25. Some of the inner vias 25 are disposed between two adjacent first circuit layers 24 for electrically connecting the two first circuit layers 24. Some of the inner vias 25 are disposed between the first circuit layer 24 and the second circuit layer 28 for electrically connecting the first circuit layer 24 and the second circuit layer 28. In some embodiments, each inner via 25 may include a seed layer 251 and a conductive metallic material 252 disposed on the seed layer 251. In some embodiments, each inner via 25 and the corresponding first circuit layer 24 may be formed integrally as a monolithic or one-piece structure. Each inner via 25 tapers upwardly along a direction from the bottom surface 22 towards the top surface 21 of the upper conductive structure 2. That is, a size (e.g., a width) of a top portion of the inner via 25 is less than a size (e.g., a width) of a bottom portion of the inner via 25 that is closer towards the bottom surface 22. In some embodiments, a maximum width of the inner via 25 (e.g., at the bottom portion) may be less than or equal to about 25 μm, such as about 25 μm, about 20 μm about 15 μm or about 10 μm.
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The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of through holes 373 extending through the core portion 37. An interconnection via 39 is disposed or formed in each through hole 373 for vertical connection. In some embodiments, each interconnection via 39 includes a base metallic layer 391 and an insulation material 392. The base metallic layer 391 is disposed or formed on a side wall of the through hole 373, and defines a central through hole. The insulation material 392 fills the central through hole defined by the base metallic layer 391. In some embodiments, the interconnection via 39 may omit an insulation material, and may include a bulk metallic material that fills the through hole 373.
The first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. Thus, the bottom surface 302 of the first upper dielectric layer 30 contacts the top surface 371 of the core portion 37. The second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30, and has a top surface 361 and a bottom surface 362 opposite to the top surface 361. Thus, the bottom surface 362 of the second upper dielectric layer 36 contacts the top surface 301 of the first upper dielectric layer 30, and the second upper dielectric layer 36 is the topmost dielectric layer. In addition, the first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. Thus, the top surface 301a of the first lower dielectric layer 30a contacts the bottom surface 372 of the core portion 37. The second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a, and has a top surface 361a and a bottom surface 362a opposite to the top surface 361a. Thus, the top surface 361a of the second lower dielectric layer 36a contacts the bottom surface 302a of the first lower dielectric layer 30a, and the second lower dielectric layer 36a is the bottommost dielectric layer. As shown in
A thickness of each of the dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) of the upper conductive structure 2a is less than or equal to about 40%, less than or equal to about 35%, less than or equal to about 30% of a thickness of each of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a and the second lower dielectric layer 36a) of the lower conductive structure 3a. For example, a thickness of each of the dielectric layers (e.g., the first dielectric layers 20 and the second dielectric layer 26) of the upper conductive structure 2a may be less than or equal to about 7 μm, and a thickness of each of the dielectric layers (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a and the second lower dielectric layer 36a) of the lower conductive structure 3a may be about 40 μm.
An L/S of the first upper circuit layer 34 may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the first upper circuit layer 34 may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upper conductive structure 2a. The first upper circuit layer 34 has a top surface 341 and a bottom surface 342 opposite to the top surface 341. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37, and covered by the first upper dielectric layer 30. The bottom surface 342 of the first upper circuit layer 34 contacts the top surface 371 of the core portion 37. In some embodiments, the first upper circuit layer 34 may include a first metallic layer 343, a second metallic layer 344 and a third metallic layer 345. The first metallic layer 343 is disposed on the top surface 371 of the core portion 37, and may be formed from a copper foil (e.g., may constitute a portion of the copper foil). The second metallic layer 344 is disposed on the first metallic layer 343, and may be a plated copper layer. The third metallic layer 345 is disposed on the second metallic layer 344, and may be another plated copper layer. In some embodiments, the third metallic layer 345 may be omitted.
An L/S of the second upper circuit layer 38 may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the second upper circuit layer 38 may be substantially equal to the L/S of the first upper circuit layer 34, and may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upper conductive structure 2a. The second upper circuit layer 38 has a top surface 381 and a bottom surface 382 opposite to the top surface 381. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30, and covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 contacts the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through the upper interconnection vias 35. That is, the upper interconnection vias 35 are disposed between the second upper circuit layer 38 and the first upper circuit layer 34 for electrically connecting the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnection vias 35 are formed integrally as a monolithic or one-piece structure. Each upper interconnection via 35 tapers downwardly along a direction from the top surface 31 towards the bottom surface 32 of the lower conductive structure 3a.
In addition, in some embodiments, the second upper circuit layer 38′ is disposed on and protrudes from the top surface 361 of the second upper dielectric layer 36. In some embodiments, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38′ through the upper interconnection vias 35. That is, the upper interconnection vias 35 are disposed between the second upper circuit layers 38, 38′ for electrically connecting the second upper circuit layers 38, 38′. In some embodiments, the second upper circuit layer 38′ and the upper interconnection vias 35 are formed integrally as a monolithic or one-piece structure.
An L/S of the first lower circuit layer 34a may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the first lower circuit layer 34a may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upper conductive structure 2a. The first lower circuit layer 34a has a top surface 341a and a bottom surface 342a opposite to the top surface 341a. In some embodiments, the first lower circuit layer 34a is formed or disposed on the bottom surface 372 of the core portion 37, and covered by the first lower dielectric layer 30a. The top surface 341a of the first lower circuit layer 34a contacts the bottom surface 372 of the core portion 37. In some embodiments, the first lower circuit layer 34a may include a first metallic layer 343a, a second metallic layer 344a and a third metallic layer 345a. The first metallic layer 343a is disposed on the bottom surface 372 of the core portion 37, and may be formed from a copper foil. The second metallic layer 344a is disposed on the first metallic layer 343a, and may be a plated copper layer. The third metallic layer 345a is disposed on the second metallic layer 344a, and may be another plated copper layer. In some embodiments, the third metallic layer 345a may be omitted.
An L/S of the second lower circuit layer 38a may be greater than or equal to about 10 μm/about 10 μm. Thus, the L/S of the second lower circuit layer 38a may be substantially equal to the L/S of the first upper circuit layer 34, and may be greater than or equal to about five times the L/S of the first circuit layers 24 of the upper conductive structure 2a. The second lower circuit layer 38a has a top surface 381a and a bottom surface 382a opposite to the top surface 381a. In some embodiments, the second lower circuit layer 38a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a, and covered by the second lower dielectric layer 36a. The top surface 381a of the second lower circuit layer 38a contacts the bottom surface 302a of the first lower dielectric layer 30a. In some embodiments, the second lower circuit layer 38a is electrically connected to the first lower circuit layer 34a through the lower interconnection vias 35a. That is, the lower interconnection vias 35a are disposed between the second lower circuit layer 38a and the first lower circuit layer 34a for electrically connecting the second lower circuit layer 38a and the first lower circuit layer 34a. In some embodiments, the second lower circuit layer 38a and the lower interconnection vias 35a are formed integrally as a monolithic or one-piece structure. The lower interconnection vias 35a tapers upwardly along a direction from the bottom surface 32 towards the top surface 31 of the lower conductive structure 3a.
In addition, in some embodiments, the second lower circuit layer 38a′ is disposed on and protrudes from the bottom surface 362a of the second lower dielectric layer 36a. In some embodiments, the second lower circuit layer 38a′ is electrically connected to the second lower circuit layer 38a through the lower interconnection vias 35a. That is, the lower interconnection vias 35a are disposed between the second lower circuit layers 38a, 38a′ for electrically connecting the second lower circuit layers 38a, 38a′. In some embodiments, the second lower circuit layer 38a′ and the lower interconnection vias 35a are formed integrally as a monolithic or one-piece structure.
In some embodiments, each interconnection via 39 electrically connects the first upper circuit layer 34 and the first lower circuit layer 34a. The base metallic layer 391 of the interconnection via 39, the second metallic layer 344 of the first upper circuit layer 34 and the second metallic layer 344a the first lower circuit layer 34a may be formed integrally and concurrently as a monolithic or one-piece structure.
The intermediate layer 12 is interposed or disposed between the upper strips 2 and the lower substrate 3 to bond the upper strips 2 and the lower substrate 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2a and the top surface 31 of the lower conductive structure 3a. In some embodiments, the intermediate layer 12 may be an adhesion layer that is cured from an adhesive material (e.g., includes a cured adhesive material such as an adhesive polymeric material). The intermediate layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121, and defines at least one through hole 123 having an inner surface 1231. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2a (that is, the bottom surface 22 of the upper conductive structure 2a is attached to the top surface 121 of the intermediate layer 12), and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3a. Thus, the bottommost first circuit layer 24 of the upper conductive structure 2a and the topmost circuit layer 38′ (e.g., the second upper circuit layer 38′) of the lower conductive structure 3a are embedded in the intermediate layer 12. In some embodiments, a bonding force between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2a is greater than a bonding force between a dielectric layer (e.g., the bottommost first dielectric layers 20) of the upper conductive structure 2a and the intermediate layer 12. A surface roughness of a boundary between two adjacent dielectric layers (e.g., two adjacent first dielectric layers 20) of the upper conductive structure 2a is greater than a surface roughness of a boundary between a dielectric layer (e.g., the bottommost first dielectric layers 20) of the upper conductive structure 2a and the intermediate layer 12, such as about 1.1 times or greater, about 1.3 times or greater, or about 1.5 times or greater in terms of root mean squared surface roughness.
In some embodiments, a material of the intermediate layer 12 is transparent, and can be seen through by human eyes or machine. That is, a mark disposed adjacent to the top surface 31 of the lower conductive structure 3a can be recognized or detected from the top surface 21 of the upper conductive structure 2a by human eyes or machine. In addition, a material of the intermediate layer 12 may include an insulating film, such as Ajinomoto build-up film (ABF).
The through hole 123 extends through the intermediate layer 12. In some embodiments, the through hole 123 of the intermediate layer 12 may extend through the bottommost first circuit layer 24 of the upper conductive structure 2a and terminate at or on a topmost circuit layer (e.g., the second upper circuit layer 38′) of the lower conductive structure 3a. That is, the through hole 123 of the intermediate layer 12 does not extend through the topmost circuit layer (e.g., the second upper circuit layer 38′) of the lower conductive structure 3a. The through hole 123 of the intermediate layer 12 may expose a portion of the topmost circuit layer (e.g., the top surface of the second upper circuit layer 38′) of the lower conductive structure 3a.
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The upper through via 14 is formed or disposed in the corresponding single through hole 23, and is formed of a metal, a metal alloy, or other conductive material. Thus, the upper through via 14 extends through at least a portion of the upper conductive structure 2a and the intermediate layer 12, and is electrically connected to the topmost circuit layer (e.g., the top surface of the second upper circuit layer 38′) of the lower conductive structure 3a. As shown in
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In addition, the warpage of the upper strip 2 (e.g., the upper conductive structure 2a) and the warpage of the lower substrate 3 (e.g., the lower conductive structure 3a) are separated and will not influence each other. In some embodiments, a warpage shape of the upper strip 2 (e.g., the upper conductive structure 2a) may be different from a warpage shape of the lower substrate 3 (e.g., the lower conductive structure 3a). For example, the warpage shape of the upper strip 2 (e.g., the upper conductive structure 2a) may be a convex shape, and the warpage shape of the lower substrate 3 (e.g., the lower conductive structure 3a) may be a concave shape. In some embodiments, the warpage shape of the upper strip 2 (e.g., the upper conductive structure 2a) may be the same as the warpage shape of the lower substrate 3 (e.g., the lower conductive structure 3a); however, the warpage of the lower substrate 3 (e.g., the lower conductive structure 3a) will not be accumulated onto the warpage of the upper strip 2 (e.g., the upper conductive structure 2a). Thus, the yield of the wiring structure 1 may be further improved.
In addition, during a manufacturing process, the lower substrate 3 (e.g., the lower conductive structure 3a) and the upper strip 2 (e.g., the upper conductive structure 2a) may be tested individually before being bonded together. Therefore, known good lower substrate 3 (e.g., the lower conductive structure 3a) and known good upper strip 2 (e.g., the upper conductive structure 2a) may be selectively bonded together. Bad (or unqualified) lower substrate 3 (e.g., the lower conductive structure 3a) and bad (or unqualified) upper strip 2 (e.g., the upper conductive structure 2a) may be discarded. As a result, the yield of the wiring structure 1 may be further improved.
In addition, during a manufacturing process, the relative positions of the upper strips 2 are separated and will not influence each other. In some embodiments, if one or some of the upper strips 2 may be shifted with respect to a predetermined position of the lower substrate 3, the other upper strips 2 still can be disposed on a predetermined position of the lower substrate 3. In addition, the design of the upper strips 2 can increase effective area of the lower substrate 3. That is, the lower substrate 3 can carry more upper strips 2 (or upper conductive structures 2a) as compared with a panel type of upper conductive structure.
Each through via 16 is formed or disposed in the corresponding through hole 17, and is formed of a metal, a metal alloy, or other conductive material. Thus, the through via 16 extends through the upper conductive structure 2a, the intermediate layer 12 and the lower conductive structure 3a. As shown in
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In addition, the relative positions of the upper strips 2 are separated and will not influence each other. In some embodiments, if one or some of the upper strips 2 may be shifted with respect to a predetermined position of the lower substrate 3, the other upper strips 2 still can be disposed on a predetermined position of the lower substrate 3.
Then, the adhesive layer 12 is cured to form an intermediate layer 12.
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In some embodiments, a singulation process is conducted to the lower conductive structure 3 and the intermediate layer 12 along the cutting lines 87 to obtain a plurality of wiring structure 1a of
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The following stages of the illustrated process are the same as, or similar to, the stages illustrated in
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Then, a singulation process is conducted to singulate the lower module 86 along the cutting lines 87 to form a plurality of wiring structures 1c of
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Then, a singulation process is conducted to singulate the lower module 86, the intermediate layer 12 and the upper module 90 along the cutting lines to form a plurality of wiring structures 1e of
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to ±10% of the second numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.
Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be deemed to be substantially flat if a displacement between a highest point and a lowest point of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.
Claims
1. A wiring structure, comprising:
- an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer;
- a lower conductive structure including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer;
- a lower encapsulant surrounding a lateral peripheral surface of the lower conductive structure; and
- an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure,
- wherein a lateral peripheral surface of the intermediate layer is substantially coplanar with a lateral peripheral surface of the lower encapsulant.
2. The wiring structure of claim 1, wherein a lateral peripheral surface of the upper conductive structure is inwardly recessed from the lateral peripheral surface of the lower encapsulant.
3. The wiring structure of claim 1, wherein a lateral peripheral surface of the upper conductive structure is substantially coplanar with a lateral peripheral surface of the lower conductive structure.
4. The wiring structure of claim 1, wherein a lateral peripheral surface of the upper conductive structure is inwardly recessed from a lateral peripheral surface of the lower conductive structure.
5. The wiring structure of claim 1, wherein a portion of the intermediate layer covers a top surface of the lower encapsulant.
6. The wiring structure of claim 1, further comprising an upper encapsulant surrounding a lateral peripheral surface of the upper conductive structure.
7. The wiring structure of claim 6, wherein a lateral peripheral surface of the upper encapsulant is substantially coplanar with the lateral peripheral surface of the lower encapsulant.
8. The wiring structure of claim 6, wherein the lateral peripheral surface of the upper conductive structure is substantially coplanar with a lateral peripheral surface of the lower conductive structure.
9. The wiring structure of claim 6, wherein the lateral peripheral surface of the upper conductive structure is inwardly recessed from a lateral peripheral surface of the lower conductive structure.
10. The wiring structure of claim 1, wherein a line space of the lower circuit layer of the lower conductive structure is greater than a line space of the upper circuit layer of the upper conductive structure.
11. A method for manufacturing a wiring structure, comprising:
- (a) providing a lower substrate including at least one lower conductive structure, wherein the lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
- (b) providing a plurality of upper strips, wherein each of the upper strips includes at least one upper conductive structure, and the upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
- (c) attaching the upper strips to the lower substrate side by side, wherein a position of the upper conductive structure of the upper strip corresponds to a position of the lower conductive structure of the lower substrate;
- (d) electrically connecting the upper conductive structure of the upper strip and the lower conductive structure of the lower substrate; and
- (e) conducting a singulation process to form a plurality of wiring structures.
12. The method of claim 11, wherein (b) comprises:
- (b1) forming a conductive structure on a carrier; and
- (b2) cutting the conductive structure and the carrier to form the upper strips with a plurality of carrier strips;
- wherein in (c), the upper strips and the carrier strips are attached to the lower substrate, wherein the upper strips face the lower substrate;
- wherein after (c), the method further comprises:
- (c1) removing the carrier strips.
13. The method of claim 11, wherein after (a), the method further comprises:
- (a1) testing an electrical property of the lower conductive structure of the lower substrate; and
- wherein after (b), the method further comprises:
- (b1) testing an electrical property of the upper conductive structure of the upper strip.
14. The method of claim 11, wherein in (c), the upper strips are attached to the lower substrate through an adhesive layer.
15. The method of claim 11, wherein (d) includes:
- (d1) forming at least one through hole to extend through the upper conductive structure of the upper strip by drilling; and
- (d2) forming at least one upper through via in the through hole.
16. A method for manufacturing a wiring structure, comprising:
- (a) providing a plurality of lower conductive structures, wherein each of the lower conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
- (b) forming a lower encapsulant to encapsulate a plurality of known good lower conductive structures to form a lower module;
- (c) providing a plurality of upper conductive structures, wherein each of the upper conductive structures includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer of the upper conductive structure;
- (d) attaching the upper conductive structures to the known good lower conductive structures of the lower module respectively;
- (e) electrically connecting the upper conductive structures and the known good lower conductive structures of the lower module; and
- (f) conducting a singulation process to form a plurality of wiring structures.
17. The method of claim 16, wherein (c) comprises:
- (c1) forming a conductive structure on a carrier; and
- (c2) cutting the conductive structure and the carrier to form the plurality of upper conductive structures;
- wherein in (d), the upper conductive structures and the carrier are attached to the lower module, wherein the upper conductive structures face the lower module;
- wherein after (d), the method further comprises:
- (d1) removing the carrier.
18. The method of claim 16, wherein after (c), the method further comprises:
- (c1) forming an upper encapsulant to encapsulate a plurality of known good upper conductive structures to form an upper module.
19. The method of claim 18, wherein (d) comprises:
- (d1) attaching the upper module to the lower module.
20. The method of claim 16, wherein in (d), the upper conductive structures are attached to the known good lower conductive structures of the lower module through an adhesive layer.
21. A wiring structure, comprising:
- a high-density conductive structure including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
- a low-density conductive structure bonded to and electrically connected to the high-density conductive structure, and including at least one dielectric layer and at least one circuit layer in contact with the dielectric layer;
- a lower encapsulant surrounding a lateral peripheral surface of the low-density conductive structure; and
- an intermediate layer disposed between the high-density conductive structure and the low-density conductive structure and bonding the high-density conductive structure and the low-density conductive structure together, wherein a lateral peripheral surface of the intermediate layer is substantially coplanar with a lateral peripheral surface of the lower encapsulant.
22. The wiring structure of claim 21, wherein the low-density conductive structure further includes a core portion, the at least one dielectric layer and the at least one circuit layer of the low-density conductive structure are disposed adjacent to a surface of the core portion.
23. The wiring structure of claim 21, wherein a line space of the circuit layer of the low-density conductive structure is greater than a line space of the circuit layer of the high-density conductive structure.
24. The wiring structure of claim 21, further comprising at least one upper through via extending through at least a portion of the high-density conductive structure, and electrically connected to the circuit layer of the low-density conductive structure.
25. A wiring structure, comprising:
- an upper conductive structure including at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer;
- a lower conductive structure electrically connected to the upper conductive structure, and including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer;
- an intermediate layer disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together; and
- a lower encapsulant covering a lateral peripheral surface of the lower conductive structure and being in contact with a portion of the intermediate layer,
- wherein a lateral peripheral surface of the intermediate layer is substantially coplanar with a lateral peripheral surface of the lower encapsulant.
26. The wiring structure of claim 25, wherein a lateral peripheral surface of the upper conductive structure is inwardly recessed from the lateral peripheral surface of the lower encapsulant.
27. The wiring structure of claim 25, further comprising an upper encapsulant surrounding a lateral peripheral surface of the upper conductive structure.
28. The wiring structure of claim 25, wherein the lower conductive structure further includes a core portion, the at least one lower dielectric layer and the at least one lower circuit layer of the lower conductive structure are disposed adjacent to a surface of the core portion.
29. The wiring structure of claim 25, wherein a line space of the lower circuit layer of the lower conductive structure is greater than a line space of the upper circuit layer of the upper conductive structure.
30. The wiring structure of claim 25, further comprising at least one upper through via extending through at least a portion of the upper conductive structure and the intermediate layer, and electrically connected to the lower circuit layer of the lower conductive structure.
Type: Application
Filed: May 13, 2019
Publication Date: Nov 19, 2020
Applicant: Advanced Semiconductor Engineering, Inc. (Kaohsiung)
Inventor: Wen Hung HUANG (Kaohsiung)
Application Number: 16/410,872