Abstract: A device includes: a substrate having a semiconductor fin; a stack of semiconductor channels on the substrate and positioned over the fin; a gate structure wrapping around the semiconductor channels; a source/drain abutting the semiconductor channels; an inner spacer positioned between the stack of semiconductor channels and the fin; an undoped semiconductor layer vertically adjacent the source/drain and laterally adjacent the fin; and an isolation structure that laterally surrounds the undoped semiconductor layer, the isolation structure being between the source/drain and the inner spacer.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a redistribution layer (RDL) substrate over an active side of a semiconductor die. The RDL substrate includes a plurality of under-bump metallization (UBM) structures. A die pad of a leadframe is affixed on a backside of the semiconductor die. The leadframe includes a plurality of leads having a first portion of each lead connected to the die pad and a second portion of each lead extending vertically along sidewalls of the semiconductor die toward a plane of the RDL substrate. An encapsulant encapsulates the semiconductor die and the leadframe, a lead tip portion of each lead is exposed through the encapsulant.

Abstract: A heat dissipation assembly is disclosed and includes a fan, a vapor chamber and a heat dissipation fin set. The fan includes a fan frame, an impeller and a fan cover. The impeller is disposed on the fan frame and accommodated in an accommodation space. The impeller includes plural metal blades and a hub, and the plural metal blades are radially arranged on the periphery of the hub to form a dense-metal-blade impeller. The fan cover is assembled with the fan frame to form an outlet, and the fan cover includes an inlet. The vapor chamber includes an upper plate and a lower plate assembled with each other. The upper plate or the lower plate is connected to the fan cover, and the vapor chamber and the fan cover are coplanar. The heat dissipation fin set is connected to the lower plate and spatially corresponding to the outlet.

Abstract: A semiconductor structure includes a ferroelectric layer and a semiconductor layer. Thee ferroelectric layer has a first surface and a second surface opposite to the first surface. The semiconductor layer is formed on one of the first surface and the second surface.

Abstract: A teleconferencing system includes a system housing, a speaker enclosure configured within the system housing, a speaker mounted to the speaker enclosure, and one or more damping elements coupling the speaker enclosure to the system housing. The one or more damping elements suspend the speaker enclosure within the system housing such that the speaker enclosure is isolated and separated from the system. In some cases, the one or more damping elements provide the only structural coupling between the speaker enclosure and the system housing. The damping elements are laterally attached directly to the speaker housing with a resilient element.

Abstract: A method of predicting an effect of a chemotherapy treatment on a cancer patient's cognitive status using the patient's predicted age difference (PAD) comprises acquiring at least one medical brain image of a patient's brain before a chemotherapy treatment; processing the medical brain image to obtain at least one feature of the image; generating a PAD value of the individual based on the at least one feature of the image; and predicting an effect of the chemotherapy treatment on a cancer patient's cognitive status using the PAD value.

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

Abstract: A semiconductor device and a method for operating the semiconductor device are provided. The semiconductor device includes a calibration device, an adjustment device and a driver. The calibration device is configured to continuously generate a first signal including a first number of bits. The adjustment device is configured to continuously receive the first signal and generate a second signal according to the last two bits of the first signal The second signal includes a second number of bits, and the second number is different from the first number. The driver is electrically coupled to the adjustment device, wherein an output resistance of the driver is controllable in response to the second signal.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over an active side of a semiconductor die. A die pad of the semiconductor die is connected to an interconnect segment of the RDL by way of a bond wire. An encapsulating layer is formed over the active side of the semiconductor die such that exposed portions of the die pad and the bond wire are embedded in the encapsulating layer.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

Abstract: A leadless semiconductor package includes an integrated circuit (IC) die having one or more contacts at an active surface facing a mounting surface of the leadless semiconductor package. The leadless semiconductor package further includes a plurality of dual-sided stud structures providing electrical connectivity between the IC die and the mounting surface, each dual-sided stud structure having at least one first conductive pillar structure extending from a corresponding contact at the active surface to a redistribution layer and having at least one second conductive pillar structure extending from a redistribution layer to an edge of the mounting surface, each first conductive pillar structure having a first dimension in a direction parallel to the mounting surface that is less than a corresponding second dimension of each second conductive pillar structure. Solder wettable flanks may be formed at the external sidewall edges of the second conductive pillar structures to facilitate soldering or inspection.

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

Abstract: A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.