Patents by Inventor Wen-Hung Huang

Wen-Hung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210134864
    Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Publication number: 20210125946
    Abstract: An electronic device package includes a redistribution layer and a conductive substrate. The RDL includes a first surface. The conductive substrate is disposed on the first surface and electrically connected to the RDL. A circuit density of the RDL is higher than a circuit density of the conductive substrate, and an edge of the RDL laterally protrudes out from a respective edge of the conductive substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210124144
    Abstract: An optical element driving mechanism includes a fixed portion, a movable portion, a driving assembly, and a circuit assembly. The movable portion is connected to the optical element and is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The circuit assembly is connected to the driving assembly. The driving assembly is electrically connected to an external circuit via the circuit assembly.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 29, 2021
    Inventors: Yi-Ho CHEN, Chen-Hsin HUANG, Chao-Chang HU, Chen-Chi KUO, Ying-Jen WANG, Ya-Hsiu WU, Sin-Jhong SONG, Che-Hsiang CHIU, Kuen-Wang TSAI, Mao-Kuo HSU, Tun-Ping HSUEH, I-Hung CHEN, Chun-Chia LIAO, Wei-Zhong LUO, Wen-Chang LIN
  • Publication number: 20210125905
    Abstract: A wiring structure includes a semiconductor assembly, a conductive structure, an adhesion layer and at least one through via. The semiconductor assembly includes a reconstitution module and a redistribution structure. The reconstitution module includes a plurality of semiconductor elements and an encapsulant. The semiconductor elements are disposed side by side. The encapsulant bonds the semiconductor elements together. The redistribution structure is in direct contact with the reconstitution module. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer bonds the semiconductor assembly and the conductive structure together. The through via electrically connects the conductive structure and the redistribution structure of the semiconductor assembly.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Patent number: 10978417
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 13, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Publication number: 20210098357
    Abstract: A device structure includes a stacked structure, a dielectric material, and an electrode via. The stacked structure includes a first metal oxide layer, a second metal oxide layer and a metal layer. The second metal oxide layer is opposite to the first metal oxide layer. The metal layer is interposed between the first metal oxide layer and the second metal oxide layer. The dielectric material extends through the first metal oxide layer. The electrode via extends through the dielectric material and electrically connected to the metal layer.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210066264
    Abstract: A semiconductor device package includes a first passive component having a first surface and a second passive component having a second surface facing the first surface of the first passive component. The first surface has a recessing portion and the second surface includes a protruding portion within the recessing portion of the first surface of the first passive component. A contour of the protruding portion and a contour of the recessing portion are substantially matched. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Wen Chieh YANG
  • Publication number: 20210066156
    Abstract: A stacked structure includes a lower structure, an upper structure and a buffer layer. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The buffer layer is interposed between the lower structure and the upper structure. A coefficient of thermal expansion (CTE) of the buffer layer is between a coefficient of thermal expansion (CTE) of the lower structure and a coefficient of thermal expansion (CTE) of the upper structure.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210068267
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG
  • Publication number: 20210066218
    Abstract: A stacked structure includes a lower structure and an upper structure. The lower structure includes at least one lower dielectric layer and at least one lower metal layer in contact with the lower dielectric layer. The upper structure includes at least one upper dielectric layer and at least one upper metal layer in contact with the upper dielectric layer. The upper dielectric layer includes a first upper dielectric layer attached to the lower structure. The first upper dielectric layer includes a first portion and a second portion. A difference between a thickness of the first portion and a thickness of the second portion is greater than a gap between a highest point of a top surface of the first upper dielectric layer and lowest point of the top surface of the first upper dielectric layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Patent number: 10939561
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Publication number: 20210035896
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. Each of the sub-layers is formed from a polymeric material. A boundary is formed between two adjacent sub-layers.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210035949
    Abstract: A package structure includes a plurality of lower elements, a reinforcement structure and an encapsulant. The lower elements are disposed side by side. The reinforcement structure surrounds the lower elements. The encapsulant covers the lower elements and the reinforcement structure. The electrical connectors of the lower elements are exposed from the encapsulant.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20210035897
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, a plurality of metallic structures and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The metallic structures are disposed between the upper conductive structure and the lower conductive structure, and electrically connecting the upper conductive structure and the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure, and covers the metallic structures.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Patent number: 10903169
    Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Publication number: 20210013163
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
  • Patent number: 10892213
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an adhesion layer and at least one outer via. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The adhesion layer is interposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The outer via extends through at least a portion of the upper conductive structure and the adhesion layer, and electrically connected to the circuit layer of the lower conductive structure.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Li-Yu Hsieh, Yan Wen Chung
  • Publication number: 20200411402
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Publication number: 20200388600
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Application
    Filed: June 6, 2019
    Publication date: December 10, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
  • Patent number: 10861780
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang