COAXIAL VIA ARRANGEMENT IN PROBE CARD FOR AUTOMATED TEST EQUIPMENT
A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
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Electronic components, such as semiconductor devices, circuits, and printed circuit board (PCB) assemblies, are frequently tested, during and after their manufacture, using a test system such as an automated test equipment (ATE). To perform these tests, an ATE may include instruments that generate or measure test signals such that a range of operating conditions can be tested on a particular device-under-test (DUT). An instrument, for example, may generate a pattern of digital or analog signals that are applied to a semiconductor device, and may measure digital or analog signals from the semiconductor device as a response.
In some instances, semiconductor devices are tested at the wafer level. Testing at the wafer-level has several benefits including testing and validating a device as a known good die before it is diced as a semiconductor die and packaged. A wafer may contain many devices, and permit testing of a large number of devices in close proximity to each other without having to reload another wafer, which can decrease testing time and increase manufacturing throughput.
Each device under test contains exposed connection structures such as pads or bumps, which may serve as test points at which test signals may be applied to or measured to a DUT on a wafer. An ATE interfaces with the device using a probe card assembly that contains an array of multiple probe pins. Each probe pin has a tiny probe needle on a free end that is used to make electrical contact to a test point of the DUT, with the opposite end of the probe pin electrically connected to pads on a printed circuit board, which may be part of the tester or may be part of the probe card assembly that, in turn, is electrically connected to the tester. Sometimes a probe card assembly includes more than one circuit boards stacked vertically over each other to form a probe card. Mechanical supports within the probe card assembly hold the probe pins and press the pins against the printed circuit board in the probe card, enabling contact to be made between the board and the pins. In order to make electrical contact to the wafer, a wafer prober presses the wafer against the probe needles so that the needle tips make physical and electrical contact with test points on the device. Once the probe needles have made contact with both the test points on the wafer and the pads that are electrically coupled to the tester, the testing process can begin. A probe card assembly may also be referred to as a probe card, when various components of the probe card assembly has been assembled together.SUMMARY
According to some embodiments, a probe card for testing a semiconductor wafer is provided. The probe card comprises a board having a first pad and a second pad disposed adjacent each other along a first direction parallel to a first surface of the board configured to face the semiconductor wafer; a first via and a second via in the board, the first via having a first contact surface in direct contact with the first pad, the second via having a second contact surface in direct contact with the second pad. A center of the first contact surface and a center of the second contact surface are offset towards each other along the first direction from respective centers of the first and second pads.
According to some embodiments, a probe card for testing a semiconductor wafer is provided. The probe card comprises a board. The board comprises a first surface, a second surface separated from the first surface in a first direction, and an interior between the first surface and the second surface. The board further comprises plurality of pads on the first surface configured to be connected with a plurality of wafer pads on the semiconductor wafer via a plurality of probe pins contacting the plurality of pads; at least one layer of conductors in the interior; and a first via in the board, elongated in the first direction and in contact with a first pad of the plurality of pads; a second via in the board, elongated in the first direction, and at least partially surrounding the first via. The second via comprises a perimeter facing the first via.
The foregoing is a non-limiting summary of the invention, which is defined by the appended claims.
Various aspects and embodiments will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing.
In probe card assemblies, an array of probe pins are each arranged perpendicularly, or “vertically” from a wafer surface, with free ends of the probe pins used to contact wafer pads the wafer. The wafer pads serve as test points during testing of a DUT on the wafer. Probe pins are arranged generally with the same pitch as wafer pads on the DUT such that a probe needle at the free end of each probe pin will land on a corresponding wafer pad during testing. The opposite ends of the probe pins are each in contact with a corresponding probe card pad on a surface of a circuit board that is part of a probe card within the probe card assembly. The probe card pads and probe pins serve to electrically interface test points on the DUT with circuitry in the rest of the tester via the circuit board in the probe card. The circuit board may have vias that route electric signals vertically through different planes within the circuit board, and conductive structures such as traces within each plane that route electric signals horizontally parallel to the plane.
Aspects of the present application are directed to a novel transposed via arrangement within a circuit board for a probe card. In some embodiments, adjacent vias are offset towards each other such that the inductance between the adjacent vias may be reduced to provide a desirable impedance during high frequency signal transmission. The inventor has recognized that inductance between adjacent conductive structures such as vias increase with the spacing between such conductive structures. When high frequency data signal and power signal are transmitted in the vias, the inter-via inductance may increase an impedance of the signal path through the vias. When the impedances are much higher than impedances of components on the DUT, which is typically 50Ω single ended and/or 100Ω differential, a large impedance mismatch is created in the signal path from the vias to and from the components in electrical contact with the probe pins, which causes undesirable signal reflections.
In some embodiments, instead of vias being spaced at a fixed pitch that is the same as corresponding wafer pads on the surface of the DUT, vias may be transposed such that they no longer contact the center of respective probe card pads on a surface of the circuit board in the probe card. In such embodiments, there is no need to shrink the probe card pad pitch and they may have the same pitch as the probe card pins that connects the probe card pads to respective wafer pads. In some embodiments, to provide electrical connection to the close proximity of the transposed vias while avoid shorting, the vias are connected to planes that are in parallel but offset vertically. Conductors in such planes may overlap each other in the vertical direction, but are nevertheless isolated without shorting due to the vertical offset, or “ganging” of the planes.
Some aspects are directed to a probe card having vias that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias. In some embodiments, shielding is achieved by at least partially surrounding the signal via with one or more ground vias. The ground via has a perimeter that face the signal via. For the ground via may be shaped as a rectangle, an arc, or a circle from a top view, such that an inner side of the rectangle, arc or circle faces and partially surrounds the signal via to provide electromagnetic shielding of the signal via from other conductive structures within the circuit board.
The aspects and embodiments describes above, as well as additional aspects and embodiments, are described further below with reference to the figures. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect. In the figures, like reference numerals are used to designate like components.
It should be appreciated that
Regardless of the number of instruments or other components generating or measuring test signals and the number of devices under test, test system 10 may include signal delivery components that route the signals between the DUT 30 and the instruments within ATE 16.
Further, it should be appreciated that other components as illustrated are exemplary rather than limiting. For example, although the test computer 12 is illustrated as a personal computer (PC) in
As shown in
DUT 30 may be one of an array of DUTs on a wafer 20 as shown in the example in
Probe pins 410 may be of a vertical-type probe pin design, where each probe pin is oriented in use substantially vertically with the wafer to be probed. Each probe pin 410 may be formed from metal wire or plated micro-electromechanical systems (MEMS) having any suitable cross-sectional shape. While
Guide plate 400 has a plurality of guide holes in which individual probe pins 410 are fitted. The guide holes are arranged in an array that aligns with the specific wafer pad array 110 on the DUT, such that the probe needles 410b of probe pins 410 can land on and make electrical contact with each corresponding wafer pads 110 during testing. In some embodiments, guide plate 400 may be considered an interposer that sits between second circuit board 300 and the DUT 30, and serves to interface routing between probe card pads 310 and wafer pads 110 on the DUT 30 by a plurality of probe pins 410. Interposer 400 may comprise a semiconductor substrate that includes an insulative material, such as a dielectric material. It should be appreciated that guide plate 400 is depicted in
During manufacturing of probe card assembly 100, guide plates 400 may be mechanically fastened to the second circuit board 300 via one or more mechanical fasteners (not shown) such that the array of probe card pads 310 and array of probe pins 410 are in contact.
Probe card pads 310 are formed of one or more layers of conductive material such as metal, and are arranged in an array that generally aligns to the array of probe pins 410 and the wafer pads 110, such that each top end 410a contacts a corresponding probe card pad 310, when a center of the pads 312 is aligned with the center 412 of the probe pin array. The center 312 of the pad array 310 may be computed as a centroid 312 of the pads in the array. Each probe card pad 310 may be of any suitable shape and spatial arrangement known in the art.
The second circuit board 300 may comprise a dielectric body, with a an array of pads 310 disposed on a surface 320 of the dielectric body that is facing the DUT. Second circuit board 300 may be a printed circuit board (PCB) or a printed wire board. In some embodiments, second circuit board 300 may be formed of multiple layers of organic materials, such as a polymer, and may be referred to as a multi-layer organic (MLO) board.
Some of the probe card pads are configured to carry test signals to corresponding test points on a wafer and may be referred to as “signal pads,” while some other probe card pads are configured to provide a reference voltage such as ground or power to the wafer, and may be referred to as “ground pads” or “power pads,” respectively. In some embodiments, the test signals, power and ground voltages are provided to signal pads, ground pads and power pads via interconnection structures within the second circuit board 300. The interconnection structures couple respective probe card pads to the rest of the test system via for example solder bumps 210 and the first circuit board 200.
Some of the vias are configured to carry test signals to corresponding test points on a wafer and may be referred to as “signal vias,” while some other vias are configured to provide a reference voltage such as ground or power to the wafer, and may be referred to as “ground vias” or “power vias,” respectively.
The test signals carried on signal pads may be signals generated within the wafer and measured from test points on the wafer, or externally generated stimulus signals provided to test points on the wafer. In some embodiments, the test signals may be a radio frequency signal having a frequency of at least 10 MHz, at least 100 MHz, at least 1 GHz, at least 10 GHz, between 1 GHz and 100 GHz, between 10 GHz and 60 GHz, or of any other frequency range suitable for semiconductor devices to be tested under a probe card assembly.
The power pads may supply external power from the tester to components on the wafer. The supplied power may be direct current (DC) power, as well as alternative current (AC) power. In some embodiments, AC power may be provided to components on the wafer at a frequency of at least 10 MHz, at least 100 MHz, at least 1 GHz, at least 10 GHz, between 10 MHz and 10 GHz, between 50 MHz and 5 GHz, or of any other frequency range suitable for semiconductor devices to be tested under a probe card assembly. Probe pins that are in contact with power pads on the board 300 may carry higher amounts of DC or AC currents than probe pins for signal pads. Some of the supplied DC or AC currents may flow through a conductive path from a power pad on the probe card circuit board, to a probe pin connected to the power pad, to a corresponding wafer pad on the wafer under test, to components within the wafer under test, and return to one or more grounds pads on the probe card circuit board via corresponding probe pins and wafer pads.
In some embodiments, circuit boards within a probe card can have additional components that can process or condition signals on the probe card pads. The additional components may be passive or active components, such as but not limited to discrete resistors, capacitors, inductors, or any suitable combination thereof. In the example illustrated in
High frequency transient power is supplied either from the tester, bypass capacitors, or from components on the wafer under test itself. In some embodiments, the wafer may be tested in a loop back configuration, where high frequency digital, analog or power signals are transmitted form a current path that originates from components at a first region on the wafer under test, upwards via a wafer pad and corresponding probe pin to a first probe card pad, routed via one or more traces, planes and vias within a circuit board in the probe card to a second probe card pad, and then to components at a second region on the wafer under test via its corresponding wafer pad and a probe pin connected to the second probe card pad.
Regardless of how signals and power are assigned to the array of probe card pads in the probe card assembly, the inventor has recognized that when high frequency test signals and high frequency transient power signals are routed using the vias and planes 304 to the DUT, high impedance from the high inductive coupling between adjacent vias may undesirable lead to impedance mismatch and signal loss at the wafer. To solve this problem, aspects of the present application are directed to providing an arrangement of vias within the probe card circuit board that places vias in close proximity to each other. Furthermore, the vias may be arranged in some embodiments such that power and/or ground vias surround a signal via to provide a radio frequency shielding to the signal via and reduce crosstalk between signal vias.
First pad 3101 and second pad 3102 may be disposed on the same plane parallel to the surface 320 of the board, and are formed of a suitable metal conductive material known in the art. In some embodiments, pads 3101, 3102 may be wafer card pads similar to wafer card pad 310 disposed on surface 320 of the board 300 as shown in
As shown in
Each via may be an axio-symmetric structure about a vertical axis, with the contact surfaces 3203, 3204 having a circular or oval shape as illustrated in
Any suitable semiconductor manufacturing technique may be used for creation of via holes in a layer of MLO board material, such as but not limited to patterned etching, mechanical drilling, or laser drilling. Each via segment 3211, 3212 may be cylindrical or cone shaped as illustrated in
In some embodiments, the contact surfaces 3203, 3204 may be circular and have a diameter of about 40 μm. The via center-to-center spacing D1 along the transverse direction may be about 80 μm. The via center-to-center spacing D4 along the longitudinal direction may be about 60 μm. The width D2 for each pad 3101, 3102 may be about 110 μm, with the two pads having a center-to-center pitch D3 of about 130 μm, such that a gap D5 of about 20 μm is between the two pads. It should be appreciated that the dimensions as described above are by way of example only and aspects of the present application are not so limited. For example, D1 may be pushed to be as close to the gap between the two pads as possible, with the consideration that spacing between the two vias is not designed to be lower than the permissible lateral resolution and tolerance during the via manufacturing process.
It should be appreciated that while only a pair of vias a few pads and planes are illustrated, such depiction is for simplicity and illustrative purpose only and embodiments of the present application may have any number of like components in a probe card assembly.
While cylindrically-shaped vias are shown in
Vias 4201, 4202 may sometimes be referred to as rectangular vias. It should be appreciated that techniques for manufacturing vias 3201, 3202 may be readily modified to fabricate rectangular vias. For example, rectangular trenches may be patterned in each layer of the MLO board, prior to filling in the trench to form rectangular via segments 4211, 4212 that stack up vertically to form via 4201, 4202.
The center-to-center spacing D6 of via array 5201 as shown in
Some aspects are directed to a probe card having vias having a coaxial arrangement that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias and create controlled impedance structures.
A plurality of ground vias 6202 on top of ground conductors 6232 are provided in the board 300 adjacent the signal via 6201.
Still referring to
Referring back to
Referring back to
While the ground via in the coaxial arrangement in the embodiment shown in
In some embodiments, shielding is achieved by at least partially surrounding the signal via with one or more ground vias. The ground via has a perimeter that face the signal via. For the ground via may be shaped as a rectangle, an arc, or a circle from a top view, such that an inner side of the rectangle, arc or circle faces and partially surrounds the signal via to provide electromagnetic shielding of the signal via from other conductive structures within the circuit board.
Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. For example, while rectangles, arcs and circles are described in relation to
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Further, though advantages of the present invention are indicated, it should be appreciated that not every embodiment of the technology described herein will include every described advantage. Some embodiments may not implement any features described as advantageous herein and in some instances one or more of the described features may be implemented to achieve further embodiments. Accordingly, the foregoing description and drawings are by way of example only.
Various aspects of the present invention may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.
Also, the invention may be embodied as a method, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
Use of ordinal terms such as “first,” “second,” “third,” etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.
The terms “approximately” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and yet within ±2% of a target value in some embodiments. The terms “approximately” and “about” may include the target value.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
1. A probe card for testing a semiconductor wafer, the probe card comprising:
- a board comprising: a first surface, a second surface separated from the first surface in a first direction, and an interior between the first surface and the second surface; a plurality of pads on the first surface configured to be connected with a plurality of wafer pads on the semiconductor wafer via a plurality of probe pins contacting the plurality of pads; at least one layer of conductors in the interior; and a first via in the board, elongated in the first direction and in contact with a first pad of the plurality of pads; a second via in the board, elongated in the first direction, and at least partially surrounding the first via,
- wherein: the second via comprises a perimeter facing the first via.
2. The probe card of claim 1, wherein the first via is a signal via, and the second via is a ground via.
3. The probe card of claim 2, wherein the second via comprises a plurality of vias connected to a common ground plane in the board.
4. The probe card of claim 2, wherein the second via comprises a plurality of trenches extending in a plane perpendicular to the first direction.
5. The probe card of claim 1, wherein the perimeter is elongated along a second direction in parallel with the first surface and is longer than an extent of the first via along the second direction.
6. The probe card of claim 1, wherein the perimeter is shaped as a rectangle.
7. The probe card of claim 1, wherein the perimeter is shaped as an arc.
8. The probe card of claim 1, wherein the perimeter is shaped as a circle.
9. The probe card of claim 1, wherein the first pad is disposed in a first plane, and the second via is in contact with a second pad disposed in a second plane different from the first plane.
10. The probe card of claim 9, wherein the second pad at least partially surrounds the first pad.
11. The probe card of claim 9, wherein the second pad comprises a circular opening that encloses the first pad.
12. The probe card of claim 9, further comprising a third via connecting the second pad to a third pad, wherein the third pad is coplanar with the first pad.
13. The probe card of claim 9, wherein second pad is a ground pad, and wherein the first pad is a signal pad.
14. The probe card of claim 9, wherein the first via is in direct contact with a conductor in a third plane, the second via is in direct contact with a conductor in a fourth plane, wherein:
- the second plane and the fourth plane are between the first and third planes.
15. The probe card of claim 5, wherein the second via has a trapezoidal shape at a cross-section along a plane perpendicular to the second direction.
16. The probe card of claim 1, wherein the board comprises a plurality of dielectric layers, and wherein the first via is a stack of a plurality of conductive fill material disposed within respective dielectric layers.
17. The probe card of claim 16, wherein the substrate is a multiple layer organic (MLO) board.