Patents Assigned to Teradyne, Inc.
  • Patent number: 11067629
    Abstract: Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 20, 2021
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Publication number: 20210190826
    Abstract: A probe card in an automated test equipment (ATE) and methods for operating the same for testing electronic devices. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins. The probe card has a pad geometry that compensates for misalignment with corresponding probe pins due to manufacturing error or a mismatch of coefficient of thermal expansion, enabling reliable operation of the ATE over a wide range of test temperatures. The pad array may have a plurality of elongated pads, each of uniquely designed size, tilt angle, and/or center location, with the characteristics of each pad being dependent on a distance between each pad and a centroid of the pad array, such that a probe pin to pad location errors can be mitigated.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventors: Brian Brecht, Steve Ledford
  • Publication number: 20210190828
    Abstract: A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a transposed via arrangement within a circuit board for a probe card, where adjacent vias are offset towards each other such that the inductance between the adjacent vias may be reduced to provide a desirable impedance during high frequency signal and/or power transmission.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventor: Brian Brecht
  • Publication number: 20210190825
    Abstract: A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventor: Brian Brecht
  • Publication number: 20210190827
    Abstract: Probe pin arrangements in a vertical-type probe card assembly for an automated test equipment (ATE) are disclosed. In some embodiments, one or more additional conductive regions are provided in between adjacent probe pins. The additional conductive regions may reduce spacing between probe pins connected to adjacent probe card pads, and may in turn reduce or adjust inductance between the two probe cards pads to provide improved signal impedance matching or lower power impedance. In one embodiment, the additional conductive region is a short probe pin. In another embodiment, the additional conductive region is a protrusion on a vertical probe pin.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Applicant: Teradyne, Inc.
    Inventor: Brian Brecht
  • Patent number: 11041900
    Abstract: A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 22, 2021
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Patent number: 10996272
    Abstract: An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 4, 2021
    Assignee: TERADYNE, INC.
    Inventor: Jan Paul Antonie van der Wagt
  • Patent number: 10983145
    Abstract: An example test system includes a carrier having a test socket to receive a device to test. The test socket includes electrical connections. The test system also includes a lid assembly having a socket cap to contact the device to apply pressure to cause the device to connect electrically to the electrical connections. The socket cap includes a material having a thermal conductivity that exceeds a defined value. The lid assembly also includes one or more structures configured to provide surface area over which heat from the device dissipates. The one or more structures are made of a material having a thermal conductivity that exceeds the defined value.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 20, 2021
    Assignee: TERADYNE, INC.
    Inventors: Larry W. Akers, Philip Campbell, Valquirio Nazare Carvalho, Shant Orchanian
  • Patent number: 10972192
    Abstract: An example system includes a receptacle to house a device under test (DUT); an antenna for exchanging signals with the DUT, where at least some of the signals are for use in performing radiated testing of the DUT; and a cap configured to mate to the receptacle to form a housing to enclose the DUT. The housing is for isolating the DUT at least one of physically or electromagnetically.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 6, 2021
    Assignee: TERADYNE, INC.
    Inventors: Brian Charles Wadell, Jonathan Hanes Williams, Roger Allen Sinsheimer
  • Patent number: 10955465
    Abstract: Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 23, 2021
    Assignee: Teradyne, Inc.
    Inventors: Anthony J. Suto, John Joseph Arena, Joseph Francis Wrinn
  • Patent number: 10948534
    Abstract: An example test system includes robotics configured to operate on devices at a first level of precision, and stages configured to operate at levels of precision that are less than the first level of precision. Each of the stages may include parallel paths that are configured to pass the devices between adjacent stages.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 16, 2021
    Assignee: TERADYNE, INC.
    Inventors: David Paul Bowyer, Jianfa Pei, John P. Toscano, Philip Campbell, Valquirio N. Carvalho
  • Patent number: 10942220
    Abstract: Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 9, 2021
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Greg Warwar
  • Patent number: 10923872
    Abstract: An example tool for disconnecting a connector from a circuit board includes: a first arm having first handle and a first notch, where the first notch is for engaging a first connector connected to the circuit board; and a second arm having a second handle and a second notch, where the second notch is for engaging a second connector connected to a cable. A hinge connects the first arm to the second arm. The hinge is biased so that, when the tool is not in use, the first handle and the second handle are farther apart than are the first notch and the second notch.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 16, 2021
    Assignee: TERADYNE, INC.
    Inventor: Randolph Taylor Jones
  • Patent number: 10914757
    Abstract: An example apparatus includes a connection module. The example connection module includes a connection interface and a connection matrix having a root transmission line to conduct signals to and from the connection interface. The connection matrix also includes branch transmission lines that are connectable electrically to the root transmission line to conduct the signals to and from the root transmission line. Each of the branch transmission lines is part of an electrical pathway between a device and the root transmission line. A housing encloses the connection matrix and enables access to the connection interface. The root transmission line and the branch transmission lines are each multi-conductor transmission lines that conduct the signals in transverse electromagnetic (TEM) mode.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 9, 2021
    Assignee: TERADYNE, INC.
    Inventor: Jonathan Hanes Williams
  • Patent number: 10896106
    Abstract: An example test system includes instruments for controlling testing. Each instrument may be controlled by a processing unit. Each processing unit may be configured to operate on portions of a test program relevant to an instrument that the processing unit controls. A synchronization mechanism operates with at least some processing units to produce a synchronized sequence of actions, measurements, or measurements and actions at a test instrument interface absent intervention from a centralized controller.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 19, 2021
    Assignee: Teradyne, Inc.
    Inventors: Michael C. Panis, Jeffrey S. Benagh, Richard Pye
  • Publication number: 20200379043
    Abstract: Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Applicant: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Patent number: 10845410
    Abstract: An example test system includes a test carrier to hold devices for test; a device shuttle to transport the devices; and a robot to move the devices between the test carrier and the device shuttle. The device shuttle is configured to move, towards a stage of the test system containing the robot, a first device among the devices that has not been tested. The device shuttle is configured to move in a first dimension. The robot is configured to move the first device from the device shuttle to the test carrier. The robot is configured to move in a second dimension that is different from the first dimension.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: November 24, 2020
    Assignee: TERADYNE, INC.
    Inventors: David Paul Bowyer, Jianfa Pei, John P. Toscano, Philip Campbell, Marc LeSueur Smith
  • Publication number: 20200341059
    Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice has a time constant, and is controlled to switchably connect a driver output to either a high voltage level or a low voltage level, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. The circuit slices may also have programmable capacitors that may be adjusted to provide a programmable time domain behavior of the output voltage waveform, such as a programmable voltage peaking characteristic.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Applicant: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Allan Parks, Lawrence Choi
  • Publication number: 20200343882
    Abstract: Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Applicant: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Denis Zelenin
  • Publication number: 20200341060
    Abstract: Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Applicant: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Greg Warwar