Patents Assigned to Teradyne, Inc.
  • Patent number: 10404363
    Abstract: Example pin electronics includes driver circuitry to output a first optical signal to a UUT. The first optical signal is based on a first signal representing first informational content and one or more second signal representing first parametric information. Receiver circuitry receives a second optical signal from the UUT. The second optical signal is related to a third signal representing second informational content and one or more fourth signal representing second parametric information. Comparison circuitry obtains parametric data representing at least one of the first parametric information or the second parametric information, and compares, based on the parametric data, the at least one of the first parametric information or the second parametric information to one or more thresholds. Control circuitry adjusts at least some of the first parametric information prior to output of the first optical signal, and one or more of the thresholds.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: September 3, 2019
    Assignee: Teradyne, Inc.
    Inventors: Tushar K. Gohel, Pavel Gilenberg
  • Patent number: 10401423
    Abstract: An example test system includes: a test slot to hold a device under test (DUT); a temperature control system comprising a phase-change material, with the temperature control system for maintaining a temperature of the phase-change material in a steady-state condition, with the phase-change material changing phase during a transient condition to affect a temperature of a thermally-conductive structure, and with the steady-state condition being longer in duration than the transient condition; and an air mover to direct air over the thermally-conductive structure and towards the DUT in the test slot in order to affect a temperature of the DUT.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: September 3, 2019
    Assignee: Teradyne, Inc.
    Inventors: Larry Akers, Joseph Wrinn, Philip Campbell, David Graziose
  • Patent number: 10404364
    Abstract: An example system includes circuitry to receive an input signal, to provide a related signal based on informational content of the input signal, and to obtain parametric data associated with the input signal. The parametric data represents one or more signal characteristics other than the informational content. The example system also includes a first switch that is configurable to provide first data based on the related signal to one or more first channels of the system; and a second switch that is configurable to provide second data based on the parametric data to one or more second channels of the system.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: September 3, 2019
    Assignee: Teradyne, Inc.
    Inventors: Tushar K. Gohel, David Kaushansky, Pavel Gilenberg, Pedro M. Teixeira, Casey A. Hersey, Frank L. Booth, Jr.
  • Patent number: 10387356
    Abstract: An example method is performed on a packet-oriented bus at a point between a source of a data packet and a destination of a data packet. The example method includes detecting a format of the data packet on the packet-oriented bus; determining a time at which the data packet was detected; generating a timestamp report containing the time, with the timestamp report being addressed to a device connected to the packet-oriented bus; and outputting the timestamp report to the device. Detecting, determining, generating, and outputting are performed by digital logic connected to the packet-oriented bus.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 20, 2019
    Assignee: Teradyne, Inc.
    Inventor: Lloyd K. Frick
  • Patent number: 10345418
    Abstract: Example automatic test equipment (ATE) includes: a test instrument for outputting test signals to test a device under test (DUT), and for receiving response signals based on the test signals; a device interface board (DIB) connected to the test instrument, with the DIB including an application space having a site to which the DUT connects, and with the test signals and the response signals passing through the site; and calibration circuitry in the application space on the DIB. The calibration circuitry includes a communication interface over which communications pass, with the communications comprising control signals to the calibration circuitry and measurement signals from the calibration circuitry. The calibration circuitry also includes non-volatile memory to store calibration data and is controllable, based on the control signals, to pass the test signals from the test instrument to the DUT and to pass the response signals from the DUT to the test instrument.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: July 9, 2019
    Assignee: Teradyne, Inc.
    Inventors: Brian C. Wadell, Richard Pye
  • Patent number: 10283958
    Abstract: An example system includes a channel over which signals are transmitted between test equipment and a device under test (DUT); and limiting circuitry to limit a voltage on the channel. The limiting circuitry includes a PN-junction device connected to pass current in response to the voltage on the channel exceeding a limit.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: May 7, 2019
    Assignee: Teradyne, Inc.
    Inventors: Brian Kirkish, Donald Joseph Nowakowski, Mark Christopher Cress
  • Patent number: 10276229
    Abstract: Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: April 30, 2019
    Assignee: Teradyne, Inc.
    Inventor: Jan Paul Antonie van der Wagt
  • Patent number: 10250957
    Abstract: An example system includes input circuitry configured to obtain first data corresponding to first signals on a communication channel, with the first data having a first frequency that is less than a predefined frequency; and sampling circuitry configured to sample the first data to produce second data having a second frequency that is greater than or equal to the predefined frequency. The example system also includes switching circuitry configured to support AC-coupled data having a frequency that is greater than or equal to the predefined frequency, with the switching circuitry being configured to receive the second data and to forward the second data; and output circuitry to receive the second data and parametric data representing non-information signal content, to produce third data based on the second data, and to produce, based on the third data and the parametric data, second signals for output from the system.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 2, 2019
    Assignee: Teradyne, Inc.
    Inventors: Tushar K. Gohel, Pavel Gilenberg
  • Patent number: 10195746
    Abstract: An example gripper may include: a base; two or more fingers attached to the base, with each finger being movable towards, and away from, one or more others of the fingers; and one or more ports at the base or at one or more of the fingers to provide suction through a vacuum.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 5, 2019
    Assignee: Teradyne, Inc.
    Inventor: Eric L. Truebenbach
  • Patent number: 10156611
    Abstract: Automatic test equipment (ATE) may include: a test instrument to implement a communication protocol to communicate to a unit under test (UUT), where the test instrument is memory storing bytecode that is executable, and where the test instrument being configured to identify an event in communication between the test instrument and the UUT and, in response to the event, to execute the bytecode. The ATE may also include a test computing system to execute a test program and an editor program, where the editor program is for receiving human-readable code and for generating the bytecode from the human-readable code, and the test program is for registering the event with the test instrument and for downloading the bytecode to the test instrument for storage in the memory.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: December 18, 2018
    Assignee: Teradyne, Inc.
    Inventors: Yonet A. Eracar, Michael Francis McGoldrick, Stephan Krach
  • Patent number: 10139449
    Abstract: A tester interface unit comprising a test hardware module. The test hardware module may have a simple construction, relying on control and/or signal processing in one or more tester instruments to generate or analyze test signals for a device under test. The test hardware module may be disposed within the tester interface unit, providing a short and high integrity signal path length to the device under test. The tester interface unit may include a purge gas chamber and a cooling chamber, with the hardware module penetrate a separator between those chambers, sealing an opening between the purge gas chamber and the cooling chamber. A heat spreader may move heat generated on the portion of the test hardware module in the purge gas chamber to the cooling chamber.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: November 27, 2018
    Assignee: Teradyne, Inc.
    Inventors: Michael A. Caradonna, Daniel A. Derringer, Stephen R. Wilkinson
  • Patent number: 10094854
    Abstract: An example manipulator for transporting a test head includes: a tower having a base and a track, with the track being vertical relative to the base; an arm to enable support for the test head, with the arm being connected to the track to move the test head vertically relative to the tower; one or more motors to drive movement of the arm along the track; and pneumatic cylinders to control movement of the arm to cause the test head to apply an amount of force to a peripheral device.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: October 9, 2018
    Assignee: Teradyne, Inc.
    Inventors: Gary Fowler, Vladimir Vayner
  • Patent number: 10079762
    Abstract: An example method includes broadcasting periodically, from a computing system, control packets over a network to instrument modules, where a control packet includes data representing sequence numbers of last data packets received from the instrument modules and information based on the sequence numbers, and the control packet includes slots for all of the instrument modules, with each slot containing the data that is specific to one of the instrument modules. The example method also includes receiving, at the computing system and in response to the control packet, via unicast and over the network, an acknowledgement packet from each of the instrument modules, where the acknowledgement packet includes repair information that is based on a broadcast control packet received by the instrument module from the computing system.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 18, 2018
    Assignee: Teradyne, Inc.
    Inventor: Byoung J. Keum
  • Patent number: 10060475
    Abstract: An example method includes: for a component supported by an air bearing, detecting a speed of movement of the component relative to a predefined location, the air bearing generating an air flow to elevate the component relative to a ground plane; and controlling the air bearing based, at least in part, on the speed detected.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: August 28, 2018
    Assignee: Teradyne, Inc.
    Inventors: Roger Allen Sinsheimer, Gary Fowler, Vladimir Vayner, Michael Peter Hascher, Andreas Flieher
  • Patent number: 10060968
    Abstract: An example test system includes: multiple channels, where each of the multiple channels is configured to force voltage and to source current; and circuitry to combine current sourced by the multiple channels to produce a combined current for output on a single channel to a device under test (DUT), where each of the multiple channels includes a load sharing resistor to control a contribution of the channel to the combined current.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 28, 2018
    Assignee: Teradyne, Inc.
    Inventor: Douglas W. Pounds
  • Patent number: 10048348
    Abstract: Apparatus and methods for calibrating tester channels of an automated test system. A relay matrix assembly including a plurality of microelectromechanical (MEM) switches may be used to connect a plurality of tester channels to an analyzer calibration instrument rapidly without requiring serial, robotic probing of the test channels. The relay matrix assembly may be constructed on a printed circuit board that can be attached to an interface on the tester. Calibration parameters for the test channels may be calculated from waveforms received through the relay matrix assembly and that have been corrected to remove waveform distortion introduced by the relay matrix assembly. Parameters to correct for distortion in the relay matrix assembly may be measured in advance and stored for use when calibration is to be performed.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: August 14, 2018
    Assignee: Teradyne, Inc.
    Inventor: Alan Hussey
  • Patent number: 10048304
    Abstract: Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows, the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: August 14, 2018
    Assignee: Teradyne, Inc.
    Inventors: Jason D. King, Richard Pye, Randall B. Stimson, Steven R. Shirk
  • Patent number: 10012721
    Abstract: A testing device for testing a radar device. The testing device may be configured to determine a first frequency difference between a frequency of a first signal or a second signal and a frequency of a third signal based on a first distance value; transmit to the radar device the first signal; receive the second signal from the radar device; transmit to the radar device the third signal at an offset relative to at least one of the first signal and the second signal based on the first frequency difference; and receive from the radar device a fourth signal indicating a second distance value or a second frequency difference between the frequency of the second signal and the frequency of the third signal, determined by the radar device, for comparison with the first distance value or the first frequency difference.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 3, 2018
    Assignee: Teradyne, Inc.
    Inventors: Jeorge S. Hurtarte, Daniel A. Rosenthal
  • Patent number: 9989584
    Abstract: Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: June 5, 2018
    Assignee: Teradyne, Inc.
    Inventors: Jack E. Weimer, Steven C. Price, David R. Hanna, Jeffry Baenen, Scott Skibinski
  • Patent number: 9977052
    Abstract: An example test fixture, which interfaces a tester and a unit under test (UUT), includes the following: first electrical contacts that face the tester; second electrical contacts that face the UUT; a substrate made of sections of printed first material, with the first material being electrically non-conductive, and with the substrate being between the first electrical contacts and the second electrical contacts; and structures through the substrate, with the structures including sections of second material, with the second material being electrically conductive, and with at least one of the structures electrically connecting a first electrical contact and a second electrical contact.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 22, 2018
    Assignee: Teradyne, Inc.
    Inventors: Anthony J. Suto, Joseph Francis Wrinn, John P. Toscano, John Joseph Arena