Abstract: An example apparatus is for contacting a device to change a temperature of the device. The apparatus includes a plate configured to contact the device and a channel within the plate configured to enable flow of fluid between an input port and an output port. The plate includes a thermally conductive material to conduct heat between the device and the fluid. The channel includes multiple islands arranged in series. An island among the multiple islands is arranged to receive the fluid at a first side. The island is for splitting the fluid into a first flow and a second flow and for causing the first flow and the second flow to merge at a second side of the island that is downstream of the first side of the island.

Abstract: Example circuitry is usable in testing a device under test (DUT). The circuitry includes test inputs; a resistor ladder including resistors electrically connected in series, with the resistor ladder being electrically connected to each of the test inputs; and first operational amplifiers, with each first operational amplifier including a first input and a first output, with each first input being electrically connected to the resistor ladder, and with each first output to electrically connect to the DUT. The circuitry includes floating circuitry which includes a second operational amplifier. The second operational amplifier includes a second input electrically connected to the resistor ladder and a reference input; a first power input to receive a first voltage; and a second power input to receive a second voltage. The floating circuitry is configured to apply the first voltage and the second voltage to power inputs of each of the first operational amplifiers.

Abstract: An example test system includes a test instrument configured to test a device under test (DUT). The test instrument is configured to interact with the DUT using first commands having a first syntax. The test system also includes one or more processing devices configured (i) to receive a definitions file, where the definitions file includes information defining a second syntax that is used by a third party to communicate with the DUT, (ii) to receive second commands having the second syntax, (iii) to convert the second commands into the first commands having the first syntax based on the definitions file, and (iv) to send the first commands to the test instrument to enable the test instrument to interact with the DUT.

Abstract: Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor.

Abstract: An example waveguide connector is for making a blind-mate electrical connection between a first waveguide and a second waveguide. The waveguide connector includes a male part connected to the first waveguide, where the first waveguide includes a first conductive channel, and a female part connected to the second waveguide, where the second waveguide includes a second conductive channel. The female part includes a receptacle into which the male part slides to create the blind-mate electrical connection between the first conductive channel and the second conductive channel. A self-alignment feature is on at least one of the male part or the female part. The self-alignment feature is configured to guide the male part into the receptacle while correcting for misalignment of the male part and the female part.

Abstract: An example method performed for a circuit path includes: receiving signals in the circuit path; and controlling states of the signals in the circuit path based on skews produced by circuits electrically connected in series in the circuit path. The states are controlled by inverting or not inverting the signals in the circuit path so that skews produced by different circuits in the circuit paths at least partially cancel.

Abstract: An example probe for a test system includes a conductor to carry direct current (DC) signals between a DC testing resource and a signal trace on the test system, where the signal trace is for carrying the DC signals and alternating current (AC) signals to and from a device under test; and an inductor connected in series with the conductor. A mechanism is included in the probe for enabling the conductor to move toward the signal trace or a pin electrically connected to the signal trace to create an electrical connection between the conductor and the signal trace to enable the testing resource to transmit the DC signals to the signal trace, and to move away from the signal trace or the pin so that no electrical connection is created between the conductor and the signal trace when the DC signals are not to be transmitted to the signal trace.

Abstract: An example test socket for a test system includes a receptacle to make electrical and mechanical connections to a device under test (DUT) and a lid to cover the DUT in the receptacle. The lid is controllable to open automatically to enable receipt of the DUT in the receptacle and, following receipt of the DUT, to close automatically to cover the DUT in the receptacle. Closing the lid applies force to the DUT to complete the electrical and mechanical connections between the test socket and the DUT.

Abstract: An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

Abstract: An example printed circuit board (PCB) includes a substrate having layers of a dielectric material, where the layers of dielectric material include a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; and a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, where the conductive via is configured also to connect electrically to a signal input to receive or to transmit a signal that has a center frequency span.

Abstract: An example test system includes packs. The packs include test sockets for testing devices under test (DUTs) and at least some test electronics for performing tests on the DUTs in the test sockets. Different packs are configured to have different configurations. The different configurations include at least different numbers of test sockets arranged at different pitches.

Abstract: Example techniques may be implemented as a method, a system or more non-transitory machine-readable media storing instructions that are executable by one or more processing devices, Operations performed by the example techniques include obtaining data representing results of tests executed by one or more test instruments on an initial set of devices under test (DUTs) in a test system; and using the data to train a machine learning model. The machine learning model is for predicting which of the tests will produce failing results for a different set of DUTs. DUTs in the different set have one or more features in common with DUTs in the initial set.

Abstract: An example system includes a first circuit board having first conductive traces, where a first conductive trace is for conducting an alternating current (AC) digital signal having an edge; a second circuit board having second conductive traces, where a second conductive trace is within a predefined distance of the first conductive trace to produce a contactless coupling with the first conductive trace, and where the contactless coupling enables electrical energy on the first conductive trace to manifest on the second conductive trace as a transient response that is based on the edge; and circuitry to reconstruct the edge based on the transient response from the second conductive trace.

Abstract: An example test system includes test sites comprising test sockets for testing devices under test (DUTs) and pickers for picking DUTs from the test sockets or placing the DUTs into the test sockets. Each picker may include a picker head for holding a DUT. The test system also includes a gantry on which the pickers are mounted. The gantry may be configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the test sockets or placing the DUTs into the test sockets. The test sockets are arranged in at least one array that is accessible to the pickers on the gantry.

Abstract: An example test system includes test sites that include sockets for testing devices under test (DUTs), pickers for picking DUTs from the sockets or placing the DUTs in the sockets, and a gantry on which the pickers are mounted. The gantry is configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the sockets or placing the DUTs into the sockets. The test system also includes one or more LASER range finders mounted on the gantry for movement over the DUTs in the sockets and in conjunction with movement of the pickers. A LASER range finder among the one or more LASER rangefinders mounted on the gantry is configured to detect a distance to a DUT placed into a socket.

Abstract: An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.

Abstract: An example contact head includes coaxial contacts configured for transmission of radio frequency (RF) signals or digital signals between a test system and a device under test (DUT). Each of the coaxial contacts is configured to target a specific impedance. Each of the coaxial contacts includes a coaxial structure having an open-curve shape. The coaxial structure includes a spring material that bends in response to applied force and that returns to the open-curve shape absent the applied force. The coaxial structure includes a center conductor terminating in a contact pin and a return conductor separated by a dielectric from the center conductor. At least part of the center conductor and the return conductor include an electrically-conductive material. Flexible contacts on the coaxial contact include the electrically-conductive material.

Abstract: Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor.

Abstract: An example test system includes test sites for testing devices under test (DUTs), where the test sites include a test site configured to hold a DUT for testing. The test system includes a thermal control system to control a temperature of the DUT separately from control over temperatures of other DUTs in other test sites. The thermal control system includes a thermoelectric cooler (TEC) and a structure that is thermally conductive. The TEC is in thermal communication with the DUT to control the temperature of the DUT by transferring heat between the DUT and the structure.

Abstract: An example test system includes a test socket for testing a DUT, a lid for the test socket, and an actuator configured to force the lid onto the test socket and to remove the lid from the test socket. The actuator includes an upper arm to move the lid, an attachment mechanism connected to the upper arm to contact the lid, where the attachment mechanism is configured to allow the lid to float relative to the test socket to enable alignment between the lid and the test socket, and a lower arm to anchor the actuator to a board containing the test socket. The actuator is configured to move the upper arm linearly towards and away from the test socket and to rotate the upper arm towards and away from the test socket.