SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREOF
The present application discloses a semiconductor structure and a preparation method. The semiconductor structure includes a heterojunction, including at least two sets of channel layers and barrier layers stacked sequentially; a first p-type semiconductor, disposed in a gate region of the heterojunction and extended to a bottom of the heterojunction; and a second p-type semiconductor, disposed on the gate region of the heterojunction. By providing a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially, multilayer 2DEG is realized by using multilayer channel layers and barrier layers to increase the concentration of 2DEG, thereby reducing the resistance. Since a first p-type semiconductor is disposed in a gate region of the heterojunction, the p-type semiconductor materials in the first p-type semiconductor are used to deplete the 2DEG to realize normally-off and increase the threshold voltage.
This application is a continuation of International Application No. PCT/CN2019/130513 filed on Dec. 31, 2019, the disclosure of which is hereby incorporated by reference in its entirety.
TECHNICAL FIELDThe present application relates to the field of semiconductors, and more particularly to a structure of a normally-off device and a preparation method thereof.
BACKGROUNDCurrently, in a normally-off device, a gallium nitride layer doped with p-type impurities is formed under a gate to deplete the two-dimensional electron gas (2DEG) under the gate. When a forward voltage is not applied to the gate, the concentration of 2DEG under the gate is 0, thereby realizing normally-off.
However, there are two problems with the above structure.
1. The concentration of 2DEG is low, which results in a high resistance when the device is turned on.
2. The threshold voltage is low.
SUMMARYIn view of this, the present application provides a semiconductor structure, which solves the problems of high resistance and low threshold voltage when the device mentioned above is turned on.
An embodiment of the present application discloses a semiconductor structure, including: a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially; a first p-type semiconductor disposed in a gate region of the heterojunction and extended to a bottom of the heterojunction; and a second p-type semiconductor disposed on the gate region of the heterojunction.
In another embodiment, the semiconductor structure further includes: a source disposed on a source region of the heterojunction, a drain disposed on a drain region of the heterojunction, and a gate disposed above the gate region of the heterojunction.
In another embodiment, materials of the first p-type semiconductor, the second p-type semiconductor and the heterojunction include a gallium nitride based material.
In another embodiment, the semiconductor structure further includes a substrate disposed under the heterojunction.
In another embodiment, the semiconductor structure further includes a nucleation layer and a buffer layer, disposed sequentially between the substrate and the heterojunction.
In another embodiment, the semiconductor structure further includes a regrowth layer, disposed between the first p-type semiconductor and the heterojunction.
In another embodiment, the semiconductor structure further includes an in-situ insulation layer and a transition layer, which are disposed between the second p-type semiconductor and the heterojunction. The in-situ insulation layer is provided with a through recess in the gate region, and the transition layer is disposed on the in-situ insulation layer and in the through recess.
In another embodiment, the semiconductor structure further includes an insulation dielectric layer, disposed on the second p-type semiconductor and the heterojunction, and under the gate.
An embodiment of the present application also discloses a preparation method of a semiconductor structure, including: preparing a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially; preparing a recess in a gate region of the heterojunction, wherein the recess extends to a bottom of the heterojunction, and the recess is filled with a first p-type semiconductor; and preparing a second p-type semiconductor and a gate on the gate region of the heterojunction sequentially.
In another embodiment, the preparation method of a semiconductor structure further includes: preparing a source and a drain on a source region and a drain region of the heterojunction respectively.
In another embodiment, the preparation method of a semiconductor structure further includes: preparing a regrowth layer on the heterojunction before filling the recess with the first p-type semiconductor.
In another embodiment, before the preparing a recess in a gate region of the heterojunction, the preparation method of a semiconductor structure further includes: preparing an in-situ insulation layer and a transition layer on the heterojunction; removing the in-situ insulation layer and the transition layer on the gate region of the heterojunction.
In another embodiment, before the preparing a recess in a gate region of the heterojunction, the preparation method of a semiconductor structure further includes: preparing an in-situ insulation layer on the heterojunction; removing the in-situ insulation layer on the gate region of the heterojunction; and preparing a transition layer covering the in-situ insulation layer and exposed heterojunction.
According to a semiconductor structure provided by the embodiments of the present application, by providing a heterojunction including at least two sets of channel layers and barrier layers stacked sequentially, multilayer 2DEG is realized by using multilayer channel layers and barrier layers to increase the concentration of 2DEG, thereby reducing the resistance. Since a first p-type semiconductor is disposed in a gate region of the heterojunction, the p-type semiconductor materials in the first p-type semiconductor are used to deplete the 2DEG to realize normally-off and increase the threshold voltage. The design of a regrowth layer may improve the reliability of the device. An in-situ insulation layer and a transition layer may reduce the gate leakage current caused by leakage from channel to the gate in the device, so the thickness of the barrier layer in the heterojunction may be smaller to increase the threshold voltage. In addition, due to the disposition of an in-situ insulation layer, the block resistance may be reduced, the concentration of 2DEG may be increased, the control ability of the gate to the channel may be improved, and the working current may be increased.
A clear and complete description of technical solutions of the embodiments of the present application will be given below, in combination with the accompanying drawings in the embodiments of the present application. Apparently, the embodiments described below are a part, but not all, of the embodiments of the present application. All of other embodiments, obtained by those skilled in the art based on the embodiments of the present application without any inventive efforts, fall into the protection scope of the present application.
Furthermore, in the exemplary embodiments, because the same reference numeral represents the same component with the same structure or the same step of the same method, if an embodiment is described exemplarily, only structures or methods that are different from the described embodiment are described in other exemplary embodiments.
In the whole specification and the claims, when a component is described as being “connected” to another component, the component may be “directly connected” to another component, or “electrically connected” to another component through a third component. In addition, unless an explicit description is made to the contrary, the term “including” and its corresponding terms should only be construed as including the said component, and should not be construed as excluding any other components.
The arrangement of multiple channel layers and barrier layers may realize multilayer 2DEG to improve the concentration of the 2DEG. The arrangement of the first p-type semiconductor and the second p-type semiconductor may deplete the 2DEG in the gate region of the heterojunction 1 to achieve a normally-off state.
In the embodiment, three first p-type semiconductors 2 are provided. It should be understood that the number of the first p-type semiconductors may be selected according to the requirements of actual application scenarios in the embodiments of the present application, and the present application is not limited thereto.
As an embodiment shown in
The heterojunction 1, the first p-type semiconductor 2 and the second p-type semiconductor 6 all include a gallium nitride based material.
In the above embodiment, the cross section of the first p-type semiconductor 2 is rectangular. However, the present application is not limited thereto. In another embodiment, as shown in
The present application also provides a preparation method of a semiconductor structure, and as shown in
Step S1, preparing a heterojunction 1, including at least two sets of channel layers 11 and barrier layers 12 stacked sequentially;
Step S2, preparing a recess in a gate region of the heterojunction 1. The recess extends to a bottom of the heterojunction 1, and the recess is filled with a first p-type semiconductor 2.
Step S3, preparing a second p-type semiconductor 6 on the gate region of the heterojunction 1 sequentially.
Step S4, preparing a source 3, a drain 4 and a gate 5 on a source region, a drain region and the gate region of the heterojunction 1 respectively.
It should be understood that the recess extends to the bottom of the heterojunction may be that, the recess penetrates the heterojunction as shown in
As shown in
As shown in
preparing an insulation dielectric layer 20, which is disposed on the second p-type semiconductor 6 and the heterojunction 1.
Additional step may be added between step S1 and step S2: preparing an in-situ insulation layer 13 and a transition layer 14. Specifically, there are two ways to implement.
The first way is shown in
S210, preparing an in-situ insulation layer 13 and a transition layer 14 on the heterojunction 1.
S211, removing the in-situ insulation layer 13 and the transition layer 14 on the gate region of the heterojunction 1.
The second way is shown in
S220, preparing an in-situ insulation layer 13 on the heterojunction 1.
S221, removing the in-situ insulation layer 13 on the gate region of the heterojunction 1.
S222, preparing a transition layer 14 on the heterojunction 1 and the in-situ insulation layer 13.
Furthermore, when the preparation method of a semiconductor structure in the present application includes steps S210 and S211, or steps S220, S221 and S222, as shown in
The material of the in-situ insulation layer 13 may include at least one of SiN and SiAlN. The material of the transition layer 14 may include at least one of AlN, SiAlN and AlGaN. The in-situ insulation layer and transition layer may reduce the gate leakage current caused by leakage from the channel to the gate in the device, so the thickness of the barrier layer in the heterojunction may be smaller to increase the threshold voltage. In addition, the dispose of the in-situ insulation layer may reduce the block resistance, increase the concentration of 2DEG, improve the control ability of the gate to the channel, and increase the working current. Due to the dispose of the in-situ insulation layer 13 and the transition layer 14, the second p-type semiconductor 6 may be disposed on the transition layer 14 in the gate region, and the second p-type semiconductor 6 may also be disposed on the transition layer 14 in the region between the source and the gate and the region between the drain and the gate, so that there is no need to remove all the second p-type semiconductor 6 in regions besides the gate region when preparing the second p-type semiconductor 6 on the transition layer 14, and the craft difficulty may be reduced.
The above are only the preferred embodiments of the present application and are not configured to limit the scope of the present application. Any modifications, equivalent substitutions and so on made within the spirit and principle of the present application should be included within the scope of the present application. It should be understood that the embodiments described above may be combined arbitrarily as long as it conforms to the purpose of the present application.
Claims
1. A semiconductor structure, comprising:
- a heterojunction, comprising at least two sets of channel layers and barrier layers stacked sequentially;
- a first p-type semiconductor, disposed in a gate region of the heterojunction and extended to a bottom of the heterojunction; and
- a second p-type semiconductor, disposed on the gate region of the heterojunction.
2. The semiconductor structure of claim 1, further comprising:
- a source disposed on a source region of the heterojunction, a drain disposed on a drain region of the heterojunction, and a gate disposed above the gate region of the heterojunction.
3. The semiconductor structure of claim 2, further comprising:
- an insulation dielectric layer, disposed on the second p-type semiconductor and the heterojunction, and under the gate.
4. The semiconductor structure of claim 1, wherein materials of the first p-type semiconductor, the second p-type semiconductor and the heterojunction comprise a gallium nitride based material.
5. The semiconductor structure of claim 1, further comprising:
- a substrate, disposed under the heterojunction.
6. The semiconductor structure of claim 5, further comprising:
- a nucleation layer and a buffer layer, disposed sequentially between the substrate and the heterojunction.
7. The semiconductor structure of claim 6, wherein the nucleation layer comprises one or more combinations of the following materials: aluminum nitride, gallium nitride, and aluminum gallium nitrogen.
8. The semiconductor structure of claim 6, wherein the buffer layer comprises one or more combinations of the following materials: aluminum nitride, gallium nitride, aluminum gallium nitrogen, and aluminum indium gallium nitrogen.
9. The semiconductor structure of claim 1, further comprising:
- a regrowth layer, disposed between the first p-type semiconductor and the heterojunction.
10. The semiconductor structure of claim 1, further comprising:
- an in-situ insulation layer and a transition layer, disposed between the second p-type semiconductor and the heterojunction.
11. The semiconductor structure of claim 10, wherein the second p-type semiconductor penetrates the in-situ insulation layer and the transition layer to contact directly with the heterojunction.
12. The semiconductor structure of claim 10, wherein the transition layer penetrates the in-situ insulation layer and contacts directly with the heterojunction, and the second p-type semiconductor is disposed on the transition layer.
13. The semiconductor structure of claim 10, wherein a material of the in-situ insulation layer comprises at least one of SiN and SiAlN; and a material of the transition layer comprises at least one of AlN, SiAlN and AlGaN.
14. A preparation method of a semiconductor structure, comprising:
- preparing a heterojunction comprising at least two sets of channel layers and barrier layers stacked sequentially;
- preparing a recess in a gate region of the heterojunction, wherein the recess extends to a bottom of the heterojunction, and the recess is filled with a first p-type semiconductor; and
- preparing a second p-type semiconductor on the gate region of the heterojunction sequentially.
15. The preparation method of claim 14, further comprising:
- preparing a source, a drain and a gate on a source region, a drain region and the gate region of the heterojunction respectively.
16. The preparation method of claim 14, wherein materials of the first p-type semiconductor, the second p-type semiconductor and the heterojunction comprise a gallium nitride based material.
17. The preparation method of claim 14, further comprising:
- preparing a regrowth layer on the heterojunction before filling the recess with the first p-type semiconductor.
18. The preparation method of claim 14, before the preparing a recess in a gate region of the heterojunction, the method further comprising:
- preparing an in-situ insulation layer and a transition layer on the heterojunction; and
- removing the in-situ insulation layer and the transition layer on the gate region of the heterojunction.
19. The preparation method of claim 14, before the preparing a recess in a gate region of the heterojunction, the method further comprising:
- preparing an in-situ insulation layer on the heterojunction;
- removing the in-situ insulation layer on the gate region of the heterojunction; and
- preparing a transition layer covering the in-situ insulation layer and exposed heterojunction.
20. The preparation method of claim 14, further comprising:
- preparing an insulation dielectric layer after preparing the second p-type semiconductor, to make the insulation dielectric layer dispose on the second p-type semiconductor and the heterojunction.
Type: Application
Filed: May 10, 2021
Publication Date: Aug 26, 2021
Patent Grant number: 12136668
Inventors: Kai CHENG (Suzhou), Peng XIANG (Suzhou)
Application Number: 17/315,665