Patents by Inventor Kai Cheng

Kai Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261479
    Abstract: A method for manufacturing an electronic device is provided. The method for manufacturing the electronic device includes: providing a substrate with elements disposed thereon and transferring at least one of the elements from the substrate to a driving substrate, which includes illuminating a region of the substrate overlapped with the at least one of the elements by an energy beam, wherein the driving substrate includes a circuit board and a pixel defining layer disposed on the circuit board, and the pixel defining layer includes a hole for accommodating the at least one of the elements. A bottom surface of the at least one of the elements is higher than a top surface of the pixel definition layer when the region of the substrate is illuminated by the energy beam.
    Type: Application
    Filed: April 1, 2025
    Publication date: August 14, 2025
    Applicant: Innolux Corporation
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Jian-Jung Shih, Fang-Ying Lin, Hui-Chieh Wang, Wan-Ling Huang
  • Publication number: 20250246494
    Abstract: A semiconductor structure includes a substrate, a channel layer, a barrier layer, and a passivation layer sequentially stacked; the passivation layer includes first and second passivation layers, the first passivation layer has a plurality of strip-shaped structures, a first groove is formed between any two adjacent strip-shaped structures, the second passivation layer at least covers the first groove, and an ability of the second passivation layer to consume a two-dimensional electron gas is greater than that of the first passivation layer to consume a two-dimensional electron gas. A concentration of a two-dimensional electron gas in the channel layer below the second passivation layer is modulated by using the high-concentration hydrogen ion in the second passivation layer, so that a decrease of a transconductance curve at a relatively large drain current is slowed down to improve a transconductance flatness of a device, improving a linearity of the device.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 31, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Patent number: 12376355
    Abstract: The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a channel region, a source region and a drain region; one or more grooves provided in at least one of the source region or the drain region, where, for each of the grooves, a length of a first side edge adjacent to the channel region and located on a bottom wall of the groove is larger than a length of an orthographic projection of the first side edge on a vertical plane in a length direction of the channel region; a source region N-type ion heavily-doped layer and a drain region N-type ion heavily-doped layer; and a gate electrode, a source electrode, and a drain electrode.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: July 29, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 12364085
    Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and manufacturing methods for semiconductor structure and substrate thereof. In the method for manufacturing the substrate, at least one of groove is provided in each subunit region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two subunit regions, the at least one of groove is filled with heat conduction materials to form a substrate; in one of the at least one unit region, the at least two subunit regions respectively have different heat conduction coefficients.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 15, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Publication number: 20250227981
    Abstract: The present disclosure provides a HEMT device and a manufacturing method thereof. The HEMT device includes: a substrate, a heterojunction structure, a P-type semiconductor layer, a first stress layer and/or a second stress layer, a gate, a source and a drain, where the first stress layer is located on the opposite sidewalls of the P-type semiconductor layer, and is configured to apply compressive stress to the P-type semiconductor layer in the direction parallel to the plane where the substrate is located, and to apply tensile stress to the P-type semiconductor layer in the direction perpendicular to the plane where the substrate is located. The second stress layer is located on the top wall of the P-type semiconductor layer, and is configured to apply compressive stress to the P-type semiconductor layer in the direction parallel to the plane where the substrate is located.
    Type: Application
    Filed: November 5, 2021
    Publication date: July 10, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Peng XIANG, Kai CHENG
  • Patent number: 12352823
    Abstract: The present application provides method and circuit for monitoring a power supply, which firstly obtains an auxiliary side voltage from a switching power supply and then adopts a divided voltage circuit to obtain a divided voltage from the auxiliary side voltage, for detecting the divided voltage and a detected current flowed in the detection circuit with adopting a first detection circuit and a second detection circuit in an switch circuit to correspondingly generate a first and a second detection signals, which is corresponding to an ambient temperature and an output voltage of the power supply. Hereby, the power supply is monitored.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: July 8, 2025
    Assignee: Infsitronix Technology Corporation
    Inventors: Yuan-Kai Cheng, Chun-Chiang Chen
  • Patent number: 12356763
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure may include: a first epitaxial layer disposed on a substrate; a bonding layer disposed on the first epitaxial layer (where the bonding layer is provided with a first through-hole to expose the first epitaxial layer); a silicon substrate disposed on a side of the bonding layer away from the first epitaxial layer (where the first epitaxial layer is bonded to the silicon substrate by the bonding layer, the silicon substrate is provided with a through-silicon-via, and the through-silicon-via communicates with the first through-hole); a silicon device disposed on the silicon substrate; and a second epitaxial layer disposed on the first epitaxial layer exposed by the first through-hole. The present disclosure can improve the quality of the second epitaxial layer, and realize the integration of a silicon device and a III-V semiconductor device.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: July 8, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Liyang Zhang
  • Patent number: 12356649
    Abstract: The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: July 8, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Yu Zhu
  • Patent number: 12349506
    Abstract: A preparation method for a resonant cavity light-emitting diode comprises: forming a first mirror and a first semiconductor layer on a substrate in sequence; forming an active layer on the first semiconductor layer; and forming a second semiconductor layer and a second mirror on the active layer in sequence. The preparation method further comprises: planarizing at least one of a first contact surface between the first semiconductor layer and the first mirror, and a second contact surface between the second semiconductor layer and the second mirror. Since the first contact surface between the first semiconductor layer and the first mirror, and/or the second contact surface between the second semiconductor layer and the second mirror is planarized, the light emission uniformity of the resonant cavity light-emitting diode can be improved.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: July 1, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 12349512
    Abstract: Disclosed are a light-emitting device, a template of the light-emitting device and preparation methods thereof. The template of the light-emitting device comprises a substrate; a GaN-based semiconductor layer and a mask layer provided on the substrate, where the mask layer comprises a plurality of mask openings provided at intervals, and the plurality of mask openings are filled with the GaN-based semiconductor layer; and a sacrificial layer provided on a surface of the GaN-based semiconductor layer away from the substrate and located in the plurality of mask openings provided at intervals.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 1, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Liyang Zhang
  • Patent number: 12349377
    Abstract: According to the preparation method for a semiconductor structure provided in the present application, a selective epitaxial growth method is used, without etching the n-type semiconductor layer and the p-type semiconductor layer, thus avoiding problems such as uncontrollable etching depth and damaged etched surface, which effectively reduces gate leakage, maintains low resistance in a channel region, suppresses current collapse, and improves reliability and stability of a device.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 1, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Publication number: 20250203947
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a channel structure on the substrate. The channel structure includes a first intermediate layer, a channel layer, and a second intermediate layer that are stacked. The channel structure includes a gate region and source and drain regions located at both ends of the gate region. A first N-type heavily doped layer is located between the substrate and the channel structure, and the second N-type heavily doped layer is located on the side of the channel structure far from the substrate. The projections of the first N-type heavily doped layer and the second N-type heavily doped layer on the channel structure are located within the gate region. A gate is located on the gate region. The gate covers the sidewalls of the first N-type heavily doped layer, the channel layer, and the second N-type heavily doped layer.
    Type: Application
    Filed: June 6, 2024
    Publication date: June 19, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Publication number: 20250203948
    Abstract: The present disclosure provides a semiconductor structure, including: a substrate; a channel structure on the substrate, a first N-type heavily doped layer and a second N-type heavily doped layer. The channel structure includes a first intermediate layer, a channel layer, and a second intermediate layer that are sequentially arranged on the substrate, where a width of a cross-section of the channel layer is smaller than a width of a cross-section of the first intermediate layer, and the second intermediate layer covers sidewalls of the channel layer and a surface of the channel layer far from the first intermediate layer. The first N-type heavily doped layer is between the substrate and the channel structure, and the second N-type heavily doped layer is on a side of the channel structure far from the substrate.
    Type: Application
    Filed: June 6, 2024
    Publication date: June 19, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Patent number: 12336207
    Abstract: Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: June 17, 2025
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Dandan Zhu
  • Publication number: 20250191918
    Abstract: Disclosed are a dielectric structure, a semiconductor device structure, and manufacturing methods therefor. The manufacturing method for the dielectric structure includes: performing Al doping to a surface of a SiC substrate to form an Al-doped SiC layer and then oxidizing the Al-doped SiC layer to form a dielectric layer including at least a SiAlO layer. On one hand, thermal oxidation temperature required for oxidizing SiC to SiO2 may be reduced, so that an interface state with a high density at an interface of SiC/SiO2 is reduced, and quality of the dielectric layer is improved. On the other hand, original Si in the SiO2 is replaced with Al, a more stable structure may be formed, and the quality of the dielectric layer is further improved.
    Type: Application
    Filed: October 23, 2024
    Publication date: June 12, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Publication number: 20250194172
    Abstract: A semiconductor structure includes: a substrate, a channel layer and a barrier layer which are stacked sequentially, the channel layer and the barrier layer including a gate region, and a source region and a drain region which are located on two sides of the gate region; a p-type semiconductor layer, located in the gate region; a first hydrogen-rich layer, located on a side, close to the drain region, of the p-type semiconductor layer, a hydrogen concentration of the first hydrogen-rich layer being greater than a hydrogen concentration of the p-type semiconductor layer; a gate, a source and a drain, where the gate is located on a side, away from the substrate, of the p-type semiconductor layer, the source is located in the source region, and the drain is located in the drain region.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 12, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Publication number: 20250194192
    Abstract: Disclosed are a dielectric structure, a semiconductor device structure and manufacturing methods therefor. The manufacturing method for the dielectric structure includes growing a single-crystal AlN layer on the SiC substrate, and then simultaneously oxidizing the SiC substrate and the single-crystal AlN layer to form a composite dielectric layer including a SiO2 layer and a single-crystal AlOX layer. By simultaneously oxidizing the single-crystal AlN layer provided on the surface of the SiC substrate and the SiC substrate, on the one hand, the AlOX layer includes a higher background concentration of nitrogen, so that nitrogen ions diffuse into the SiO2, thereby improving the interface characteristics of the SiC/SiO2; and on the other hand, after oxidation of the single-crystal AlN layer, the single-crystal AlOX layer with wide band gap and high-density may be introduced, so that the single-crystal AlOX has good quality and a high-quality interface with SiO2.
    Type: Application
    Filed: October 31, 2024
    Publication date: June 12, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Publication number: 20250194170
    Abstract: Disclosed are a semiconductor structure and a fabricating method thereof. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a first passivation layer, and a second passivation layer that are sequentially stacked; a through hole is disposed penetrating through the first passivation layer and the second passivation layer, and the through hole is filled with a semiconductor layer, where the semiconductor layer includes a P-type activation region and a first high-resistance region, and the P-type activation region is configured to deplete a 2DEG of a lower channel to implement an enhancement mode device; the first high-resistance region is located at an included angle formed by the P-type activation region and the barrier layer, so as to reduce a leakage current near the P-type activation region and improve a reliability of a device.
    Type: Application
    Filed: August 13, 2024
    Publication date: June 12, 2025
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai CHENG
  • Publication number: 20250194244
    Abstract: A three-dimensional structure with an FD-SOI transistor includes a handler wafer, a first device layer and a second device layer stacked in sequence from bottom to top. The first device layer includes a first SOI layer, a first FD-SOI transistor and a first back gate. The first SOI layer includes a first front side and a first back side. The first FD-SOI transistor is disposed on the first front side. The first back gate is disposed on the first back side. The second device layer includes a second SOI layer, a second FD-SOI transistor and a second back gate. The second SOI layer includes a second front side and a second back side. The second FD-SOI transistor is disposed on the second front side. The second back gate is disposed on the second back side.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 12, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Kai Cheng
  • Patent number: D1084092
    Type: Grant
    Filed: January 3, 2025
    Date of Patent: July 15, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Wen-Yo Lu, Matthew J. England, Chia-Song Liu, Tsung-Kai Cheng, Ming-Cheng Cheng, Oleksii Krasnoshchok, Oleksii Shekolian, Sergiy Aafanasov, Mikhail Donskoi, Chia-Wei Chan