Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.

Abstract: Provided are a semiconductor structure and manufacturing method thereof, the semiconductor comprising: a base, wherein the base comprises strip trenches arranged parallelly; and a heterojunction structure located on bottom walls and sidewalls of the strip trenches and on the base other than the strip trenches, wherein regions of the heterojunction structure located on the bottom walls and on the base other than the strip trenches are polarized regions, regions of the heterojunction structure on the sidewalls are non-polarized regions, and the polarized regions contain carriers; the heterojunction structure comprises a source region and a drain region respectively located at both ends of each of the strip trenches, and a gate region between the source region and the drain region; and the carriers between the source region and the drain region are confined to flow in each of the polarized regions.

Abstract: The present invention relates to a device and method for the treatment of trismus. The device comprises: a frame including two arms connected to a base portion; a first insert locatable in the frame, the first insert configured to cause the two arms to exert a first predetermined force in opposing outward directions relative to a central axis of the device; a second insert locatable in the frame in the same position as the first insert, the second insert configured to cause the two arms to exert a second predetermined force in opposing outward directions relative to the central axis of the device.

Abstract: Disclosed is a semiconductor structure. The semiconductor structure includes a support structure, and a first dielectric layer and a growth substrate sequentially formed on the support structure, where a gravity center of the support structure and a gravity center of the growth substrate are disposed in a staggered manner, so that the direct contact between the growth substrate and the graphite disk can be avoided, a centrifugal force on the growth substrate exerted by the graphite disk to the support structure can be transferred, thereby further ensuring a quality of the growth substrate, and significantly reducing a probability of cracking to ensure a crystal quality of a subsequent epitaxial layer. The support structure is formed at the bottom of the growth substrate, so that a mechanical strength of the semiconductor structure can be effectively improved, a stability can be enhanced, and a deformation of the semiconductor structure can be suppressed.

Abstract: Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.

Abstract: A light-emitting structure includes: a first region and a second region surrounding the first region. The first region includes a plurality of first light-emitting units, and the second region includes a plurality of second light-emitting units. An area of the first light-emitting unit is greater than an area of the second light-emitting unit. The area of the second light-emitting unit in the second region arranged on the edge is relatively small, which improves a doping rate of a light-emitting element in the second region, so that doping rates of the light-emitting element of the light-emitting structure in the first region and the second the area tend to be equal, thereby solving a problem of uneven light-emitting wavelengths in the first region and the second region when the light-emitting unit is prepared by epitaxy.

Abstract: Disclosed are a semiconductor structure and a method for preparing a semiconductor structure, a film bulk acoustic resonator and a method for preparing a film bulk acoustic resonator. The method for preparing a semiconductor structure according to the present application includes: growing a first nitride layer on a surface, including an active silicon layer, of a substrate, and selectively removing a partial area of the active silicon layer to form a hollow structure, so that the first nitride layer and the substrate are partially separated, and then a stress between the substrate and the first nitride layer is released. A crack of the semiconductor structure is reduced and quality of the semiconductor structure is improved while a thickness of the semiconductor structure is guaranteed.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes an N-type semiconductor layer provided on a substrate in a vertical direction, and at least one of multiple-quantum-well structure is formed on the N-type semiconductor layer in a horizontal direction, a P-type semiconductor layer is provided above the multiple-quantum-well structure and on at least part of sides of the multiple-quantum-well structure, each multiple-quantum-well structure includes a plurality of semiconductor layers sequentially stacked in the vertical direction and a multiple-quantum-well unit formed between each two adjacent semiconductor layers of the plurality of semiconductor layers, and the P-type semiconductor layer is in contact with each of the plurality of semiconductor layers of the multiple-quantum-well structure in the vertical direction. The method is used to manufacture the semiconductor structure.

Abstract: The present application provides a substrate and a manufacturing method therefor. The substrate includes a silicon substrate and a protective layer, the silicon substrate includes a middle part and an edge part, and a thickness of the middle part is greater than a thickness of the edge part. The middle part has a to-be-grown surface, and a crystal orientation of the to-be-grown surface is different from a crystal orientation of surface of the edge part. The protective layer covers the edge part and is configured to prevent defects in the edge part from extending to the middle part during high-temperature processing.

Abstract: A semiconductor structure includes: a substrate, a buffer layer and a multi-channel heterojunction layer which are disposed in a stacking manner, the multi-channel heterojunction layer including a first, a second, . . . , and an n-th heterojunction layers in a direction away from the substrate, where n?2, and each heterojunction layer includes a channel layer and a barrier layer; and an n-type heavily doped layer, which is disposed on a side wall of the multi-channel heterojunction layer, the n-type heavily doped layer being a multi-layer structure. The present disclosure provides the n-type heavily doped layer with the multi-layer structure, which may effectively reduce an ohmic contact resistance of a source region and a drain region.

Abstract: The embodiment of the present disclosure provides a semiconductor structure and a method for manufacturing thereof, the semiconductor structure includes a substrate and a channel structure at a side of the substrate, and the channel structure includes a first channel layer and a first barrier layer which are sequentially disposed at a side of the substrate; where the semiconductor structure includes a gate region, and a source region and a drain region at both sides of the gate region, the channel structure in the source region is provided with a first groove, and the channel structure in the drain region is provided with a second groove; and two N-type heavily doped layers are in the first groove and the second groove respectively, where a surface of the N-type heavily doped layers away from the substrate has a plurality of V-shaped pits.

Abstract: A semiconductor structure includes a substrate, an N+ type gallium nitride epitaxial layer, an N? type gallium nitride epitaxial layer and a first AlGaN layer which are sequentially disposed; a P-type gallium nitride epitaxial layer extending from a surface of a side, away from the substrate, of the first AlGaN layer into the N? type gallium nitride epitaxial layer; and a second AlGaN layer located on a side, away from the substrate, of the first AlGaN layer and the P-type gallium nitride epitaxial layer. According to technical solutions of the present disclosure, an enhancement mode device with a high threshold voltage can be realized and an on-resistance of the device can be reduced.

Abstract: A semiconductor structure includes a substrate, a channel layer and a barrier layer which are stacked sequentially, the channel layer and the barrier layer including a gate region, a source region located at one side of the gate region and a drain region located at another one side of the gate region; and a P-type semiconductor layer, located at least in the gate region and located at a side, away from the substrate, of the barrier layer; where the P-type semiconductor layer includes a non-activated layer, an N-type doped layer and an activated layer which are stacked sequentially, and the non-activated layer is located on a side, close to the substrate, of the P-type semiconductor layer.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; and a first semiconductor layer, a first stress releasing layer, an active layer and a second semiconductor layer that are sequentially stacked on the substrate from bottom to top; where conductive types of the first semiconductor layer and the second semiconductor layer are opposite, the first stress releasing layer comprises one or more periodic structures, each of the one or more periodic structures comprises a first group III nitride and a second group III nitride, and an In component content in the first group III nitride is different from an In component content in the second group III nitride. By the semiconductor structure provided in the present disclosure, an active layer with high In component content can be epitaxial grown while ensuring high crystal quality.

Abstract: Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, a passivation layer, and a cap layer stacked in sequence. The passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate through at least the passivation layer. A first electrode is arranged at least on the cap layer corresponding to the first groove; a second electrode is arranged in the second groove. A Schottky contact is formed between the first electrode and the cap layers, so that a direct contact area between the first electrode and the heterostructure layer may be avoided, a contradiction between the forward turn-on voltage and the reverse leakage of the Schottky diode may be balanced, and a leakage characteristic of the heterostructure layer in a high temperature environment may be suppressed.

Abstract: Disclosed are a semiconductor light-emitting device and a preparation method of the semiconductor light-emitting device. The preparation method of the semiconductor light-emitting device includes: forming a mask layer on a substrate, the mask layer is provided with a plurality of openings exposing the substrate; etching the substrate at each of the plurality of openings to form a first groove, and forming a first reflector in the first groove; epitaxially growing a light-emitting structure on the first reflector, and the light-emitting structure includes a first conductive type semiconductor layer, a multiple quantum well layer and a second conductive type semiconductor layer epitaxial grown in sequence; forming a second reflector in one side of the light-emitting structure away from the first reflector.

Abstract: Disclosed are a semiconductor structure and a method for preparing the same, relating to the field of semiconductor technologies. The semiconductor structure includes: a substrate; and a plurality of functional film layers stacked on the substrate, the plurality of functional film layers include a first semiconductor layer and a second semiconductor layer stacked with each other, the first semiconductor layer is arranged between the substrate and the second semiconductor layer. The first semiconductor layer includes a plurality of defect pits recessed toward the substrate, the defect pits are filled by the second semiconductor layer, and one side of the second semiconductor layer away from the first semiconductor layer is a plane. The semiconductor structure and the preparation method thereof provided in the present application solve the problem of vertical leakage in the semiconductor structure in the prior art.

Abstract: Disclosed is an enhancement-mode semiconductor device, comprising: a substrate; a p-type nitride semiconductor layer and an n-type nitride semiconductor layer formed on the substrate in sequence, the p-type nitride semiconductor layer having a first protruding structure at a gate region of the p-type nitride semiconductor layer; the n-type nitride semiconductor layer having a first through hole corresponding to the first protruding structure, exposing the gate region of the p-type nitride semiconductor layer; a channel layer conformally disposed on the n-type semiconductor layer and the first protruding structure; a barrier layer, the barrier layer being conformally disposed on the channel layer. The enhancement-mode semiconductor device has a simple structure, a good repeatability, and avoids impurities and defects brought to the channel layer and the barrier layer.

Abstract: A composite substrate includes a substrate, a high-resistance layer located on the substrate, the high-resistance layer comprising a first low-temperature aluminum nitride (AlN) layer, a high-temperature AlN layer and a second low-temperature AlN layer which are stacked in sequence, and a growth substrate located on a side, away from the substrate, of the high-resistance layer. Under the action of the first low-temperature AlN layer, a tensile stress on the high-temperature AlN layer may be reduced, to reduce a dislocation, and further improve a crystal quality of the high-temperature AlN layer and ensure resistivity of the high-temperature AlN layer; and an element of Al in the high-temperature AlN layer is prevented from diffusing into the growth substrate, to protect the crystal quality of the high-temperature AlN layer and improve a bonding effect between the high-resistance layer and the growth substrate. Thus, stability and reliability of the composite substrate are greatly improved.