Patents by Inventor Kai Cheng
Kai Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12713738Abstract: The present application provides an LED structure and a GaN-based substrate thereof, and a method for manufacturing a GaN-based substrate. The GaN-based substrate includes: a patterned base including a plurality of depressions and a plurality of protrusions; a metal Ga layer located at the plurality of depressions; and a second semiconductor layer located on the metal Ga layer and the plurality of protrusions exposed by the metal Ga layer, where a material for the second semiconductor layer is a GaN-based material. When the LED light-emitting structure is formed on the GaN-based substrate, light emitted by the LED light-emitting structure, after being reflected via the metal Ga layer, can emit from an upper surface or a side surface of the LED light-emitting structure, which reduces the light absorption and further improves the light-emitting efficiency of the LED light-emitting structure.Type: GrantFiled: November 11, 2020Date of Patent: August 18, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Weihua Liu, Kai Cheng
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Patent number: 12713977Abstract: The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the method, for the substrate, the first conductive type semiconductor layer, the light emitting layer and the second conductive type semiconductor layer distributed sequentially from bottom to top, the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in first predetermined regions are removed to form grooves. The second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer in second predetermined regions and third predetermined regions are retained. Layers retained in second predetermined regions form light emitting units arranged in an array. Various layers retained in third predetermined regions form connection posts, each of which connects adjacent light emitting units.Type: GrantFiled: July 16, 2020Date of Patent: August 18, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Zhuan Liu
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Publication number: 20260231569Abstract: A manufacturing method for a light emitting diode with a vertical structure includes: forming a metal atom layer on a substrate, the substrate being an n-type substrate; forming an n-type buffer layer on the metal atom layer; forming a light emitting structure on the n-type buffer layer, the light emitting structure including an n-type semiconductor layer, an active layer and a p-type semiconductor layer from bottom to top; disposing a p electrode on the light emitting structure; and disposing an n electrode on one side, away from the metal atom layer, of the substrate. The n-type substrate with conductivity is adopted, and the metal atom layer and the n-type buffer layer are sequentially formed on the n-type substrate, so that conductivity of a device with the vertical structure can be ensured, and stripping and bonding are not needed.Type: ApplicationFiled: March 25, 2026Publication date: August 6, 2026Applicant: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai CHENG
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Patent number: 12701844Abstract: Disclosed are a semiconductor light-emitting device and a preparation method for the semiconductor light-emitting device. The semiconductor light-emitting device having a red light sub-pixel region, a green light sub-pixel region, and a blue light sub-pixel region includes a substrate and a blue light epitaxial layer epitaxially grown on the substrate, and a green light epitaxial layer and a red light epitaxial layer continually grown on the green light sub-pixel region and the red light sub-pixel region, respectively, on the blue light epitaxial layer, the green light epitaxial layer and the red light epitaxial layer being distributed on the blue light epitaxial layer at an interval.Type: GrantFiled: April 27, 2023Date of Patent: August 4, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 12701827Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a silicon substrate having several through-silicon-vias therein; a first semiconductor layer located in each through-silicon-via and on the silicon substrate, an active layer located on the first semiconductor layer, and a second semiconductor layer located on the active layer, where a conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer, a material of the first semiconductor layer a group III nitride, a material of the active layer a group III nitride, and a material of the second semiconductor layer include a group III nitride.Type: GrantFiled: April 15, 2021Date of Patent: August 4, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Liyang Zhang
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Patent number: 12701849Abstract: Disclosed are a light emitting structure and a preparation method therefor. The method includes: forming a mask layer on a n-type substrate, disposing a plurality of openings in the mask layer; and forming a light emitting unit in each of the plurality of openings, including: forming a metal atomic layer in the opening; forming an n-type semiconductor layer on the metal atomic layer, and forming a light extraction structure on the n-type semiconductor layer; and sequentially forming an active layer and a p-type semiconductor layer on the n-type semiconductor layer and the light extraction structure. In this way, step of peeling off the substrate may be avoided. In addition, with a plurality of discrete light emitting structures formed on the same substrate, a step of cutting a device is avoided, and damage to the device can be prevented.Type: GrantFiled: February 27, 2023Date of Patent: August 4, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Publication number: 20260215337Abstract: An electronic device includes a substrate, a first organic portion, a first opening, a second organic portion, a second opening, a third organic portion and a first element. In a cross-section view, the first organic portion, the first opening, the second organic portion, the second opening and the third organic portion are disposed on the substrate and arranged in a first direction, the first opening is located between the first organic portion and the second organic portion, the second opening is located between the second organic portion and the third organic portion, the second organic portion is located between the first organic portion and the third organic portion, and a width of the first opening and a width of the second opening are less than a width of the second organic portion in the first direction. The first element is overlapped with the first opening.Type: ApplicationFiled: December 19, 2025Publication date: July 23, 2026Applicant: Innolux CorporationInventors: Jian-Jung Shih, Tsau-Hua Hsieh, Fang-Ying Lin, Kai Cheng
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Patent number: 12690218Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer arranged from bottom to up; and a P-type semiconductor layer located on a source region and a drain region of the etch stop layer.Type: GrantFiled: August 13, 2020Date of Patent: July 21, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Kai Cheng, Peng Xiang
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Patent number: 12690298Abstract: A light-emitting device and a method for manufacturing a light-emitting device are provided. The light-emitting device includes: a substrate, provided with at least one light guide channel through the substrate, wherein each of the at least one light guide channel comprises a first opening and a second opening opposite to the first opening, an area of a section of the second opening is greater than an area of a section of the first opening, the substrate comprises a first substrate and a second substrate stacked, and the second substrate is configured to control a direction of light output through the light guide channel; and a light-emitting structure, provided at a side of the substrate where the first opening is located, wherein the light-emitting structure comprises at least one light-emitting unit, each of the at least one light guide channel corresponds to at least one light-emitting unit.Type: GrantFiled: May 17, 2023Date of Patent: July 21, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Liyang Zhang, Kai Cheng
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Patent number: 12690221Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present application provides. The semiconductor structure includes a substrate and a heterojunction structure located on the substrate. The heterojunction structure includes a channel layer and a barrier layer located on the channel layer. The channel layer includes at least one n-type doped layer. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a heterojunction structure on the substrate, where forming the heterojunction structure includes: forming a channel layer on the substrate, doping the channel layer to form an n-type doped layer; forming a barrier layer on the channel layer; forming a gate electrode, a source electrode and a drain electrode, the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the grid electrode, separately.Type: GrantFiled: May 24, 2023Date of Patent: July 21, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 12690220Abstract: The present disclosure provides a semiconductor structure, including a substrate, a channel layer, a barrier layer, and a P-type semiconductor layer that are distributed from bottom to top, where the barrier layer includes an Al element, and a variation curve of a proportion of Al element in the barrier layer is continuous; where at an interface between the channel layer and the barrier layer, the proportion of Al element in the barrier layer is the same as the proportion of Al element in the channel layer; and at an interface between the barrier layer and the P-type semiconductor layer, the proportion of Al element in the barrier layer is the same as the proportion of Al element in the P-type semiconductor layer.Type: GrantFiled: October 20, 2023Date of Patent: July 21, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 12690301Abstract: Disclosed are a diode and a manufacturing method thereof. The diode includes: a first substrate, the first substrate being an N-type doped substrate with a doping concentration equal to or greater than 1×1018 cm?3; a metal atomic layer located on a first surface of the first substrate; an epitaxial structure located on the metal atomic layer; a first electrode located on the epitaxial structure; and a second electrode located on a second surface, opposite to the first surface, of the first substrate. The diode significantly reduces forward conduction voltage drop.Type: GrantFiled: March 1, 2023Date of Patent: July 21, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 12684867Abstract: Disclosed are a composite substrate and a method for manufacturing the same, and a semiconductor device structure. In this application, after a buffer layer and an epitaxial growth layer are sequentially formed on a support substrate, the epitaxial growth layer is bonded on a target substrate of which a surface has a bonding layer, and the support substrate and the buffer layer are removed to form the composite substrate at least including the target substrate, the bonding layer and the epitaxial growth layer which are stacked sequentially, the buffer layer has a periodic structure in which a first sublayer and a second sublayer are alternately arranged. In this application, the buffer layer is provided with the periodic structure, so that a stress may be adjusted, and crystal quality of the epitaxial growth layer may be significantly improved.Type: GrantFiled: April 24, 2023Date of Patent: July 14, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 12684928Abstract: Disclosed are a light-emitting chip, a manufacturing method thereof and an electronic device. The light-emitting chip includes a first substrate; and at least one reflector and a light-emitting pixel layer sequentially located on the first substrate. The light-emitting pixel layer includes at least one light-emitting pixel. The reflector is arranged corresponding to the light-emitting pixel. A first surface, close to the light-emitting pixel, of the reflector is a bowl-shaped surface. The bowl-shaped surface is concave in a direction close to the first substrate. The reflector is configured to reflect light emitted by a corresponding light-emitting pixel and adjust an emission direction and/or an emission angle of the light, so that the light exit rate of the light-emitting chip can be improved, and the light-emitting brightness of the light-emitting chip and electronic device can be further improved.Type: GrantFiled: June 30, 2023Date of Patent: July 14, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Liyang Zhang, Kai Cheng
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Patent number: 12684800Abstract: Disclosed are an enhancement-mode switching device and a preparation method therefor. The enhancement-mode switching device includes: a substrate; a channel structure; an n-type semiconductor layer covering a bottom wall of the trench; a p-type semiconductor layer arranged in a gate region; a gate electrode arranged on a side, away from the substrate, of the p-type semiconductor layer; a source electrode arranged in a source region; a drain electrode arranged in a drain region. In the gate region, the p-type semiconductor layer and n-type semiconductor layer are in contact with each other to form a space depletion region in the gate region, and the electronic channel between the source electrode and the drain electrode of the switching device is interrupted, so that the switching device may be effectively turned off under a gate bias voltage of zero, improving control capability of the gate electrode and reliability of the device.Type: GrantFiled: May 16, 2023Date of Patent: July 14, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventor: Kai Cheng
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Patent number: 12684880Abstract: Disclosed is an image sensor, comprising: at least one photosensitive unit, where the photosensitive unit includes a main photosensitive region and an auxiliary photosensitive region arranged at the periphery of the main photosensitive region, and a photosensitive component content of the main photosensitive region is different from a photosensitive component content of the auxiliary photosensitive region. The disclosure enlarges a wavelength range of sensible light of each the photosensitive unit by arranging the auxiliary photosensitive region at the periphery of the main photosensitive region of the photosensitive unit, where the photosensitive component content of the main photosensitive region is different from that of the auxiliary photosensitive region. Thereby more image details may be recorded to generate images with high dynamic range, which enables people to experience a visual effect close to a real environment.Type: GrantFiled: January 19, 2023Date of Patent: July 14, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Yuchao Chen, Kai Cheng
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Patent number: 12677448Abstract: Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.Type: GrantFiled: August 2, 2023Date of Patent: July 7, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Peng Xiang, Kai Cheng
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Publication number: 20260190407Abstract: A semiconductor structure includes a substrate, a channel layer, and a barrier layer that are stacked in sequence; multiple first P-type semiconductor layers, and multiple second P-type semiconductor layers. The channel layer and the barrier layer form a heterojunction. The heterojunction includes a gate region, and a source region and a drain region located on two sides of the gate region. The first P-type semiconductor layers are spaced apart along a first direction and located in the gate region, where the first direction is the extension direction of the gate region. The second P-type semiconductor layers are arranged along the first direction and located between the gate region and the drain region. The first P-type semiconductor layers and the second P-type semiconductor layers alternate along the first direction.Type: ApplicationFiled: June 19, 2025Publication date: July 2, 2026Inventors: Jiaqi HE, Kai CHENG
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Publication number: 20260190411Abstract: A semiconductor structure includes a substrate, a channel layer, a source N-type doped layer, a drain N-type doped layer, a barrier layer, a source metal layer, a first P-type semiconductor layer, a gate metal layer, a second P-type semiconductor layer, and a drain metal layer. The channel layer is disposed above the substrate. The side of the channel layer facing away from the substrate includes a source region, a drain region, and an intermediate region between the source region and the drain region. The side of the barrier layer facing away from the substrate includes a gate region. The source metal layer is disposed on the side of the source N-type doped layer facing away from the substrate. The first P-type semiconductor layer and the gate metal layer are stacked in sequence in the gate region.Type: ApplicationFiled: June 19, 2025Publication date: July 2, 2026Inventors: Jiaqi HE, Kai CHENG
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Patent number: 12672372Abstract: The present application provides a frontside-illuminated image sensor, including a substrate, a photosensitive unit, and a lens structure. The substrate has a plurality of charge storage regions; The photosensitive unit is above the substrate, and the photosensitive unit includes a plurality of photosensitive sub-units. Each photosensitive sub-unit includes a red photosensitive layer, a green photosensitive layer, and a blue photosensitive layer that are stacked. One photosensitive sub-unit is electrically connected with one charge storage region; the lens structure is on a side of the photosensitive unit away from the substrate.Type: GrantFiled: June 18, 2021Date of Patent: June 30, 2026Assignee: ENKRIS SEMICONDUCTOR, INC.Inventors: Yuchao Chen, Kai Cheng