Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a semiconductor substrate, a back barrier layer, a channel layer and an etch stop layer arranged from bottom to up; and a P-type semiconductor layer located on a source region and a drain region of the etch stop layer.

Abstract: A light-emitting device and a method for manufacturing a light-emitting device are provided. The light-emitting device includes: a substrate, provided with at least one light guide channel through the substrate, wherein each of the at least one light guide channel comprises a first opening and a second opening opposite to the first opening, an area of a section of the second opening is greater than an area of a section of the first opening, the substrate comprises a first substrate and a second substrate stacked, and the second substrate is configured to control a direction of light output through the light guide channel; and a light-emitting structure, provided at a side of the substrate where the first opening is located, wherein the light-emitting structure comprises at least one light-emitting unit, each of the at least one light guide channel corresponds to at least one light-emitting unit.

Abstract: A semiconductor structure and a manufacturing method thereof are provided in the present application provides. The semiconductor structure includes a substrate and a heterojunction structure located on the substrate. The heterojunction structure includes a channel layer and a barrier layer located on the channel layer. The channel layer includes at least one n-type doped layer. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a heterojunction structure on the substrate, where forming the heterojunction structure includes: forming a channel layer on the substrate, doping the channel layer to form an n-type doped layer; forming a barrier layer on the channel layer; forming a gate electrode, a source electrode and a drain electrode, the gate electrode is located on the heterojunction structure, and the source electrode and the drain electrode are located on two sides of the grid electrode, separately.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a channel layer, a barrier layer, and a P-type semiconductor layer that are distributed from bottom to top, where the barrier layer includes an Al element, and a variation curve of a proportion of Al element in the barrier layer is continuous; where at an interface between the channel layer and the barrier layer, the proportion of Al element in the barrier layer is the same as the proportion of Al element in the channel layer; and at an interface between the barrier layer and the P-type semiconductor layer, the proportion of Al element in the barrier layer is the same as the proportion of Al element in the P-type semiconductor layer.

Abstract: Disclosed are a diode and a manufacturing method thereof. The diode includes: a first substrate, the first substrate being an N-type doped substrate with a doping concentration equal to or greater than 1×1018 cm?3; a metal atomic layer located on a first surface of the first substrate; an epitaxial structure located on the metal atomic layer; a first electrode located on the epitaxial structure; and a second electrode located on a second surface, opposite to the first surface, of the first substrate. The diode significantly reduces forward conduction voltage drop.

Abstract: Disclosed are a composite substrate and a method for manufacturing the same, and a semiconductor device structure. In this application, after a buffer layer and an epitaxial growth layer are sequentially formed on a support substrate, the epitaxial growth layer is bonded on a target substrate of which a surface has a bonding layer, and the support substrate and the buffer layer are removed to form the composite substrate at least including the target substrate, the bonding layer and the epitaxial growth layer which are stacked sequentially, the buffer layer has a periodic structure in which a first sublayer and a second sublayer are alternately arranged. In this application, the buffer layer is provided with the periodic structure, so that a stress may be adjusted, and crystal quality of the epitaxial growth layer may be significantly improved.

Abstract: Disclosed are a light-emitting chip, a manufacturing method thereof and an electronic device. The light-emitting chip includes a first substrate; and at least one reflector and a light-emitting pixel layer sequentially located on the first substrate. The light-emitting pixel layer includes at least one light-emitting pixel. The reflector is arranged corresponding to the light-emitting pixel. A first surface, close to the light-emitting pixel, of the reflector is a bowl-shaped surface. The bowl-shaped surface is concave in a direction close to the first substrate. The reflector is configured to reflect light emitted by a corresponding light-emitting pixel and adjust an emission direction and/or an emission angle of the light, so that the light exit rate of the light-emitting chip can be improved, and the light-emitting brightness of the light-emitting chip and electronic device can be further improved.

Abstract: Disclosed are an enhancement-mode switching device and a preparation method therefor. The enhancement-mode switching device includes: a substrate; a channel structure; an n-type semiconductor layer covering a bottom wall of the trench; a p-type semiconductor layer arranged in a gate region; a gate electrode arranged on a side, away from the substrate, of the p-type semiconductor layer; a source electrode arranged in a source region; a drain electrode arranged in a drain region. In the gate region, the p-type semiconductor layer and n-type semiconductor layer are in contact with each other to form a space depletion region in the gate region, and the electronic channel between the source electrode and the drain electrode of the switching device is interrupted, so that the switching device may be effectively turned off under a gate bias voltage of zero, improving control capability of the gate electrode and reliability of the device.

Abstract: Disclosed is an image sensor, comprising: at least one photosensitive unit, where the photosensitive unit includes a main photosensitive region and an auxiliary photosensitive region arranged at the periphery of the main photosensitive region, and a photosensitive component content of the main photosensitive region is different from a photosensitive component content of the auxiliary photosensitive region. The disclosure enlarges a wavelength range of sensible light of each the photosensitive unit by arranging the auxiliary photosensitive region at the periphery of the main photosensitive region of the photosensitive unit, where the photosensitive component content of the main photosensitive region is different from that of the auxiliary photosensitive region. Thereby more image details may be recorded to generate images with high dynamic range, which enables people to experience a visual effect close to a real environment.

Abstract: Disclosed are a semiconductor structure and a preparation method thereof. The semiconductor structure includes a substrate, including a first region arranged at the center of the substrate and a second region arranged at the periphery of the first region; and a composite buffer layer arranged on the substrate, including a carbon-containing first buffer layer including at least one set of a first sub-buffer layer and a second sub-buffer layer stacked in layers; therein, a carbon concentration of the first sub-buffer layer arranged at the first region is higher than that arranged at the second region; and a carbon concentration of the second sub-buffer layer arranged at the first region is lower than that at arranged the second region. Therefore, uniformity of the carbon concentration of the composite buffer layer is improved to improve resistivity of the composite buffer layer, so as to increase breakdown voltage and improve device performance.

Abstract: A semiconductor structure includes a substrate, a channel layer, and a barrier layer that are stacked in sequence; multiple first P-type semiconductor layers, and multiple second P-type semiconductor layers. The channel layer and the barrier layer form a heterojunction. The heterojunction includes a gate region, and a source region and a drain region located on two sides of the gate region. The first P-type semiconductor layers are spaced apart along a first direction and located in the gate region, where the first direction is the extension direction of the gate region. The second P-type semiconductor layers are arranged along the first direction and located between the gate region and the drain region. The first P-type semiconductor layers and the second P-type semiconductor layers alternate along the first direction.

Abstract: A semiconductor structure includes a substrate, a channel layer, a source N-type doped layer, a drain N-type doped layer, a barrier layer, a source metal layer, a first P-type semiconductor layer, a gate metal layer, a second P-type semiconductor layer, and a drain metal layer. The channel layer is disposed above the substrate. The side of the channel layer facing away from the substrate includes a source region, a drain region, and an intermediate region between the source region and the drain region. The side of the barrier layer facing away from the substrate includes a gate region. The source metal layer is disposed on the side of the source N-type doped layer facing away from the substrate. The first P-type semiconductor layer and the gate metal layer are stacked in sequence in the gate region.

Abstract: An optical coupling structure includes an alignment layer, a growth substrate and an optical functional layer, the growth substrate being used for epitaxially manufacturing the optical functional layer, and the optical functional layer being aligned with a first through hole in the growth substrate; an optical fiber input end disposed in a second through hole in the alignment layer for improving stability of the optical fiber input end; and an embedding structure used to penetrate through the first and second through holes, which may not only clamp and fix the alignment layer and the growth substrate, effectively improving overall stability of the optical coupling structure, but also align the optical functional layer with the optical fiber input end, and therefore, light emitting from the optical functional layer directly enters the optical fiber input end through the first and second through holes, improving an optical coupling efficiency.

Abstract: The present application provides a frontside-illuminated image sensor, including a substrate, a photosensitive unit, and a lens structure. The substrate has a plurality of charge storage regions; The photosensitive unit is above the substrate, and the photosensitive unit includes a plurality of photosensitive sub-units. Each photosensitive sub-unit includes a red photosensitive layer, a green photosensitive layer, and a blue photosensitive layer that are stacked. One photosensitive sub-unit is electrically connected with one charge storage region; the lens structure is on a side of the photosensitive unit away from the substrate.

Abstract: This application provides an ultraviolet LED and a manufacturing method thereof. In the manufacturing method, an N-type transition layer is formed above an electron supply layer and/or a P-type transition layer is formed above a hole supply layer, materials of the electron supply layer and the hole supply layer include at least three elements: Al, Ga and N, and materials of the N-type transition layer and the P-type transition layer are GaN; an N electrode is formed on the N-type transition layer, and an ohmic contact is formed between the N-type transition layer and the N electrode; a P electrode is formed on the P-type transition layer, and an ohmic contact is formed between the P-type transition layer and the P electrode.

Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.

Abstract: Provided are a semiconductor structure and manufacturing method thereof, the semiconductor comprising: a base, wherein the base comprises strip trenches arranged parallelly; and a heterojunction structure located on bottom walls and sidewalls of the strip trenches and on the base other than the strip trenches, wherein regions of the heterojunction structure located on the bottom walls and on the base other than the strip trenches are polarized regions, regions of the heterojunction structure on the sidewalls are non-polarized regions, and the polarized regions contain carriers; the heterojunction structure comprises a source region and a drain region respectively located at both ends of each of the strip trenches, and a gate region between the source region and the drain region; and the carriers between the source region and the drain region are confined to flow in each of the polarized regions.

Abstract: The present invention relates to a device and method for the treatment of trismus. The device comprises: a frame including two arms connected to a base portion; a first insert locatable in the frame, the first insert configured to cause the two arms to exert a first predetermined force in opposing outward directions relative to a central axis of the device; a second insert locatable in the frame in the same position as the first insert, the second insert configured to cause the two arms to exert a second predetermined force in opposing outward directions relative to the central axis of the device.

Abstract: Disclosed is a semiconductor structure. The semiconductor structure includes a support structure, and a first dielectric layer and a growth substrate sequentially formed on the support structure, where a gravity center of the support structure and a gravity center of the growth substrate are disposed in a staggered manner, so that the direct contact between the growth substrate and the graphite disk can be avoided, a centrifugal force on the growth substrate exerted by the graphite disk to the support structure can be transferred, thereby further ensuring a quality of the growth substrate, and significantly reducing a probability of cracking to ensure a crystal quality of a subsequent epitaxial layer. The support structure is formed at the bottom of the growth substrate, so that a mechanical strength of the semiconductor structure can be effectively improved, a stability can be enhanced, and a deformation of the semiconductor structure can be suppressed.

Abstract: Disclosed are a semiconductor structure and a method for manufacturing a semiconductor structure, the method includes: forming a first transition layer, a protection layer and an active structure layer sequentially epitaxially on a side of a growth substrate, where a surface, away from the growth substrate, of the first transition layer is a two-dimensional flat surface; on a first plane, an orthographic projection of the active structure layer is at least partially covered by an orthographic projection of the protection layer, and the first plane is perpendicular to an arrangement direction of the protection layer and the active structure layer; detaching the growth substrate by a laser lift-off process, to make the epitaxial layer transferred to a transfer substrate; etching the first transition layer up to the protection layer, to make a surface, away from the active structure layer, of the protection layer to be a planarization surface.