Abstract: A manufacturing method of an electronic device including steps of: providing a substrate, wherein the substrate includes a bonding element, and the bonding element includes a first region and a second region separated from each other; providing an electronic unit, wherein the electronic unit includes an electronic element and an electrode electrically connected to the electronic element; transferring the electronic unit onto the substrate, wherein the electrode is stacked on the first region; and applying an energy beam to the second region so that the energy of the energy beam is transmitted from the second region to the first region by heat conduction, so as to bond the electrode to the first region. An electronic device made by the manufacturing method is also provided.

Abstract: A semiconductor structure comprises a substrate; a V-shaped groove layer, a V-shaped groove enlargement layer and a semiconductor epitaxial layer stacked from bottom to top; an insertion layer; and a first V-shaped groove arranged on a surface of the V-shaped groove layer close to the V-shaped groove enlargement layer; a second V-shaped groove arranged on a surface of the V-shaped groove enlargement layer close to the semiconductor epitaxial layer, where a size of the second V-shaped groove is greater than a size of the first V-shaped groove In the present disclosure, a lateral epitaxy effect of the V-shaped groove enlargement layer and the semiconductor epitaxial layer is realized for two times, which makes dislocation fully bend, effectively improving crystal quality.

Abstract: A semiconductor structure includes: a substrate, a channel layer, a barrier layer and a P-type semiconductor layer sequentially stacked in a first direction. The P-type semiconductor layer includes a high-resistance passivation region and an activation region, and the high-resistance passivation region is located on a side, away from the substrate, of the activation region. When a semiconductor device is in an off state, the activation region of the P-type semiconductor layer may deplete 2DEG at the channel to realize an enhancement-mode device. The high-resistance passivation region is passivated to form a high-resistance structure, which may reduce a gate leakage current in the off state and improve power characteristics of the semiconductor device.

Abstract: Disclosed are a composite substrate, an epitaxial wafer, and a semiconductor device. The composite substrate includes: a support substrate layer; a first alumina layer disposed on the support substrate layer; and a sapphire substrate layer disposed on the first alumina layer. The first alumina layer may increase a bonding force between the sapphire substrate layer and the support substrate layer and release a stress between the sapphire substrate layer and the support substrate layer. Meanwhile, the existence of the first alumina layer may improve a breakdown voltage of a material without increasing a thickness of the sapphire substrate layer.

Abstract: A semiconductor structure includes a substrate, a nucleation layer, a buffer layer and a heterojunction structure layer that are stacked sequentially. The nucleation layer includes a first nucleation layer and a second nucleation layer. The first nucleation layer includes a plurality of strip-shaped structures, a strip-shaped trench is formed between two adjacent strip-shaped structures in the plurality of strip-shaped structures, and an extension direction of the strip-shaped trench is parallel to a plane where the substrate is located. The strip-shaped trench and the first nucleation layer are covered by the second nucleation layer, and an ion penetration capability of the second nucleation layer is higher than an ion penetration capability of the first nucleation layer. The technical solutions of the present disclosure may improve a linearity of a device.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing thereof, and the semiconductor structure includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer; a P-type layer in a gate region and on a side of the barrier layer away from the substrate; and a cap layer on a side of the P-type layer away from the substrate, where a surface of the cap layer away from the substrate includes pits. According to the present disclosure the pits provided in the cap layer can replace the contact interface between the cap layer and the gate electrode from the C crystal plane to the non-C crystal plane.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing thereof, and the semiconductor structure includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer; a P-type layer in a gate region and on a side of the barrier layer away from the substrate; an insertion layer on a side of the P-type layer away from the substrate; and a cap layer on a side of the insertion layer away from the substrate; where a surface of the cap layer away from the substrate includes pits which can change crystal planes of a contact interface between the cap layer and a gate electrode; and the insertion layer and the cap layer are made of different materials.

Abstract: A light-emitting structure includes: a first region and a second region, where the second region surrounds the first region; the first region includes a plurality of first light-emitting units, and the second region includes a plurality of second light-emitting units; and a distance between adjacent first light-emitting units is less than a distance between adjacent second light-emitting units in a circumferential direction or a radial direction of the light-emitting structure. The distance between the adjacent second light-emitting units of the second region arranged on the edge is large, which improves a doping rate of a light-emitting element in the second region, so that doping rates of the light-emitting element in the first region and the second region tend to be equal, thereby solving a problem of uneven light-emitting wavelengths in the first region and the second region when the light-emitting unit is prepared by epitaxy.

Abstract: The present disclosure provides a semiconductor structure including a substrate, an insulation layer on the substrate; a protrusion structure protruding out of the insulation layer, where the protrusion structure includes a source region, a drain region and a channel region between whereof; the protrusion structure includes a first through n-th heterojunction structure sequentially stacked along a direction away from the substrate, where n is an integer greater than or equal to 2; the first heterojunction structure includes a first channel layer and a first barrier layer, and the n-th heterojunction structure includes an n-th channel layer and an n-th barrier layer, and at least one of the first barrier layer, through the n-th barrier layer is doped with an N-type element; the source electrode on the source region, the drain electrode on the drain region, and the gate structure on the channel region.

Abstract: A manufacturing method of a vertical cavity surface emitting laser is provided. The vertical cavity surface emitting laser includes a first reflector, a first semiconductor layer, an active layer, a second semiconductor layer, an oxide layer, and a second reflector sequentially stacked. The conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer. The oxide layer includes a light transmitting region and a light shielding region, and the light shielding region surrounds the light transmitting region. The manufacturing method includes planarizing a first contact surface of the first semiconductor layer and the first reflector, and/or a second contact surface of the second semiconductor layer and the second reflector.

Abstract: Disclosed are a composite substrate and a manufacturing method therefor, and a semiconductor device structure. The composite substrate includes a substrate and a plurality of strengthening structures, where the plurality of strengthening structures are disposed within the substrate at intervals, and a material of the plurality of strengthening structures is a poly-crystal material or an amorphous material. The composite substrate provided by the present disclosure may withstand stress, constrain deformation, and prevent extension of a dislocation by providing the strengthening structures inside the substrate, thereby enhancing mechanical strength of the composite substrate. By filling the poly-crystal material or the amorphous material in the single-crystal substrate, the extension of the dislocation in single-crystal substrate may be prevented, so that the strength of substrate may be improved, and probability of fragmentation of the composite substrate may be reduced.

Abstract: Disclosed are a composite substrate, a manufacturing method thereof and a semiconductor device. The composite substrate includes a first substrate, a bonding layer, and a second substrate which are stacked sequentially, where the first substrate comprises a plurality of protruding structures disposed on a side close to the second substrate, and a groove formed between at least two protruding structures of the plurality of protruding structures. The composite substrate provided by the present disclosure, by setting a bonding layer, a bond strength between the first substrate and the second substrate may be improved, and a mechanical strength of the composite substrate is enhanced. By setting the groove, a stress transmitted from the second substrate to the first substrate may be attenuated, so as to improve the mechanical strength of the composite substrate and avoid a plastic deformation in a subsequent epitaxial process.

Abstract: A semiconductor device includes: a substrate, a first support structure, a first nanowire heterojunction, a source, a drain, and a ring-shaped gate. The substrate includes a first region, and a second region and a third region located on respective sides of the first region; the first support structure is located at least on the second region and the third region; the first nanowire heterojunction includes a first gate section corresponding to the first region, a first source section corresponding to the second region, and a first drain section corresponding to the third region; the first source section and the first drain section are located on the first support structure. The source is located on the first source section, the drain is located on the first drain section, and the ring-shaped gate wraps the first gate section.

Abstract: An epitaxial structure of a light-emitting device and a manufacturing method thereof are provided. The epitaxial structure of the light-emitting device includes a first semiconductor layer, an active region and a second semiconductor layer sequentially stacked; where the active region includes at least one group of a barrier layer and a quantum well layer which are stacked, a surface of the quantum well layer away from the first semiconductor layer has a first roughness, a surface of the barrier layer away from the first semiconductor layer has a second roughness, and the first roughness is greater than the second roughness.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes: providing a patterned substrate, where the patterned substrate includes columnar structures; providing second inhibition layers, where the second inhibition layers are respectively located between two adjacent columnar structures of the columnar structures, and upper surfaces of the columnar structures are exposed; providing a light-emitting structure layer on the upper surface of each of the columnar structures; and removing the patterned substrate, to obtain holes at regions corresponding to the columnar structures, where the holes are respectively located between two adjacent second inhibition layers of the second inhibition layers, and the holes correspond to the light-emitting structure layers respectively. The manufacturing method provided by the present disclosure optimizes the manufacturing process and realizes full-color LED.

Abstract: A composite substrate includes a supporting substrate layer, a buried layer and a growth substrate layer stacked in sequence. The buried layer is provided with a plurality of grooves at least partially penetrating the buried layer, the supporting substrate layer includes a charge trapping region beneath the plurality of grooves, and on a plane where the supporting substrate layer is located, shapes of projections of the charge trapping region and a corresponding groove overlap. The charge trapping region is arranged on the supporting substrate layer, and the charge trapping region is used to deplete charges of the supporting substrate layer, so as to increase resistivity of the composite substrate, reducing an impact of crosstalk; and the buried layer is provided with grooves, which may attenuate a stress transmitted from the growth substrate layer to the supporting substrate layer, so as to enhance a mechanical strength of the composite substrate.

Abstract: Disclosed are a semiconductor structure and a manufacturing method for the semiconductor structure. The semiconductor structure includes a light-emitting structure; a light control layer disposed on a side of the light-emitting structure, including a plurality of light control regions regularly arranged and a substrate structure located between the plurality of light control regions; where the plurality of light control regions include a wavelength conversion structure, and the wavelength conversion structure includes a quantum dot and a porous structure adsorbed with the quantum dot. In the present disclosure, the plurality of light control regions and the substrate structure are provided to ensure uniform light output, good directionality, high light extraction rate, and avoidance of light crosstalk in each light control region. The porous structure is utilized to adsorb the quantum dot and achieve a full color display, thereby improving resolution, simplifying a manufacturing process and reducing costs.

Abstract: The present disclosure provides enhancement mode switching devices and manufacturing methods thereof. The enhancement mode switching device includes a substrate; a channel structure including a channel layer and a barrier layer. The channel layer is provided on the substrate, and the barrier layer is provided on a side of the channel layer far away from the substrate. A side of the channel structure far away from the substrate is provided with a trench in a gate region, and the trench penetrates through the barrier layer and a part of the channel layer. The enhancement mode switching device includes a p-type semiconductor layer in the gate region, a gate electrode on a side of the p-type semiconductor layer far away from the substrate, a source electrode in the source region, and a drain electrode in the drain region. At least part of the p-type semiconductor layer is in the trench.

Abstract: Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure includes an N-type substrate provided with a plurality of first grooves on a first surface; and an epitaxial layer located on the first surface, where the epitaxial layer includes an N-type drift region, a P-type well region, an N-type source region and a JFET region, where a surface of a side, away from the N-type substrate, of the epitaxial layer is provided with a plurality of second grooves, the second grooves are in one-to-one correspondence with the first grooves, and extension directions of the second grooves and the first grooves are parallel to a length direction of a channel of the semiconductor structure. A channel width may be effectively increased, thereby increasing a channel conduction area and reducing channel resistance and interface state density; and the epitaxial layer may be prevented from being damaged by etching.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a base and a mask layer on the base; where the mask layer includes a window exposing the base, and the window comprises an opening end, an area for an orthographic projection of the opening end on a plane of the base is smaller than an area for an orthographic projection of the window on the plane of the base. According to embodiments of the present disclosure, a base with a mask layer is used as a substrate for epitaxially growing GaN-based materials. The opening in the mask layer has an inward sidewall in the direction from the base to the opening end. Using the inward sidewall of the window, the dislocations of the epitaxially grown GaN-based material terminate at the sidewall of the window.