INTERCONNECT STRUCTURE
An interconnect structure is formed in a semiconductor device. The interconnect structure includes a dielectric layer disposed over a substrate. The dielectric layer includes a region and a plurality of protrusions. The protrusions are distributed in the region. A metal layer is disposed on the dielectric layer. Tops of the protrusions are exposed with respect to the metal layer. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.
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This application claims the priority benefit of Chinese patent application serial no. 202110047135.3, filed on Jan. 14, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION Field of the InventionThe invention relates to a semiconductor manufacturing technique, and particularly to an interconnect structure in a semiconductor device.
Description of Related ArtSemiconductor devices all include interconnect structures for connecting related devices in an integrated circuit to complete the desired circuit architecture.
As generally known, the desired circuit architecture may be manufactured into a semiconductor device structure using a semiconductor manufacturing technique to achieve integrated circuit manufacture. For example, the structure of a conductor device may include a plurality of transistor elements. These transistors need to be connected to other devices using interconnect structures.
In other words, after a variety of devices are manufactured on the substrate, they require interconnect structures to provide electrical connections between the devices. For example, there are regions with high device density and regions with low device density on the substrate. The linewidth of the interconnect structures in the low device density regions is greater. The linewidth of the interconnect structures in the high device density regions is relatively less.
The material of the interconnect structures is generally a copper material, for example. In manufacture, a patterned dielectric layer is generally formed first, which is also generally referred to as an inter-layer dielectric layer. The pattern of the dielectric layer provides a recessed pattern for forming the interconnect structures. Next, the copper material covers the pattern of the dielectric layer, and then a polishing process is used to remove the copper material on the dielectric layer, stopping at the dielectric layer. The remaining copper material is filled in the recessed pattern of the dielectric layer to complete the manufacture of the interconnect structures.
When the polishing process is performed on the substrate, the polishing pressure sustained by the copper material in the high device density regions and the low device density regions is different according to the density of the recessed pattern of the dielectric layer. The copper in the low device density regions has a greater linewidth, thus readily causing dishing, and therefore reducing the quality of the interconnect structures.
For the manufacture of interconnect structures, a technique of reducing dishing phenomenon in low device density regions or large linewidth regions still needs further research and development.
SUMMARY OF THE INVENTIONThe invention provides a manufacture of an interconnect structure, wherein, for example, dishing phenomenon to an interconnect in a low device density region or a large linewidth region may be effectively reduced to maintain the design thickness of the interconnect.
In an embodiment, the invention provides an interconnect structure formed in a semiconductor device. The interconnect structure includes a dielectric layer disposed over the substrate, wherein the dielectric layer includes a region and a plurality of protrusions, and the plurality of protrusions are distributed in the region. A metal layer is disposed on the dielectric layer. Tops of the plurality of protrusions are exposed with respect to the metal layer. Any straight path crossing through a central region of the region is always intersected with a portion of the plurality of protrusions.
In an embodiment, regarding the interconnect structure, the plurality of protrusions are regularly distributed to form a plurality of rows in a first direction, and the plurality of protrusions in adjacent two of the plurality of rows are mutually shifted in the first direction.
In an embodiment, regarding the interconnect structure, each of the plurality of protrusions includes: a straight bar extended in the first direction; a first extension bar at a first side of the straight bar; and a second extension bar at a second side of the straight bar. The first extension bar and the second extension bar are extended in directions opposite to each other and intersected with the first direction.
In an embodiment, regarding the interconnect structure, each of the plurality of protrusions includes: a first straight bar extended in the first direction; a first extension bar at a first end of the first straight bar; and a second extension bar at a second end of the first straight bar. The first extension bar and the second extension bar are extended in a second direction, and the second direction is intersected with the first direction.
In an embodiment, the interconnect structure further includes: a second straight bar extended in the second direction; a third extension bar at a first end of the second straight bar; and a fourth extension bar at a second end of the second straight bar. The third extension bar and the fourth extension bar are extended in the first direction.
In an embodiment, regarding the interconnect structure, each of the plurality of protrusions includes: a first straight bar extended in the first direction; and a second straight bar extended in the second direction at a side of the first straight bar. The first direction is intersected with the second direction.
In an embodiment, regarding the interconnect structure, each of the plurality of protrusions includes: a first straight bar extended in the first direction; and a second straight bar extended in the second direction and intersected with the first straight bar to form a cross structure.
In an embodiment, the interconnect structure further includes: a first bent structure disposed at a first end of the first straight bar; and a second bent structure disposed at a second end of the first straight bar.
In an embodiment, regarding the interconnect structure, the first end and the second end are extended in the second direction with respect to the first straight bar.
In an embodiment, regarding the interconnect structure, the plurality of protrusions include: a bent strip extended in a direction, wherein a bent shape of the bent strip is a pulse signal shape; a straight bar extended in the direction and adjacent to the bent strip. A plurality of extension bars are at a left side and a right side of the straight bar, perpendicular to the direction, and alternately arranged corresponding to a concave folding region of the bent strip.
In an embodiment, the invention further provides an interconnect structure formed in a semiconductor device. The interconnect structure includes a metal layer disposed on a substrate. The metal layer has a region and a plurality of slots, and the plurality of slots are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the plurality of slots.
In an embodiment, regarding the interconnect structure, the plurality of slots are regularly distributed to form a plurality of rows in a first direction, and the plurality of slots in adjacent two of the plurality of rows are mutually shifted in the first direction.
In an embodiment, regarding the interconnect structure, each of the plurality of slots includes: a straight slot extended in the first direction; a first extension bar at a first side of the straight slot; and a second extension bar at a second side of the straight slot. The first extension bar and the second extension bar are extended in directions opposite to each other and intersected with the first direction.
In an embodiment, regarding the interconnect structure, each of the plurality of slots includes: a first straight slot extended in the first direction; a first extension bar at a first end of the first straight slot; and a second extension bar at a second end of the first straight slot. The first extension bar and the second extension bar are extended in a second direction, and the second direction is intersected with the first direction.
In an embodiment, the interconnect structure further includes: a second straight slot extended in the second direction; a third extension bar at a first end of the second straight slot; and a fourth extension bar at a second end of the second straight slot. The third extension bar and the fourth extension bar are extended in the first direction.
In an embodiment, regarding the interconnect structure, each of the plurality of slots includes: a first straight slot extended in the first direction; and a second straight slot extended in the second direction at a side of the first straight slot. The first direction is intersected with the second direction.
In an embodiment, regarding the interconnect structure, each of the plurality of slots includes: a first straight slot extended in the first direction; and a second straight slot extended in the second direction and intersected with the first straight slot to form a cross structure.
In an embodiment, the interconnect structure further includes: a first bent structure disposed at a first end of the first straight slot; and a second bent structure disposed at a second end of the first straight slot.
In an embodiment, regarding the interconnect structure, the first end and the second end are extended in the second direction with respect to the first straight slot.
In an embodiment, regarding the interconnect structure, the plurality of slots include: a bent slot extended in a direction, wherein a bent shape of the bent slot is a pulse signal shape; a straight slot extended in the direction and adjacent to the bent slot; and a plurality of extension bars at a left side and a right side of the straight slot, perpendicular to the direction, and alternately arranged corresponding to a concave folding region of the bent slot.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
The invention relates to an interconnect structure including a region belonging to, for example, a low device density region or a large linewidth region. In this region, the manufacturing process of the interconnect structure eliminates a dishing path using the protrusions of the dielectric layer, so as to reduce dishing of the interconnect structure caused by a metal polishing process.
A plurality of embodiments are provided below to illustrate the invention, but the invention is not limited to the plurality of embodiments provided. The plurality of embodiments may also be combined with each other.
Before proposing the interconnect structure, the invention first looks into the manufacturing process of the interconnect structure to facilitate understanding of the mechanism of the dishing path that may occur in the portion of the interconnect structure belonging to, for example, a low device density region or a large linewidth region. Thereafter, the invention proposes to effectively eliminate the dishing phenomenon of the interconnect structure.
The following first describes the dishing situation of the interconnect structure explored in the invention.
Referring to
The dielectric layer 50 matches the interconnect structure to be formed, and includes some patterns 52 and 52a. The patterns 52 correspond to the interconnect structure in the high device density region. The dielectric layer 50 also includes a region 30 with a large metal linewidth and a region 40 with a large metal linewidth including vias. The patterns 52a of the dielectric layer 50 are provided for forming via structures. Next, a metal layer 54 for forming an interconnect structure is formed on the dielectric layer 50. The metal layer 54 also completely fills the recessed structure provided by the patterns 52 and 52a on the dielectric layer 50.
As observed, the metal layer 54 is dished in the region 30 and the region 40, thus affecting the quality of the interconnect structure. The reason why the metal layer 54 is dished in the region 30 and the region 40 is due to the lack of a dielectric layer structure that may resist the polishing pressure in the region 30 and the region 40 with respect to the region 20.
Referring to
Referring to
Referring to
The invention further improves the design of the protrusions 60, so that there are protrusions blocking in all 360 degrees of the polishing path, so as to eliminate the forming of the dishing path.
In
The metal layer 200 is disposed on the dielectric layer, and the tops of the protrusions 102 of the dielectric layer are exposed with respect to the metal layer 200. Here, for the structure of the metal layer 200, the protrusions 102 form slots of the metal layer 200. That is, the protrusions 102 form the slots of the metal layer 200 at the same time.
For the region 100 in which dishing is to be prevented, the protrusions 102 are arranged so that any straight path 152 crossing a central region 150 of the region 100 is intersected with a portion of the protrusions 102. Here, the central region 150 is defined with respect to the region 100. In other words, if the straight path 152 is in the corner of the region 100, such as four corners, the straight path 152 may not come in contact with the protrusions 102, but whenever the straight path 152 crosses the region 100, the protrusions 102 are present for blocking. As a result, the dishing path 62 exemplified in
The plurality of protrusions 102 are, for example, a plurality of rows 104a and 104b regularly distributed in one direction 160. One protrusion 102 may also be regarded as one structural unit 110. The protrusions 102 in two adjacent rows 104a and 104b of these rows are mutually shifted in the direction 160.
In an embodiment, each of the protrusions 102 includes a straight bar 102a extended in the direction 160. An extension bar 102b is at a side of the straight bar 102a and another extension bar 102c is at another side of the straight bar. The extension bar 102b and the extension bar 102c are extended in directions 162 opposite to each other and intersected with the direction 160, for example. For another example, the extension bar 102b and the extension bar 102c are the two ends of the straight bar 102a. In this way, the straight bar 102a and the two extension bars 102b and 102c form one protrusion 102. The two directions 160 and 162 are intersected, such as perpendicularly intersected.
To enable the straight path 152 to cross the protrusions 102 and eliminate the design of the dishing path, these protrusions 102 may be designed in other different ways under the same principle.
In an embodiment, the linewidth of the protrusions 102, that is, the widths of the straight bar 102a and the extension bars 102b and 102c, may be adjusted.
Referring to
The arrangement of the extension bar 102b and the extension bar 102c of
In an embodiment, referring to
Referring to
Referring to
The invention provides a plurality of embodiments of the protrusions on the electrical connection layer, but the invention is not limited to the embodiments mentioned, and the embodiments may also be suitably combined with each other.
As also described above, the protrusions are a portion of the dielectric layer for forming the interconnect structure after the polishing process. However, from the perspective of the metal layer of the interconnect structure, the protrusions are exposed during the polishing process, so the protrusions form slots at the metal layer. Therefore, the shape of the slots is the same as the shape of the protrusions. The shape of the slots is the same as the previous protrusions, and the geometric structure of the slots is not repeated herein.
The protrusions of the dielectric layer of the invention may effectively reduce the dishing phenomenon caused by the polishing process for a large-area metal layer, wherein the dishing path may be effectively interrupted by the protrusions. In terms of the structure of the metal layer, the protrusions of the dielectric layer form corresponding slots at the metal layer.
Lastly, it should be noted that the above embodiments are only used to describe the technical solution of the invention instead of limiting it. Although the invention has been described in detail with reference to each embodiment above, those having ordinary skill in the art should understand that the technical solution recited in each embodiment above may still be modified, or some or all of the technical features thereof may be equivalently replaced. These modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solution of each embodiment of the invention.
Claims
1. An interconnect structure formed in a semiconductor device, comprising:
- a dielectric layer disposed over the substrate, wherein the dielectric layer comprises a region and a plurality of protrusions, and the plurality of protrusions are distributed in the region; and
- a metal layer disposed on the dielectric layer, wherein tops of the plurality of protrusions are exposed with respect to the metal layer,
- wherein any straight path crossing through a central region of the region is always intersected with a portion of the plurality of protrusions.
2. The interconnect structure of claim 1, wherein the plurality of protrusions are regularly distributed to form a plurality of rows in a first direction, and the plurality of protrusions in adjacent two of the plurality of rows are mutually shifted in the first direction.
3. The interconnect structure of claim 2, wherein each of the plurality of protrusions comprises:
- a straight bar extended in the first direction;
- a first extension bar at a first side of the straight bar; and
- a second extension bar at a second side of the straight bar,
- wherein the first extension bar and the second extension bar are extended in directions opposite to each other and intersected with the first direction.
4. The interconnect structure of claim 2, wherein each of the plurality of protrusions comprises:
- a first straight bar extended in the first direction;
- a first extension bar at a first end of the first straight bar; and
- a second extension bar at a second end of the first straight bar,
- wherein the first extension bar and the second extension bar are extended in a second direction, and the second direction is intersected with the first direction.
5. The interconnect structure of claim 4, further comprising:
- a second straight bar extended in the second direction;
- a third extension bar at a first end of the second straight bar; and
- a fourth extension bar at a second end of the second straight bar,
- wherein the third extension bar and the fourth extension bar are extended in the first direction.
6. The interconnect structure of claim 2, wherein each of the plurality of protrusions comprises:
- a first straight bar extended in the first direction; and
- a second straight bar extended in the second direction at a side of the first straight bar,
- wherein the first direction is intersected with the second direction.
7. The interconnect structure of claim 2, wherein each of the plurality of protrusions comprises:
- a first straight bar extended in the first direction; and
- a second straight bar extended in the second direction and intersected with the first straight bar to form a cross structure.
8. The interconnect structure of claim 7, further comprising:
- a first bent structure disposed at a first end of the first straight bar; and
- a second bent structure disposed at a second end of the first straight bar.
9. The interconnect structure of claim 8, wherein the first end and the second end are extended in the second direction with respect to the first straight bar.
10. The interconnect structure of claim 1, wherein the plurality of protrusions comprise:
- a bent strip extended in a direction, wherein a bent shape of the bent strip is a pulse signal shape;
- a straight bar extended in the direction and adjacent to the bent strip; and
- a plurality of extension bars, at a left side and a right side of the straight bar, perpendicular to the direction, and alternately arranged corresponding to a concave folding region of the bent strip.
11. An interconnect structure formed in a semiconductor device, comprising:
- a metal layer disposed on the substrate, wherein the metal layer has a region and a plurality of slots, and the plurality of slots are distributed in the region,
- wherein any straight path crossing through a central region of the region is always intersected with a portion of the plurality of slots.
12. The interconnect structure of claim 11, wherein the plurality of slots are regularly distributed to form a plurality of rows in a first direction, and the plurality of slots in adjacent two of the plurality of rows are mutually shifted in the first direction.
13. The interconnect structure of claim 12, wherein each of the plurality of slots comprises:
- a straight slot extended in the first direction;
- a first extension bar at a first side of the straight slot; and
- a second extension bar at a second side of the straight slot,
- wherein the first extension bar and the second extension bar are extended in directions opposite to each other and intersected with the first direction.
14. The interconnect structure of claim 12, wherein each of the plurality of slots comprises:
- a first straight slot extended in the first direction;
- a first extension bar at a first end of the first straight slot; and
- a second extension bar at a second end of the first straight slot,
- wherein the first extension bar and the second extension bar are extended in a second direction, and the second direction is intersected with the first direction.
15. The interconnect structure of claim 14, further comprising:
- a second straight slot extended in the second direction;
- a third extension bar at a first end of the second straight slot; and
- a fourth extension bar at a second end of the second straight slot,
- wherein the third extension bar and the fourth extension bar are extended in the first direction.
16. The interconnect structure of claim 12, wherein each of the plurality of slots comprises:
- a first straight slot extended in the first direction; and
- a second straight slot extended in the second direction at a side of the first straight slot,
- wherein the first direction is intersected with the second direction.
17. The interconnect structure of claim 12, wherein each of the plurality of slots comprises:
- a first straight slot extended in the first direction; and
- a second straight slot extended in the second direction and intersected with the first straight slot to form a cross structure.
18. The interconnect structure of claim 17, further comprising:
- a first bent structure disposed at a first end of the first straight slot; and
- a second bent structure disposed at a second end of the first straight slot.
19. The interconnect structure of claim 18, wherein the first end and the second end are extended in the second direction with respect to the first straight slot.
20. The interconnect structure of claim 11, wherein the plurality of slots comprise:
- a bent slot extended in a direction, wherein a bent shape of the bent slot is a pulse signal shape;
- a straight slot extended in the direction and adjacent to the bent slot; and
- a plurality of extension bars, at a left side and a right side of the straight slot, perpendicular to the direction, and alternately arranged corresponding to a concave folding region of the bent slot.
Type: Application
Filed: Feb 3, 2021
Publication Date: Jul 14, 2022
Applicant: United Microelectronics Corp. (Hsinchu)
Inventors: To-Wen Tsao (Tainan City), Ching-Chang Hsu (Tainan City)
Application Number: 17/166,577