OPEN LOOP PROCESS AND TEMPERATURE INDEPENDENT BIAS CIRCUIT FOR STACKED DEVICE AMPLIFIERS
An open loop process and temperature independent bias circuit for stacked device amplifiers is disclosed herein. In one or more embodiments, a method for biasing a stacked high-voltage signal amplifier with a voltage divider bias module comprises generating, by the voltage divider bias module from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation. The method further comprises biasing, a plurality of devices of the stacked high-voltage signal amplifier, with the control voltage biases.
This application claims priority to U.S. Provisional Patent Application No. 63/163,647, filed Mar. 19, 2021, which is incorporated by reference herein in its entirety.
FIELDThe present disclosure relates to bias circuits. In particular, the present disclosure relates to an open loop process and temperature independent bias circuit for stacked device amplifiers.
BACKGROUNDCurrently, there are various approaches to biasing stacked device amplifiers, which are known both academically and commercially. Both “open loop” bias circuit designs (e.g., refer to the conventional amplifiers 100, 200 shown in
In light of the foregoing, there is a need for an improved design for a bias circuit for stacked amplifier devices.
SUMMARYThe present disclosure relates to methods, systems, and apparatuses for an open loop process and temperature independent bias circuit for stacked device amplifiers. In one or more embodiments, a method for biasing a stacked high-voltage signal amplifier with a voltage divider bias module comprises generating, by the voltage divider bias module from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation. The method further comprises biasing, a plurality of devices of the stacked high-voltage signal amplifier, with the control voltage biases.
In one or more embodiments, the voltage divider bias module comprises a plurality of temperature-dependent resistive cells connected together in series and sharing a common direct current (DC). In at least one embodiment, each of the temperature-dependent resistive cells comprises a diode-connected device connected to a resistor in series. In at least one embodiment, the diode-connected device is a transistor or other three-terminal amplifying device. In some embodiments, the transistor is a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor.
In at least one embodiment, the method further comprises inputting, into the voltage divider bias module, the power supply voltage (VDD).
In one or more embodiments, the offset voltage term (Vtemp) is equal to a base-to-emitter voltage (Vbe) or a gate-to-source voltage (Vgs) for each of the devices of the stacked high-voltage signal amplifier.
In at least one embodiment, the stacked high-voltage signal amplifier comprises a plurality of unit element amplifier cells that are stacked such that the unit element amplifier cells share a common DC current (Idc). In some embodiments, the unit element amplifier cells are connected together in a cascode configuration.
In one or more embodiments, the stacked high-voltage signal amplifier comprises at least one stage.
In at least one embodiment, each unit element amplifier cell comprises a transistor or other three-terminal amplifying device. In some embodiments, the transistor is a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor.
In one or more embodiments, the devices in the stacked high-voltage signal amplifier comprise a same temperature coefficient of a threshold voltage as devices in the voltage divider bias module. In some embodiments, the devices in the stacked high-voltage signal amplifier are of a same type with a same current density as devices in the voltage divider bias module.
In at least one embodiment, the method further comprises setting, by a bias current reference, a common DC current (Idc) flowing through the stacked high-voltage signal amplifier. In some embodiments, the bias current reference is a variable bias current reference.
In one or more embodiments, a method for biasing a stacked high-voltage signal amplifier with a voltage divider bias module comprises generating, by the voltage divider bias module from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation. The method further comprises receiving, by a voltage buffer module, the control voltage biases. Also, the method comprises generating, by the voltage buffer module, a low impedance output from a high impedance input. In addition, the method comprises outputting, by the voltage buffer module, the control voltage biases. Further, the method comprises biasing, a plurality of devices of the stacked high-voltage signal amplifier, with the control voltage biases.
In at least one embodiment, the voltage buffer module comprises a plurality of unity-gain buffers. In some embodiments, the unity-gain buffers are operational amplifiers (op-amps). In one or more embodiments, the op-amps are configured in a voltage follower configuration.
In one or more embodiments, the voltage buffer module comprises a voltage follower module cascaded with a level shifter module. In some embodiments, the voltage follower module and the level shifter module comprise devices that are scaled such that an additional offset voltage term (Vtemp) generated by the voltage follower module is canceled out by the level shifter module.
In at least one embodiment, a method for generating equal division of a voltage with a voltage divider module comprises generating, by the voltage divider module from the voltage, a plurality of divider voltages, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the voltage, and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation.
In one or more embodiments, the method further comprises receiving, by a voltage buffer module, the divider voltages. Also, the method comprises generating, by the voltage buffer module, a low impedance output from a high impedance input. Further, the method comprises outputting, by the voltage buffer module, the divider voltages.
In at least one embodiment, the voltage divider module comprises a plurality of temperature-dependent resistive cells connected together in series and sharing a common direct current (DC). In one or more embodiments, each of the temperature-dependent resistive cells comprises a diode-connected device connected to a resistor in series.
In one or more embodiments, a system for biasing a stacked high-voltage signal amplifier with a voltage divider bias module comprises the voltage divider bias module to generate, from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation. The system further comprises a plurality of devices of the stacked high-voltage signal amplifier to bias with the control voltage biases.
In at least one embodiment, the system is implemented within an integrated circuit (IC) chip.
In one or more embodiments, a system for biasing a stacked high-voltage signal amplifier with a voltage divider bias module comprises the voltage divider bias module to generate, from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation. The system further comprises a voltage buffer module to receive the control voltage biases, to generate a low impedance output from a high impedance input, and to output the control voltage biases. Further, the system comprises a plurality of devices of the stacked high-voltage signal amplifier to bias with the control voltage biases.
In at least one embodiment, a system for generating equal division of a voltage with a voltage divider module comprises the voltage divider module to generate, from the voltage, a plurality of divider voltages, which comprise a plurality of voltage references plus an offset voltage term (Vtemp). In one or more embodiments, the plurality of voltage references are each proportional to a division of the voltage, and the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation.
The features, functions, and advantages can be achieved independently in various embodiments of the present disclosure or may be combined in yet other embodiments.
These and other features, aspects, and advantages of the present disclosure will become better understood with regard to the following description, appended claims, and accompanying drawings where:
The methods and apparatuses disclosed herein provide operative systems for an open loop process and temperature independent bias circuit for stacked device amplifiers. In one or more embodiments, the system of the present disclosure provides a temperature independent bias circuit that creates biasing references for a stacked device amplifier intended for high supply voltage systems. In particular, the approach utilizes a resistive divider that creates a voltage reference, which is then mirrored in a manner that is intrinsically temperature compensated and biases the stacked device amplifier in a manner that divides the power supply evenly across each stacked device. The evenly divided power supply voltage across the amplifier devices stays constant, while the DC bias current (Ibias) of the amplifier may be adjusted. The disclosed bias circuit does not utilize any feedback, and is therefore inherently stable.
As previously mentioned above, currently, there are various approaches to biasing stacked device amplifiers, which are known both academically and commercially. “Open loop” bias circuit designs (e.g., refer to the conventional amplifiers 100, 200 of
The system of the present disclosure provides a bias circuit intended for amplifiers that employ stacked transistor devices for high voltage supply systems. The disclosed bias circuit provides a reference that biases the stacked device amplifier in such a way that the high voltage supply is divided evenly across the output of each individual transistor device of the amplifier, thereby ensuring device reliability. Moreover, the disclosed bias circuit is independent of temperature variation, thereby ensuring constant performance. Lastly, the disclosed bias circuit is “open loop”, meaning no feedback is employed with corresponding stability concerns.
The system of the present disclosure provides a unique approach of creating a voltage divider reference and device current mirror configuration that mirrors the voltage divider reference in a manner such that the amplifier is biased so that the voltage supply is evenly divided across the amplifier stacked devices. The novel approach to mirroring the bias reference ensures the temperature dependent device offset voltage term (Vtemp) (e.g., a base-to-emitter voltage (Vbe) or gate-to-source voltage (Vgs)) is cancelled. The open loop nature of the bias circuit allows the amplifier to draw as much current as needed during an increase in output power, thereby improving output power and efficiency.
In the following description, numerous details are set forth in order to provide a more thorough description of the system. It will be apparent, however, to one skilled in the art, that the disclosed system may be practiced without these specific details. In the other instances, well known features have not been described in detail, so as not to unnecessarily obscure the system.
Embodiments of the present disclosure may be described herein in terms of functional and/or logical components and various processing steps. It should be appreciated that such components may be realized by any number of hardware, software, and/or firmware components configured to perform the specified functions. For example, an embodiment of the present disclosure may employ various integrated circuit components (e.g., memory elements, digital signal processing elements, logic elements, look-up tables, or the like), which may carry out a variety of functions under the control of one or more processors, microprocessors, or other control devices. In addition, those skilled in the art will appreciate that embodiments of the present disclosure may be practiced in conjunction with other components, and that the systems described herein are merely example embodiments of the present disclosure.
For the sake of brevity, conventional techniques and components related to bias circuits, and other functional aspects of the overall system may not be described in detail herein. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent example functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in one or more embodiments of the present disclosure.
The second stage amplifier (stage 2) utilizes a current-shared stacked-device architecture, in which a high voltage supply (Vs) is divided across each device 110a, 110b, 110c, 110d. The power supply voltage (Vs) (e.g., 24 volts) is divided across the drain-to-source of each device 110a, 110b, 110c, 110d to alleviate voltage breakdown of the device 110a, 110b, 110c, 110d. The second stage amplifier (stage 2) shares a common DC current through the stacked devices 110a, 110b, 110c, 110d (i.e. referred to as “current sharing”). The radio frequency (RF) power combining networks (i.e. interstage power dividing network 120 and output matching/combining network 130) create the input and output RF signal of the second stage amplifier (stage 2).
The DC gate bias of the second stage amplifier (stage 2) is set by a series resistive divider (e.g., achieved via a resistive divider network comprising R1, R2, R3, R4, and R5 resistors) of the supply voltage (VS). The value of the resistors R1, R2, R3, R4, and R5 in the resistive divider network can be designed such that the generated gate biases create an even division of the power supply voltage (VS) across the devices 110a, 110b, 110c, 110d, thereby insuring reliability of the devices 110a, 110b, 110c, 110d from the high power supply voltage (VS).
The voltage division stability of the resistive divider network (e.g., comprising R1, R2, R3, R4, and R5 resistors) can be improved by implementing an active bias network (refer to 150 of
Similar to the second stage amplifier (stage 2) of
It should be noted that although the conventional amplifier designs shown in
The stacked high-voltage signal amplifier 320 of
The stacked high-voltage signal amplifier 320 comprises a plurality of unit element amplifier cells 330 that are stacked together such that they share a common direct current (DC) current (Idc). The unit element amplifier cells 330 are connected together in a cascode configuration. It should be noted that the term “cascode” is defined herein as and used throughout to mean “a plurality of units with a first unit having the following plurality of units connected on top of the first unit in a ‘stacked’ succession.” Each unit element amplifier cell 330 of the voltage divider bias module 320 comprises a device, such as a transistor (e.g., a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor) or other three-terminal amplifying device.
Referring to
Referring to
In addition, it follows that that when the devices of temperature-dependent resistive cells 910a, 910b, 910c, 910d, 910e of the voltage bias module 310 and the devices of in the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320 are implemented as BJTs, an offset voltage term (Vtemp) (which will be discussed in more detail below) is equal to the base-to-emitter voltage (Vbe) of the devices of the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320. And, when the devices of temperature-dependent resistive cells 910a, 910b, 910c, 910d, 910e of the voltage bias module 310 and the devices of in the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320 are implemented as CMOS transistors, the offset voltage term (Vtemp) is equal to the gate-to-source voltage (Vgs) of the devices of the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320.
Referring to
During operation of the system 300 of
The control voltage biases outputted from the voltage divider bias module 310 then respectively bias the gate/base of the devices in the unit element amplifier cells 330 of stacked high-voltage signal amplifier 320 in such a manner that the gate-to-source voltage (Vgs) (or base-to-emitter voltage (Vbe)), as dependent on technology and is proportional to temperature (as is Vtemp), is cancelled. The net effect is that the stacked devices of the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320 have an evenly divided power supply voltage across each device drain-to-source voltage (Vds) (or collector-to-emitter voltage (Vce)), and the stacked devices' performance is independent of temperature, in contrast to the conventional amplifiers (e.g., refer to the amplifiers 100, 200 of
Lastly, the bias current of the stacked high-voltage signal amplifier 320 may be varied (i.e. vary Idc), and the temperature independence of the devices of the stacked high-voltage signal amplifier 320 is maintained as long as the voltage divider bias module's 310 offset voltage term (Vtemp) is varied proportionally to the offset voltage term (Vtemp) of the stacked high-voltage signal amplifier 320 and cancels out accordingly.
In one or more embodiments, the voltage buffer module 560 comprises a plurality of unity-gain buffers. In at least one embodiment, operational amplifiers (op-amps) 570 may be employed for the unity-gain buffers. In one or more embodiments, the op-amps 570 are configured in the voltage buffer module 560 in a voltage follower configuration. If the design of the unity-gain buffers is correctly designed to be temperature independent, then the same temperature independence of the stacked high-voltage signal amplifier's 320 output voltage across the devices is maintained, similar to the system 300 of
During operation of the system 500 of
Then, the unity-gain buffers of the voltage buffer module 560 receive the plurality of control voltage biases. The unity-gain buffers of the voltage buffer module 560 generate a low impedance output from a high impedance input. Then, the unity-gain buffers of the voltage buffer module 560 output the plurality of control voltage biases.
The control voltage biases outputted from the voltage buffer module 560 then respectively bias the gate/base of the devices in the unit element amplifier cells 330 of stacked high-voltage signal amplifier 320 in such a manner that the gate-to-source voltage (Vgs) (or base-to-emitter voltage (Vbe)), as dependent on technology and is proportional to temperature (as is Vtemp), is cancelled. The net effect is that the stacked devices of the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320 have an evenly divided power supply voltage across each device drain-to-source voltage (Vds) (or collector-to-emitter voltage (Vce)), and the stacked devices' performance is independent of temperature.
Similar to the functional operation of the voltage buffer module 560 of the system 500 of
During operation of the system 600 of
Then, the voltage buffer module 660 receives the plurality of control voltage biases. The voltage buffer module 660 generates a low impedance output from a high impedance input. Then, the voltage buffer module 660 outputs the plurality of control voltage biases.
The control voltage biases outputted from the voltage buffer module 660 then respectively bias the gate/base of the devices in the unit element amplifier cells 330 of stacked high-voltage signal amplifier 320 such that the gate-to-source voltage (Vgs) (or base-to-emitter voltage (Vbe)), as dependent on technology and is proportional to temperature (as is Vtemp), is cancelled. The net effect is that the stacked devices of the unit element amplifier cells 330 of the stacked high-voltage signal amplifier 320 have an evenly divided power supply voltage across each device drain-to-source voltage (Vds) (or collector-to-emitter voltage (Vce)), and the stacked devices' performance is independent of temperature.
A voltage buffer module receives the control voltage biases 750. The voltage buffer module then generates a low impedance output from a high impedance input 760. The voltage buffer module then outputs the control voltage biases 770. Then, a plurality of devices of the stacked high-voltage signal amplifier is biased with the control voltage biases 780. Then, the method 700 ends 790.
In particular,
Referring to
In one or more embodiments, the voltage bias divider module 310 of
In particular,
The disclosed circuit comprising the bias circuit 1400 of
Although particular embodiments have been shown and described, it should be understood that the above discussion is not intended to limit the scope of these embodiments. While embodiments and variations of the many aspects of the invention have been disclosed and described herein, such disclosure is provided for purposes of explanation and illustration only. Thus, various changes and modifications may be made without departing from the scope of the claims.
Where methods described above indicate certain events occurring in certain order, those of ordinary skill in the art having the benefit of this disclosure would recognize that the ordering may be modified and that such modifications are in accordance with the variations of the present disclosure. Additionally, parts of methods may be performed concurrently in a parallel process when possible, as well as performed sequentially. In addition, more steps or less steps of the methods may be performed.
Accordingly, embodiments are intended to exemplify alternatives, modifications, and equivalents that may fall within the scope of the claims.
Although certain illustrative embodiments and methods have been disclosed herein, it can be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods can be made without departing from the true spirit and scope of this disclosure. Many other examples exist, each differing from others in matters of detail only. Accordingly, it is intended that this disclosure be limited only to the extent required by the appended claims and the rules and principles of applicable law.
Claims
1. A method for biasing a stacked high-voltage signal amplifier with a voltage divider bias module, the method comprising:
- generating, by the voltage divider bias module from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp),
- wherein the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation; and
- biasing, a plurality of devices of the stacked high-voltage signal amplifier, with the control voltage biases.
2. The method of claim 1, wherein the voltage divider bias module comprises a plurality of temperature-dependent resistive cells connected together in series and sharing a common direct current (DC), and
- wherein each of the temperature-dependent resistive cells comprises a diode-connected device connected to a resistor in series.
3. The method of claim 2, wherein the diode-connected device is one of a transistor or other three-terminal amplifying device.
4. The method of claim 3, wherein the transistor is one of a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor.
5. The method of claim 1, wherein the method further comprises inputting, into the voltage divider bias module, the power supply voltage (VDD).
6. The method of claim 1, wherein the offset voltage term (Vtemp) is equal to one of a base-to-emitter voltage (Vbe) or a gate-to-source voltage (Vgs) for each of the devices of the stacked high-voltage signal amplifier.
7. The method of claim 1, wherein the stacked high-voltage signal amplifier comprises a plurality of unit element amplifier cells that are stacked such that the unit element amplifier cells share a common DC current (Idc).
8. The method of claim 7, wherein the unit element amplifier cells are connected together in a cascode configuration.
9. The method of claim 1, wherein the stacked high-voltage signal amplifier comprises at least one stage.
10. The method of claim 7, wherein each unit element amplifier cell comprises one of a transistor or other three-terminal amplifying device.
11. The method of claim 10, wherein the transistor is one of a bipolar junction transistor (BJT) or a complementary metal-oxide semiconductor (CMOS) transistor.
12. The method of claim 1, wherein the devices in the stacked high-voltage signal amplifier comprise a same temperature coefficient of a threshold voltage as devices in the voltage divider bias module.
13. The method of claim 1, wherein the devices in the stacked high-voltage signal amplifier are of a same type with a same current density as devices in the voltage divider bias module.
14. The method of claim 1, wherein the method further comprises setting, by a bias current reference, a common DC current (Idc) flowing through the stacked high-voltage signal amplifier.
15. The method of claim 14, wherein the bias current reference is a variable bias current reference.
16. A method for biasing a stacked high-voltage signal amplifier with a voltage divider bias module, the method comprising:
- generating, by the voltage divider bias module from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp),
- wherein the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation;
- receiving, by a voltage buffer module, the control voltage biases;
- generating, by the voltage buffer module, a low impedance output from a high impedance input;
- outputting, by the voltage buffer module, the control voltage biases; and
- biasing, a plurality of devices of the stacked high-voltage signal amplifier, with the control voltage biases.
17. The method of claim 16, wherein the voltage buffer module comprises a plurality of unity-gain buffers.
18. The method of claim 17, wherein the unity-gain buffers are operational amplifiers (op-amps).
19. The method of claim 18, wherein the op-amps are configured in a voltage follower configuration.
20. The method of claim 16, wherein the voltage buffer module comprises a voltage follower module cascaded with a level shifter module.
21. The method of claim 20, wherein the voltage follower module and the level shifter module comprise devices that are scaled such that an additional offset voltage term (Vtemp) generated by the voltage follower module is canceled out by the level shifter module.
22. A method for generating equal division of a voltage with a voltage divider module, the method comprising:
- generating, by the voltage divider module from the voltage, a plurality of divider voltages, which comprise a plurality of voltage references plus an offset voltage term (Vtemp),
- wherein the plurality of voltage references are each proportional to a division of the voltage, and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation.
23. The method of claim 22, wherein the method further comprises:
- receiving, by a voltage buffer module, the divider voltages;
- generating, by the voltage buffer module, a low impedance output from a high impedance input; and
- outputting, by the voltage buffer module, the divider voltages.
24. The method of claim 22, wherein the voltage divider module comprises a plurality of temperature-dependent resistive cells connected together in series and sharing a common direct current (DC), and
- wherein each of the temperature-dependent resistive cells comprises a diode-connected device connected to a resistor in series.
25. A system for biasing a stacked high-voltage signal amplifier with a voltage divider bias module, the system comprising:
- the voltage divider bias module to generate, from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp),
- wherein the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation; and
- a plurality of devices of the stacked high-voltage signal amplifier to bias with the control voltage biases.
26. The system of claim 25, wherein the system is implemented within an integrated circuit (IC) chip.
27. A system for biasing a stacked high-voltage signal amplifier with a voltage divider bias module, the system comprising:
- the voltage divider bias module to generate, from a power supply voltage (VDD), a plurality of control voltage biases, which comprise a plurality of voltage references plus an offset voltage term (Vtemp),
- wherein the plurality of voltage references are each proportional to a division of the power supply voltage (VDD), and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation;
- a voltage buffer module to receive the control voltage biases, to generate a low impedance output from a high impedance input, and to output the control voltage biases; and
- a plurality of devices of the stacked high-voltage signal amplifier to bias with the control voltage biases.
28. A system for generating equal division of a voltage with a voltage divider module, the system comprising:
- the voltage divider module to generate, from the voltage, a plurality of divider voltages, which comprise a plurality of voltage references plus an offset voltage term (Vtemp),
- wherein the plurality of voltage references are each proportional to a division of the voltage, and wherein the offset voltage term (Vtemp) is proportional to temperature and is a function of process variation.
Type: Application
Filed: Mar 15, 2022
Publication Date: Sep 22, 2022
Inventors: Chris M. Thomas (Playa Vista, CA), Brian K. Kormanyos (Edmonds, WA)
Application Number: 17/695,639