SEMICONDUCTOR DEVICE COMPRISING A MOSFET HAVING A RESURF REGION AND HIGHER PEAK IMPURITY CONCENTRATION DIFFUSION REGION IN THE RESURF REGION
Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.
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This application is a Divisional of U.S. patent application Ser. No. 17/075,032 filed Oct. 20, 2020, which claims benefit of priority to Japanese Patent Application No. 2019-234187 filed Dec. 25, 2019, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION Field of the InventionThe present disclosure relates to a semiconductor device including a metal oxide semiconductor field effect transistor (MOSFET).
Description of the Background ArtAn integrated circuit (IC) for power control, which is mainly used for driving a gate of a semiconductor device for electric power, typically includes a low-side circuit that operates using a ground (GND) potential as a reference potential, and a high-side circuit that operates using, for example, a potential such as a floating potential, different from the GND potential as a reference potential, and a level shift circuit that transmits a signal between the low-side circuit and the high-side circuit.
There is known a technique in which a low-side circuit region and a high-side circuit region are separated by a reduced surface field (RESURF) region to form a MOSFET constituting a level shift circuit in the RESURF region (e.g., refer to JP 3917211 B2). This MOSFET needs to maintain breakdown voltage equivalent to that of the RESURF region. There is also known a condition of the RESURF region, in which a value of the product of a vertical depth (thickness) t [cm] and an impurity concentration N[cm−3] of the RESURF region is limited to enable the RESURF region to maintain high breakdown voltage by being completely depleted when breakdown voltage is maintained (e.g., refer to U.S. Pat. No. 4,292,642 and Philips Journal of Research Vol. 35 No. 1 1980). According to Philips Journal of Research, a condition, N×t<6.9×1011 cm−2 (hereinafter, this condition is referred to as a “RESURF condition”) needs to be satisfied.
Although an IC including a low-side circuit and a high-side circuit requires a power supply for driving each of the low-side circuit and the high-side circuit, there is known a system in which a bootstrap circuit is provided in the IC as a power supply for the high-side circuit. There is also known a technique using a MOSFET formed in a RESURF region, as a high breakdown voltage element in this bootstrap circuit (e.g., refer to JP 5488256 B2).
As described above, the semiconductor device including the RESURF region needs to maintain high breakdown voltage by completely depleting the RESURF region when breakdown voltage is maintained, so that an impurity concentration of the RESURF region is limited. This hinders reduction in on-resistance of the MOSFET formed in the RESURF region. Increasing a length of the RESURF region formed with the MOSFET enables improving breakdown voltage performance of the MOSFET, but accordingly the on-resistance of the MOSFET increases. That is, the MOSFET formed in the RESURF region has a trade-off relationship between the improvement of breakdown voltage performance and the reduction in on-resistance.
SUMMARYThe present disclosure is made to solve the above problems, and an object thereof is to improve the trade-off between the improvement of breakdown voltage performance and the reduction in on-resistance of the MOSFET formed in the RESURF region.
A semiconductor device according to the present disclosure includes: a semiconductor substrate formed with a first region of a first conductivity type; a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other; a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and a MOSFET using the second region as a drift layer. The MOSFET includes: a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region; a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region; a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region. An end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit.
The semiconductor device according to the present disclosure allows on-resistance of the MOSFET to be reduced by the seventh region, and improves the breakdown voltage performance by dispersing a location where an electric field is concentrated into the third region and the seventh region. This enables improving the trade-off between the improvement of breakdown voltage performance of the MOSFET formed in the RESURF region and the reduction in on-resistance.
These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings.
The semiconductor device according to the first preferred embodiment is formed using a semiconductor substrate 100 of the P-type, formed with a P-type diffusion layer 1 as a first region. The semiconductor substrate 100 is formed with respective regions described below, and in the following description, a P-type region of the semiconductor substrate 100 that remains other than these formed regions is referred to as the “P-type diffusion layer 1”. Here, although the semiconductor substrate 100 is made of silicon (Si), a wide band gap semiconductor made of silicon carbide (SiC), gallium nitride (GaN), or the like may be used. A semiconductor device using the wide band gap semiconductor is superior in operation at high voltage, large current, and high temperature to a conventional semiconductor device using silicon.
The semiconductor substrate 100 includes a surface portion formed with an N-type diffusion layer 3 as a second region. Although not illustrated in
The N-type diffusion layer 3 is provided in at least its inner bottom portion (close to the high-side circuit) with an N-type buried diffusion layer 2 having a higher peak concentration of impurities than that of the N-type diffusion layer 3, as a third region. The N-type buried diffusion layer 2 achieves not only an effect of suppressing vertical parasitic operation of elements in the high-side circuit, but also an effect of preventing operation of the elements in the high-side circuit from being adversely affected by allowing a depletion layer in the N-type diffusion layer 3 to extend into the high-side circuit when the breakdown voltage is maintained.
The semiconductor device according to the first preferred embodiment includes a lateral high breakdown voltage N-channel MOSFET having the N-type diffusion layer 3 as a drift layer. Structure of the MOSFET will be described below.
The N-type diffusion layer 3 includes a surface portion formed with an N-type diffusion layer 4 as a fourth region and a P-type diffusion layer 6 as a fifth region. The N-type diffusion layer 4 has a higher peak concentration of impurities than the N-type diffusion layer 3 and serves as a drain region of the MOSFET. The P-type diffusion layer 6 includes a surface portion formed with an N-type diffusion layer 7 as a sixth region and a P-type diffusion layer 8 having a higher peak concentration of impurities than the P-type diffusion layer 6. The N-type diffusion layer 7 serves as a source region of the MOSFET. The P-type diffusion layer 6 serves as a back gate of the MOSFET, and the P-type diffusion layer 8 serves as a contact region for electrically connecting the P-type diffusion layer 6 and a back gate electrode 24 described later.
The N-type diffusion layer 3 has a surface between the N-type diffusion layer 4 and the P-type diffusion layer 6 (i.e., between the N-type diffusion layer 4 and the N-type diffusion layer 7), and a surface inside of the N-type diffusion layer 4, the surfaces each being formed with a thermal oxide film 9. The thermal oxide film 9 between the N-type diffusion layer 4 and the P-type diffusion layer 6 serves as a first thermal oxide film, and the thermal oxide film 9 inside the N-type diffusion layer 4 serves as a second thermal oxide film.
The N-type diffusion layer 3 includes a surface portion below the thermal oxide film 9 between the N-type diffusion layer 4 and the P-type diffusion layer 6, the surface portion being formed with an N-type diffusion layer 14 having a higher peak concentration of impurities than the N-type diffusion layer 3, as a seventh region. The N-type diffusion layer 14 does not satisfy the RESURF condition. That is, when the N-type diffusion layer 14 has an impurity concentration indicated as N [cm−3] and a depth indicated as t [cm], a relationship, N×t>6.9×1011 cm−2, is satisfied. The N-type diffusion layer 14 has an outer end portion, located closer to the low-side circuit than an outer end portion of the N-type buried diffusion layer 2. That is, the N-type diffusion layer 14 extends outward of the N-type buried diffusion layer 2. Although the N-type diffusion layer 14 may be in contact with the N-type buried diffusion layer 2, the N-type diffusion layer 14 is here housed in the N-type diffusion layer 3, and the N-type diffusion layer 14 and the N-type buried diffusion layer 2 are separated from each other. Although the N-type diffusion layer 14 is formed overlapping the N-type diffusion layer 4 in
Below the thermal oxide film 9 inside the N-type diffusion layer 4, an N-type diffusion layer 5 is formed as an eighth region to prevent field inversion. This N-type diffusion layer 5 may be eliminated.
The thermal oxide film 9 between the N-type diffusion layer 4 and the P-type diffusion layer 6 has an inner end portion covered with a polysilicon layer 10 as a first polysilicon layer. The thermal oxide film 9 has an outer end portion covered with a polysilicon layer 11 as a second polysilicon layer. The polysilicon layer 11 extends from the end portion on the outside of the thermal oxide film 9 between the N-type diffusion layer 4 and the P-type diffusion layer 6 to above the N-type diffusion layer 7 to cover surfaces of the N-type diffusion layer 3 and the P-type diffusion layer 6 in a region between the thermal oxide film 9 and the N-type diffusion layer 7.
The semiconductor substrate 100 has a surface formed with an insulating film 12. On the insulating film 12, a reference potential electrode 20 for fixing a potential of the P-type diffusion layer 1 to a reference potential, and a gate electrode 21, a source electrode 23, a drain electrode 22, and a back gate electrode 24 of the MOSFET, are each formed partially embedded in the insulating film 12. The reference potential electrode 20 is connected to the P-type diffusion layer 1. The gate electrode 21 is provided on the polysilicon layer 11 and faces a surface of the P-type diffusion layer 8 in a region between the N-type diffusion layer 7 and the N-type diffusion layer 3. During an ON operation of the MOSFET, a channel is formed in the P-type diffusion layer 8 below the gate electrode 21. The source electrode 23 is connected to the N-type diffusion layer 7 serving as the source region of the MOSFET. The drain electrode 22 is connected to the N-type diffusion layer 4 serving as the drain region of the MOSFET, and partly reaches an upper surface of the polysilicon layer 10. The back gate electrode 24 is connected to the P-type diffusion layer 8, and is electrically connected to the P-type diffusion layer 6 serving as a back gate through the P-type diffusion layer 8.
The semiconductor device according to the first preferred embodiment has characteristics in which the N-type buried diffusion layer 2 and the N-type diffusion layer 14 are provided, and the N-type diffusion layer 14 has the outer end portion (close to the low side circuit), located closer to the low-side circuit than the outer end portion of the N-type buried diffusion layer 2. Hereinafter, effects obtained by the characteristics will be described below.
The conventional semiconductor device has a structure without the N-type buried diffusion layer 2 and the N-type diffusion layer 14, as illustrated in
For example, when the semiconductor device of
For example, when the semiconductor device of
In contrast, the semiconductor device according to the first preferred embodiment is configured such that both of the N-type buried diffusion layer 2 and the N-type diffusion layer 14 are formed in the N-type diffusion layer 3. In this case, the N-type diffusion layer 14 reduces the on-resistance of the MOSFET, and electric field concentration occurs in both the N-type buried diffusion layer 2 and the N-type diffusion layer 14. Thus, locations where the electric field concentration occurs are dispersed to improve the breakdown voltage performance of the MOSFET. As a result, the trade-off between the breakdown voltage performance and the on-resistance is improved as compared with the semiconductor devices of
However, when the N-type diffusion layer 14 has a short length, the electric field is not remarkably concentrated in the N-type diffusion layer 14. Thus, the electric field is not dispersed into the N-type buried diffusion layer 2 and the N-type diffusion layer 14 to increase strength of the electric field generated in the N-type buried diffusion layer 2, so that the above effect cannot be sufficiently obtained. For this reason, the semiconductor device of the first preferred embodiment is configured such that the N-type diffusion layer 14 is increased in length to allow the outer end portion of the N-type diffusion layer 14 to be located outside the outer end portion of the N-type buried diffusion layer 2, thereby allowing the electric field to be also concentrated in the N-type diffusion layer 14. The breakdown voltage performance is most improved in the first embodiment under conditions where the N-type buried diffusion layer 2 has a maximum electric field strength equal to a maximum electric field strength in the N-type diffusion layer 14 when the breakdown voltage is maintained.
As described above, the semiconductor device according to the first preferred embodiment enables improving the trade-off between the reduction in the on-resistance and the improvement of the breakdown voltage performance in the MOSFET including the N-type diffusion layer 3 serving as a drift layer by providing both the N-type buried diffusion layer 2 (second region) having a higher impurity peak concentration than the RESURF region, and the N-type diffusion layer 14 (seventh region), in the N-type diffusion layer 3 serving as the RESURF region.
Second Preferred EmbodimentWhen the MOSFET of the second preferred embodiment includes the N-type diffusion layer 15, an impurity concentration of a drift layer partially increases to higher than that of the MOSFET of the first preferred embodiment. Thus, the MOSFET of the second preferred embodiment has a lower on-resistance than that of the first preferred embodiment.
The N-type diffusion layer 15 has a lower impurity concentration than the N-type diffusion layer 14, and thus is liable to be depleted. Thus, disposing the N-type diffusion layer 15 enables suppressing concentration of an electric field when breakdown voltage is maintained. This enables breakdown voltage performance to be improved as compared with the first preferred embodiment.
As described above, the second preferred embodiment enables more effects of reducing the on-resistance of the MOSFET and improving the breakdown voltage performance to be obtained as compared with the first embodiment. Thus, a trade-off between the reduction in the on-resistance and the improvement of the breakdown voltage performance in the MOSFET can be further improved as compared with the first preferred embodiment.
The N-type diffusion layer 15 may have an uneven distribution of the impurity concentration, and thus may have an outer end portion with a concentration lower than that in an inner portion, for example. In that case, the N-type diffusion layer 15 may be formed overlapping the N-type diffusion layer 14, and the N-type diffusion layer 15 may be formed overlapping the entire N-type diffusion layer 14, for example. In other words, the N-type diffusion layer 14 may have a distribution of the impurity concentration in which the outer end portion has a lower concentration than the inner portion.
Although the N-type diffusion layer 15 is one integrated region in
The present embodiment allows the N-type diffusion layer 14 and the N-type diffusion layer 5 to be formed in the same impurity implantation step, so that the N-type diffusion layer 5 has an impurity concentration that is basically equal to an impurity concentration of the N-type diffusion layer 14. However, the N-type diffusion layer 14 and the N-type diffusion layer 5 may be different from each other in impurity concentration by forming the N-type diffusion layer 14 or the N-type diffusion layer 5 from a plurality of discrete regions as with the N-type diffusion layer 15 of the second preferred embodiment. When the N-type diffusion layer 5 has an impurity concentration indicated as N1 and the N-type diffusion layer 14 has an impurity concentration indicated as N2, a relationship, 0.1×N1<N2<2×N1, is preferably satisfied.
As in the third preferred embodiment, the N-type diffusion layer 14 and the N-type diffusion layer 5 can be formed in the same impurity implantation step. This enables reduction in the number of impurity implantation steps, so that a manufacturing step of the semiconductor device can be simplified. The third preferred embodiment may be combined with the second preferred embodiment.
Fourth Preferred EmbodimentThe N-type diffusion layer 14 has a higher impurity concentration than an N-type diffusion layer 3 serving as a RESURF region, so that the N-type diffusion layer 14 has a small voltage drop when breakdown voltage is maintained and high voltage is applied to a drain electrode 22 as shown in
The first preferred embodiment has the structure including the parasitic PNP transistor composed of the P-type diffusion layer 6, the N-type diffusion layer 3, and the P-type diffusion layer 1, and thus a current flowing through the parasitic PNP transistor (parasitic current) may increase power consumption. In contrast, the fifth preferred embodiment has structure in which such a parasitic PNP transistor is not formed to cause no parasitic current to flow, so that power consumption can be reduced.
The structure of the first preferred embodiment requires the P-type diffusion layer 1 and the P-type diffusion layer 6 to be separated from each other. This requires a sufficient distance between the layers to be secured, and thus causes a problem of increase in size of the MOSFET. In contrast, the structure of the fifth embodiment does not require such separation, so that an effect of enabling reduction in size of the MOSFET is achieved. The fifth preferred embodiment may be combined with the second, third, and fourth preferred embodiments.
Sixth Preferred EmbodimentWhen a layout as illustrated in
The MOSFET formed in the N-type diffusion layer 202 surrounding the high-side circuit (hatched portion in
The seventh preferred embodiment uses the MOSFET of the first preferred embodiment as the MOSFET 401 of the level shift circuit 303. The MOSFET of the first embodiment has high breakdown voltage performance and low on-resistance, so that the level shift circuit 303 can be operated in a wider range of potentials and power consumption can be reduced. As the MOSFET 401 of the level shift circuit 303, the MOSFET of the second, third, fourth, or fifth embodiment may be used. The high-side circuit 301, the low-side circuit 302, and the level shift circuit 303 may be formed in the same chip, or may be separated into separate respective chips.
In
The bootstrap circuit includes a limiting resistor 307, a bootstrap diode 308, and a bootstrap capacitor 309. The limiting resistor 307 and the bootstrap diode 308 are connected in series between the power supply 304b of the low-side circuit 302 and a power input terminal of the high-side circuit 301. The bootstrap capacitor 309 is connected between a connection node between the upper switching element 305a and the lower switching element 305b, and the power input terminal of the high-side circuit 301.
A Vs potential at the connection node between the upper switching element 305a and the lower switching element 305b changes between a potential of the power supply 306 and the GND potential when the upper switching element 305a and the lower switching element 305b are turned on and off. When the Vs potential equals the GND potential, a charge from the power supply 304b is supplied to the bootstrap capacitor 309 through the bootstrap diode 308 to charge the bootstrap capacitor 309. After that, when the Vs potential changes to the potential of the power supply 306, a charge is supplied from the bootstrap capacitor 309 to the power input terminal of the high-side circuit 301, and thus the bootstrap capacitor 309 functions as a power supply of the high-side circuit 301. At this time, the bootstrap diode 308 functions to prevent a current from flowing into the power supply 304b. The limiting resistor 307 functions to limit a current for charging the bootstrap capacitor 309 to a desired value.
Eighth Preferred EmbodimentThe MOSFET 310 is formed in a RESURF region that separates a high-side circuit 301 and a low-side circuit 302 from each other, as in the fifth preferred embodiment. This enables forming a bootstrap circuit that functions as a power supply for the high-side circuit 301 without using a high breakdown voltage element different from the drive IC including the high-side circuit 301 and the low-side circuit 302. As a result, this can contribute to miniaturization of a driving device including the drive IC of the half bridge circuit. The MOSFET 310 in
Additionally, the N-type diffusion layer 16 does not satisfy the RESURF condition. That is, when the N-type diffusion layer 16 has an impurity concentration indicated as N [cm−3] and a depth indicated as t [cm], a relationship, N×t>6.9×1011 cm−2, is satisfied. Thus, the ninth preferred embodiment does not allow the N-type diffusion layer 16 to be completely depleted when breakdown voltage is maintained, and allows an electric field to be concentrated in an outer end portion of the N-type diffusion layer 16. This causes the electric field to concentrate in both the N-type diffusion layer 14 and the N-type diffusion layer 16, so that an operation and an effect as in the first preferred embodiment can be obtained. Even in the present embodiment, the N-type diffusion layer 5 may be eliminated.
The ninth preferred embodiment does not require a diffusion layer having structure embedded inside the semiconductor substrate 100 to be formed. This enables a semiconductor device having an operation and an effect as in the first preferred embodiment to be formed by a usual impurity diffusion step. The ninth embodiment may be also applied to the semiconductor device of the second, third, fourth, fifth, sixth, seventh, or eighth embodiment to replace the N-type buried diffusion layer 2 with the N-type diffusion layer 16.
The respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or eliminated.
While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the disclosure.
Claims
1. A semiconductor device comprising:
- a semiconductor substrate formed with a first region of a first conductivity type;
- a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other;
- a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and
- a MOSFET using the second region as a drift layer,
- the MOSFET including:
- a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region;
- a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region;
- a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and
- a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region,
- wherein an end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit,
- the third region reaches a surface of the second region, and
- when the third region has an impurity concentration indicated as N [cm−3] and a depth indicated as t [cm], the relationship, N×t>6.9×1011 cm−2, is satisfied.
2. A semiconductor device comprising:
- a semiconductor substrate formed with a first region of a first conductivity type;
- a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other;
- a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and
- a MOSFET using the second region as a drift layer,
- the MOSFET including:
- a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region;
- a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region;
- a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and
- a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region,
- wherein an end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit,
- the semiconductor device further comprising:
- a second thermal oxide film formed on the surface of the second region, closer to the high-side circuit than the fourth region; and
- an eighth region of the second conductivity type formed below the second thermal oxide film, having a higher peak concentration of impurities than the second region, and
- when the eighth region has an impurity concentration indicated as N1 and the seventh region has an impurity concentration indicated as N2, a relationship, 0.1×N1<N2<2×N1, is satisfied.
3. A semiconductor device comprising:
- a semiconductor substrate formed with a first region of a first conductivity type;
- a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other;
- a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and
- a MOSFET using the second region as a drift layer,
- the MOSFET including:
- a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region;
- a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region;
- a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and
- a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region,
- wherein an end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit, and
- the semiconductor device further comprising:
- a ninth region of the second conductivity type formed in a region closer to the low-side circuit than the seventh region, having a peak concentration of impurities lower than the seventh region and higher than the second region.
4. A semiconductor device comprising:
- a semiconductor substrate formed with a first region of a first conductivity type;
- a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other;
- a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and
- a MOSFET using the second region as a drift layer,
- the MOSFET including:
- a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region;
- a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region;
- a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and
- a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region,
- wherein an end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit, and
- the semiconductor device further comprising:
- a ninth region of the second conductivity type formed discretely in a region closer to the low-side circuit than the seventh region, having a peak concentration of impurities equal to or lower than the seventh region and higher than the second region.
5. A semiconductor device comprising:
- a semiconductor substrate formed with a first region of a first conductivity type;
- a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other;
- a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and
- a MOSFET using the second region as a drift layer,
- the MOSFET including:
- a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region;
- a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region;
- a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and
- a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region,
- wherein an end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit, and
- the seventh region includes a portion close to the low-side circuit, having an impurity concentration higher than a portion close to the high-side circuit.
6. A semiconductor device comprising:
- a semiconductor substrate formed with a first region of a first conductivity type;
- a second region that is a RESURF region of a second conductivity type formed in a surface portion of the first region to separate a high-side circuit and a low-side circuit from each other;
- a third region of the second conductivity type formed at least in a bottom portion of the second region close to the high-side circuit, having a higher peak concentration of impurities than the second region; and
- a MOSFET using the second region as a drift layer,
- the MOSFET including:
- a fourth region serving as a drain region of the second conductivity type formed in the surface portion of the second region, having a higher peak concentration of impurities than the second region;
- a sixth region serving as a source region of the second conductivity type formed in a surface portion of a fifth region of the first conductivity type or in a surface portion of the first region, in a region closer to the low-side circuit than the fourth region, the fifth region being provided in the second region;
- a first thermal oxide film formed on a surface of the second region, in a region between the fourth region and the sixth region; and
- a seventh region of the second conductivity type formed in a surface portion of the second region below the first thermal oxide film, having a higher peak concentration of impurities than the second region,
- wherein an end portion of the seventh region close to the low-side circuit is located closer to the low-side circuit than an end portion of the third region close to the low-side circuit,
- the semiconductor device further comprising:
- a polysilicon layer formed on an end portion of the first thermal oxide film close to the high-side circuit, and
- an end portion of the polysilicon layer close to the low-side circuit is located closer to the low-side circuit than an end portion of the seventh region close to the low-side circuit.
7. The semiconductor device according to claim 1, wherein
- the MOSFET functions as a bootstrap diode that supplies power to the high-side circuit.
8. The semiconductor device according to claim 2, wherein
- the MOSFET functions as a bootstrap diode that supplies power to the high-side circuit.
9. The semiconductor device according to claim 3, wherein
- the MOSFET functions as a bootstrap diode that supplies power to the high-side circuit.
10. The semiconductor device according to claim 4, wherein
- the MOSFET functions as a bootstrap diode that supplies power to the high-side circuit.
11. The semiconductor device according to claim 5, wherein
- the MOSFET functions as a bootstrap diode that supplies power to the high-side circuit.
12. The semiconductor device according to claim 6, wherein
- the MOSFET functions as a bootstrap diode that supplies power to the high-side circuit.
13. An integrated circuit comprising the semiconductor device according to claim 1.
14. An integrated circuit comprising the semiconductor device according to claim 2.
15. An integrated circuit comprising the semiconductor device according to claim 3.
16. An integrated circuit comprising the semiconductor device according to claim 4.
17. An integrated circuit comprising the semiconductor device according to claim 5.
18. An integrated circuit comprising the semiconductor device according to claim 6.
Type: Application
Filed: Sep 12, 2023
Publication Date: Jan 4, 2024
Applicant: Mitsubishi Electric Corporation (Tokyo)
Inventors: Toshihiro IMASAKA (Tokyo), Kazuhiro SHIMIZU (Tokyo), Manabu YOSHINO (Tokyo), Yuji KAWASAKI (Tokyo)
Application Number: 18/465,423