QUAD FLAT NO-LEAD (QFN) PACKAGE WITHOUT LEADFRAME AND DIRECT CONTACT INTERCONNECT BUILD-UP STRUCTURE
A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. A semiconductor chip with conductive stumps over an active surface, a first layer of encapsulant disposed around the semiconductor chip, over the active surface, and around the conductive stumps, a first conductive layer and first vertical conductive contacts electrically coupled with the conductive stumps, the first conductive layer comprising conductive traces formed over a planarized surface of the encapsulant and conductive stumps, a second layer of encapsulant disposed over the first encapsulant layer, conductive layer, conductive traces, and first vertical conductive contacts, a plurality of conductive pads formed over a planarized surface, and a solderable metal system (SMS) formed or an organic solderability preservative (OSP) applied over at least a portion of the conductive pads.
This disclosure claims the benefit, including the filing date, of U.S. Provisional Patent Application No. 63/391,315 entitled “Quad Flat No-Lead (QFN) Package Without Leadframe and Direct Contact Interconnect Build-up Structure Without Capture Pads and Method for Making the Same” to Davis et al. that was filed on Jul. 21, 2022, the entire disclosure of which is hereby incorporated herein by this reference.
TECHNICAL FIELDThis disclosure concerns devices and methods of forming quad flat no-lead (QFN), dual flat no-lead (DFN) or small-outline no-lead (SON) semiconductor packaging without a leadframe and with molded direct contact interconnect build-up structures.
BACKGROUNDSemiconductor devices, packages, substrates, and interposers are commonly found in modern electronic products. Production of semiconductor devices involves a multistep build-up of components. Conventional interconnect structures alternate dielectric and conductive layers. An opening or via is created in the dielectric to allow connectivity from one layer to another. On the conductive layers, capture pads are required for the vias to correct for inconsistencies in manufacture. Use of these conventional capture pads impacts the ability to construct compact structures due to limits on routing density. Additionally, traditional manufacturing processes involve the use of leadframes that result in exposed leadframe ends on the sides of the packaging.
SUMMARYAn opportunity exists for improved packages, including applications for semiconductor manufacturing. Aspects of this document relate to a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe, comprising a semiconductor chip comprising conductive stumps over an active surface of the semiconductor chip, a first layer of encapsulant disposed in a single step around four side surfaces of the semiconductor chip, over the active surface of the semiconductor chip, and around the conductive stumps, a first conductive layer and first vertical conductive contacts electrically coupled with the conductive stumps of the semiconductor chip, the first conductive layer comprising conductive traces formed over a planarized surface of the encapsulant and conductive stumps, a second layer of encapsulant disposed over the first encapsulant layer, the first conductive layer, the conductive traces, and the first vertical conductive contacts, a plurality of conductive pads in the form of land pads or bumps formed over a planarized surface of the second layer of encapsulant and in electrical contact with the first vertical conductive contacts, and a solderable metal system (SMS) formed or an organic solderability preservative (OSP) applied over at least a portion of the conductive pads.
Particular embodiments may comprise one or more of the following features. The SMS is a single layer or multi-material layer build-up of conductive materials comprising at least one of a layer of nickel (Ni), a layer of silver (Ag), a layer of palladium (Pd), a layer of tin (Sn), and a layer of gold (Au) formed over the conductive pads. The SMS comprising a layer of conductive materials over the conductive pads formed by one or more of electroplating, electroless plating, immersion plating, physical vapor deposition (PVD), and chemical vapor deposition (CVD). Each conductive pad includes at least the second layer of encapsulant locked between the first conductive layer and the conductive pads. The first conductive layer comprises a redistribution layer formed directly upon an encapsulant surface, and wherein the second layer of encapsulant is formed directly upon the redistribution layer, wherein the encapsulant surface and the second layer of encapsulant are of the same kind of encapsulant. One or more of a conductive structure, a flag, mounting pads, an identifying mark, and alignment marks over the semiconductor chip and over the second layer of encapsulant. The conductive pad extends beyond a surface edge of an uppermost encapsulant layer. An offset between an edge or side of the conductive pad and the package. The encapsulant of at least one of the first layer of encapsulant and the second layer of encapsulant is not a polymer material and comprises a mold compound, a polyimide or a composite material. The QFN, DFN or SON package is formed without exposed copper on the QFN, DFN or SON package. The QFN, DFN or SON package is formed without exposed copper on the periphery of the package. At least one of a through mold post and a double-sided circuit trace. Additional conductive stumps formed over the first layer of encapsulant.
Aspects of the disclosure relate to a quad flat no-lead (QFN) dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe, comprising a semiconductor chip comprising conductive stumps over an active surface of the semiconductor chip, encapsulant disposed in a single step around four side surfaces of the semiconductor chip, over the active surface of the semiconductor chip, and around a portion of sidewalls of the conductive stumps, conductive traces formed over a planarized surface of the encapsulant and conductive stumps, a plurality of conductive pads in the form of land pads or bumps formed over the encapsulant and in electrical contact with the conductive stumps, and a solderable metal system (SMS) or an organic solderability preservative (OSP) formed over at least a portion of the conductive pads.
Particular embodiments may comprise one or more of the following features. The SMS comprising a layer of conductive materials over the conductive pads formed by one or more of electroplating, electroless plating, immersion plating, physical vapor deposition (PVD), and chemical vapor deposition (CVD). Each conductive pad includes at least one layer of encapsulant locked between at least two layers of conductive material. Each conductive pad includes at least two layers of encapsulant interlocked between at least three layers of conductive material. A redistribution layer formed directly upon an encapsulant surface, and encapsulant disposed directly upon the redistribution layer, wherein the encapsulant upon which the redistribution layer is formed and the encapsulant disposed directly upon the redistribution layer are of the same kind of encapsulant. The SMS is a single layer or multi-material layer build-up of conductive materials comprising at least one of a layer of nickel (Ni), a layer of silver (Ag), a layer of palladium (Pd), a layer of tin (Sn), and a layer of gold (Au) formed over the conductive pads. One or more of a conductive structure, a flag, mounting pads, an identifying mark, and alignment marks over the semiconductor chip and over the second layer of encapsulant. The conductive pad extends beyond a surface edge of an uppermost encapsulant layer. An offset between an edge or side of the conductive pad and the package edge. The encapsulant of at least one of the first layer of encapsulant and the second layer of encapsulant is not a polymer material and comprises a mold compound, a polyimide or a composite material. The QFN, DFN or SON package is formed without exposed copper on the QFN, DFN or SON package. The package further comprising at least one of a through mold post and a double-sided circuit trace. The package further comprising a thermal path in the form of a thermal stud configured to conduct thermal energy from the package to a printed circuit board to which the package is mounted.
The QFN, DFN or SON package of claim 15, further comprising a plurality of dummy thermal conductive stumps formed over the active surface of the semiconductor chip and thermally coupled with a thermally dissipative die plate on the QFN, DFN or SON package. The QFN, DFN or SON package includes no solder balls. Additional conductive stumps formed over the encapsulant.
The foregoing and other aspects, features, applications, and advantages will be apparent to those of ordinary skill in the art from the specification, drawings, and the claims. Unless specifically noted, it is intended that the words and phrases in the specification and the claims be given their plain, ordinary, and accustomed meaning to those of ordinary skill in the applicable arts. The inventors are fully aware that they can be their own lexicographers if desired. The inventors expressly elect, as their own lexicographers, to use only the plain and ordinary meaning of terms in the specification and claims unless they clearly state otherwise and then further, expressly set forth the “special” definition of that term and explain how it differs from the plain and ordinary meaning. Absent such clear statements of intent to apply a “special” definition, it is the inventors' intent and desire that the simple, plain and ordinary meaning to the terms be applied to the interpretation of the specification and claims.
The inventors are also aware of the normal precepts of English grammar. Thus, if a noun, term, or phrase is intended to be further characterized, specified, or narrowed in some way, then such noun, term, or phrase will expressly include additional adjectives, descriptive terms, or other modifiers in accordance with the normal precepts of English grammar. Absent the use of such adjectives, descriptive terms, or modifiers, it is the intent that such nouns, terms, or phrases be given their plain, and ordinary English meaning to those skilled in the applicable arts as set forth above.
Further, the inventors are fully informed of the standards and application of the special provisions of 35 U.S.C. § 112(f). Thus, the use of the words “function,” “means” or “step” in the Detailed Description or Description of the Drawings or claims is not intended to somehow indicate a desire to invoke the special provisions of 35 U.S.C. § 112(f), to define the invention. To the contrary, if the provisions of 35 U.S.C. § 112(f) are sought to be invoked to define the inventions, the claims will specifically and expressly state the exact phrases “means for” or “step for”, and will also recite the word “function” (i.e., will state “means for performing the function of [insert function]”), without also reciting in such phrases any structure, material or act in support of the function. Thus, even when the claims recite a “means for performing the function of . . . ” or “step for performing the function of . . . ,” if the claims also recite any structure, material or acts in support of that means or step, or that perform the recited function, then it is the clear intention of the inventors not to invoke the provisions of 35 U.S.C. § 112(f). Moreover, even if the provisions of 35 U.S.C. § 112(f) are invoked to define the claimed aspects, it is intended that these aspects not be limited only to the specific structure, material or acts that are described in the preferred embodiments, but in addition, include any and all structures, materials or acts that perform the claimed function as described in alternative embodiments or forms of the disclosure, or that are well known present or later-developed, equivalent structures, material or acts for performing the claimed function.
The foregoing and other aspects, features, and advantages will be apparent to those of ordinary skill in the art from the specification, drawings, and the claims.
Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:
This disclosure, its aspects and implementations, are not limited to the specific package types, material types, or other system component examples, or methods disclosed herein. Many additional components, manufacturing and assembly procedures known in the art consistent with semiconductor wafer fabrication, manufacture and packaging are contemplated for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any components, models, types, materials, versions, quantities, or the like as is known in the art for such systems and implementing components, consistent with the intended operation.
DETAILED DESCRIPTIONThe present disclosure includes one or more aspects or embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. Those skilled in the art will appreciate that the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. In the description, numerous specific details are set forth, such as specific configurations, compositions, and processes, etc., in order to provide a thorough understanding of the disclosure. In other instances, well-known processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the disclosure. Furthermore, the various embodiments shown in the FIGs. Are illustrative representations and are not necessarily drawn to scale.
The word “exemplary,” “example” or various forms thereof are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” or as an “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Furthermore, examples are provided solely for purposes of clarity and understanding and are not meant to limit or restrict the disclosed subject matter or relevant portions of this disclosure in any manner. It is to be appreciated that a myriad of additional or alternate examples of varying scope could have been presented, but have been omitted for purposes of brevity.
This disclosure relates to a quad flat no-lead (QFN), dual flat no-lead (DFN) or small-outline no-lead (SON) package without a leadframe and with molded direct contact interconnect build-up structures, and a method of making the same. A QFN, DFN or SON is a small-sized integrated circuit (IC) package that offers small size, low cost, and very good performance.
No-lead packages such as QFN, DFN and SON packages physically and electrically connect to the surface of printed circuit boards (PCB's) or other substrates using surface mount technology, thus coupling the IC to the PCB or other substrate. In the surface mount technology illustrated in the conventional QFN package 500 of
QFN, DFN and SON packages are a near chip-scale plastic encapsulated package made with a metal leadframe substrate.
In contrast,
The present disclosure relates to QFN, DFN and SON packages without a leadframe, and with molded direct contact interconnect build-up structures. An example of a molded direct contact interconnect build-up structure is known under the trademark or tradename MDx™. Molded direct contact interconnect build-up structures (and a method for making and using the same) are discussed in U.S. Provisional Patent 63/347,516, the entirety of which is hereby incorporated herein by reference. Molded direct contact interconnect build-up structures may comprise or provide: (i) large area chip bond pad interconnect to create a very low contact resistance, (ii) removal of capture pads between build-up layers, such as traces, (iii) cost savings by removing polyimide and other polymers from the build-up layers, using mold compound instead, and (iv) facilitate ultra-high-density connections such as 20 micrometer bond pitch and smaller.
At least some of the above advantages are available at least in part by using unit specific patterning (such as adaptive patterning (custom design and lithography) and build-up interconnect structures such as a frontside build-up interconnect structure, which is also known under the trademark “Adaptive Patterning,” referred to as “AP.” Unit specific patterning: (i) allows for the use high-speed chip attach for semiconductor chips and AP will ensure alignment for high density interconnects with the molded direct contact interconnect build-up structures. Adaptive Patterning may also be used in the herein disclosed processes for manufacturing QFN, DFN and SON packages including the ability to make large area connections which are precisely aligned to chip bond pads for very low contact resistance.
Each semiconductor chip 14 may comprise a backside or back surface and an active layer opposite the backside. The active layer contains one or more circuits or discrete components of any kind implemented as active devices, or only conductive layers, and dielectric layers formed within or on the chip and electrically interconnected according to the electrical design and function of the semiconductor chip. For example, the circuit may include, without limitation, one or more transistors, diodes, and other circuit elements formed within active layer to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuits. The semiconductor chip may also contain IPDs such as inductors, capacitors, and resistors, for RF signal processing, digital power line control or other functions. The semiconductor chip 14 may consist only of conductive routing layers and associated dielectric layers such as for use as a bridge chip between active devices or other electrical function. The semiconductor chip 14 may also be added as one of many chips being added simultaneously on a carrier. The semiconductor chip may also be only a dummy substrate with no electrical function, but rather act merely as a structural element. In some instances there can be connections on both sides of the chip. The principles and structures taught in relation to this disclosure are applicable to known existing technologies that are compatible with the QFN, DFN or SON packages disclosed without a leadframe and using direct contact interconnect build-up.
In some instances, the semiconductor chips will have a thickness (shown in the vertical direction, bottom to top, of the page) of between about 25 μm to about 150 μm for thin ground wafers, or about 100 μm to about 800 μm for thick ground wafers. In some instances, the temporary carrier may be a metal carrier, a silicon carrier, a glass carrier, or a carrier made of other suitable material used for the molding or encapsulating process, and then be removed after the encapsulant, such as mold compound, filled epoxy film such as ABF, or other dielectric such as polyimide has been placed, cured, or both, such that the encapsulant provides structural support and the temporary carrier is no longer needed for processing. The semiconductor chips 14 may be placed adjacent one another, such as in a side-by-side arrangement, so that multiple chips may be formed at a re-constituted wafer or panel level and processed through various fabrication steps, before being singulated into individual QFN, DFN or SON packages. As such, multiple chips may also be processed together at a same time over the temporary carrier, which will be understood by a person of ordinary skill in the art (POSITA), even when a close-up view of just portions of the semiconductor chips 14 are shown.
Planarizing or grinding the encapsulant 130 over the active surface to expose the conductive stumps 125 may occur before or after removing the temporary carrier 120. As referenced above,
For the embodiments illustrated in
Unlike with a conventional QFN, DFN and SON packages that cannot be tested until the leadframe is cut to isolate the packages from other adjacent packages. Embodiments of the present design with the conductive pads 142 inset from an edge of the package may be tested in strip form without the need to isolate the packaged semiconductor chips prior to testing.
Although the illustrations show QFN packages, the technologies and processes disclosed herein can also be used with DFN and SON packages.
In other embodiments, the dummy thermal conductive stumps 178 dissipate heat to the die pad 512 but are not electrically connected. In embodiments where the conductive stumps 178 are electrically connected the semiconductor chip 14, the die pad 512 may be configured as a die attach feature with an additional semiconductor chip attached over the die pad 512, electrically connected to the semiconductor chip 14 through the die pad 512 and wire bonded to the contact pads 142 of the QFN, DFN or SON package 170. In cases where there is wiring on the top chip layer that prevents use of a dummy pad, conductive stumps 178 may attach on top of the chip passivation layer or other dielectric that is on top of the chip. In particular embodiments, a ground connection may be made from one or more ground pads on the semiconductor chip 14 through one or more conductive stumps 178 to the die pad 512. In such cases, the die pad 512 may be soldered to a corresponding ground pad on the PCB when the QFN, DFN or SON package is mounted on the PCB.
The QFN, DFN or SON package structure of
In other embodiments, such as is illustrated in
After the SMS 154 is applied, a second saw 161 finishes the cut through the packaging to singulate the packages. The second saw 161, however, is a narrower saw and cuts between the packaging but leaves the SMS 154 over the RDL 135 and conductive stumps 140. The resulting structure, illustrated in
While this disclosure includes a number of embodiments in different forms, the particular embodiments presented are with the understanding that the present disclosure is to be considered as an exemplification of the principles of the disclosed structures, devices, methods, and systems, and is not intended to limit the broad aspect of the disclosed concepts to the embodiments illustrated. Additionally, it should be understood by those of ordinary skill in the art that other structures, manufacturing devices, and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art. As such, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the inventions as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
Claims
1. A quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe, comprising:
- a semiconductor chip comprising conductive studs over an active layer of the semiconductor chip, wherein each of the conductive studs comprise a first end directly connected to the active layer and a second end opposite the first end wherein the second end is in a range of 1-50 micrometers (μm) from the first end;
- a first layer of encapsulant disposed as a single layer around four side surfaces of the semiconductor chip, over the active surface of the semiconductor chip, and around the conductive studs;
- a first conductive layer and first vertical conductive contacts electrically coupled with the conductive studs of the semiconductor chip, the first conductive layer comprising conductive traces formed over a planarized surface of the first layer of encapsulant and conductive studs;
- a second layer of encapsulant disposed over the first encapsulant layer, the first conductive layer, the conductive traces, and the first vertical conductive contacts;
- a plurality of conductive pads in the form of land pads or bumps formed over a planarized surface of the second layer of encapsulant and in electrical contact with the first vertical conductive contacts; and
- a solderable metal system (SMS) formed or an organic solderability preservative (OSP) applied over at least a portion of the conductive pads.
2. The QFN, DFN or SON package of claim 1, wherein:
- the SMS is a single layer or multi-material layer build-up of conductive materials comprising at least one of a layer of nickel (Ni), a layer of silver (Ag), a layer of palladium (Pd), a layer of tin (Sn), and a layer of gold (Au) formed over the conductive pads; and
- the SMS comprising a layer of conductive materials over the conductive pads is formed by one or more of electroplating, electroless plating, immersion plating, physical vapor deposition (PVD), and chemical vapor deposition (CVD).
3. The QFN, DFN or SON package of claim 1, wherein at least one of the conductive traces is coupled to at least one conductive stud such that the at least one conductive trace is narrower in at least one direction than a greatest width of the at least one conductive stud.
4. A quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe, comprising:
- a semiconductor chip comprising conductive studs over an active surface of the semiconductor chip, wherein the conductive studs comprise a first end coupled to the active layer and a second end opposite the first end wherein the second end is in a range of 1-50 micrometers (μm) from the first end;
- a first layer of encapsulant disposed as a single layer around four side surfaces of the semiconductor chip, over the active surface of the semiconductor chip, and around the conductive studs;
- a first conductive layer and first vertical conductive contacts electrically coupled with the conductive studs of the semiconductor chip, the first conductive layer comprising conductive traces formed over a planarized surface of the first layer of encapsulant and conductive studs;
- a second layer of encapsulant disposed over the first encapsulant layer, the first conductive layer, the conductive traces, and the first vertical conductive contacts;
- a plurality of conductive pads in the form of land pads or bumps formed over a planarized surface of the second layer of encapsulant and in electrical contact with the first vertical conductive contacts, wherein each conductive pad includes at least the second layer of encapsulant locked between the first conductive layer and the conductive pads; and
- a solderable metal system (SMS) formed or an organic solderability preservative (OSP) applied over at least a portion of the conductive pads.
5. The QFN, DFN or SON package of claim 1, wherein the first conductive layer comprises a redistribution layer formed directly upon an encapsulant surface, and wherein the second layer of encapsulant is formed directly upon the redistribution layer, wherein the encapsulant surface and the second layer of encapsulant are of the same kind of encapsulant.
6. The QFN, DFN or SON package of claim 1, further comprising one or more of a conductive structure, a flag, mounting pads, an identifying mark, and alignment marks over the semiconductor chip and over the second layer of encapsulant.
7. The QFN, DFN or SON package of claim 6, wherein the conductive pad extends beyond a surface edge of an uppermost encapsulant layer.
8. The QFN, DFN or SON package of claim 7, further comprising an offset between an edge or side of the conductive pad and the package.
9. The QFN, DFN or SON package of claim 8, wherein the encapsulant of at least one of the first layer of encapsulant and the second layer of encapsulant comprises a mold compound, a polyimide or a composite material.
10. The QFN, DFN or SON package of claim 9, wherein the QFN, DFN or SON package is formed without exposed copper on the QFN, DFN or SON package.
11. The QFN, DFN or SON package of claim 9, wherein the QFN, DFN or SON package is formed without exposed copper on the periphery of the package.
12. The QFN, DFN or SON package of claim 9, further comprising at least one of a through mold post and a double-sided circuit trace.
13. The QFN, DFN or SON package of claim 11, further comprising additional conductive studs formed over the first layer of encapsulant.
14. A quad flat no-lead (QFN) dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe, comprising:
- a semiconductor chip comprising conductive studs over an active layer of the semiconductor chip; wherein the conductive studs comprise a first end directly connected to the active layer and a second end opposite the first end wherein the second end is in a range of 1-50 micrometers (μm) from the first end;
- encapsulant disposed in a single layer around four side surfaces of the semiconductor chip, over the active surface of the semiconductor chip, and around a portion of sidewalls of the conductive studs;
- conductive traces formed over a planarized surface of the encapsulant and conductive studs; and
- a plurality of conductive pads in the form of land pads or bumps formed over the encapsulant and in electrical contact with the conductive studs.
15. The QFN, DFN or SON package of claim 14, wherein the SMS comprising a layer of conductive materials over the conductive pads formed by one or more of electroplating, electroless plating, immersion plating, physical vapor deposition (PVD), and chemical vapor deposition (CVD).
16. The QFN, DFN or SON package of claim 14, wherein each conductive pad includes at least one layer of encapsulant locked between at least two layers of conductive material.
17. The QFN, DFN or SON package of claim 14, wherein each conductive pad includes at least two layers of encapsulant interlocked between at least three layers of conductive material.
18. The QFN, DFN or SON package of claim 14, further comprising a redistribution layer formed directly upon an encapsulant surface, and encapsulant disposed directly upon the redistribution layer, wherein the encapsulant upon which the redistribution layer is formed and the encapsulant disposed directly upon the redistribution layer are of the same kind of encapsulant.
19. The QFN, DFN or SON package of claim 14, wherein the SMS is a single layer or multi-material layer build-up of conductive materials comprising at least one of a layer of nickel (Ni), a layer of silver (Ag), a layer of palladium (Pd), a layer of tin (Sn), and a layer of gold (Au) formed over the conductive pads.
20. The QFN, DFN or SON package of claim 14, further comprising one or more of a conductive structure, a flag, mounting pads, an identifying mark, and alignment marks over the semiconductor chip and over a second encapsulant disposed over the first layer of encapsulant.
21. The QFN, DFN or SON package of claim 14, wherein the conductive pad extends beyond a surface edge of an uppermost encapsulant layer.
22. The QFN, DFN or SON package of claim 14, further comprising an offset between an edge or side of the conductive pad and the package edge.
23. The QFN, DFN or SON package of claim 14, wherein the encapsulant comprises a mold compound, a polyimide or a composite material.
24. The QFN, DFN or SON package of claim 14, wherein the QFN, DFN or SON package is formed without exposed copper on the QFN, DFN or SON package.
25. The QFN, DFN or SON package of claim 14, the package further comprising at least one of a through mold post and a double-sided circuit trace.
26. The QFN, DFN or SON package of claim 14, the package further comprising a thermal path in the form of a thermal stud configured to conduct thermal energy from the package to a printed circuit board to which the package is mounted.
27. The QFN, DFN or SON package of claim 14, further comprising a plurality of dummy thermal conductive studs formed over the active surface of the semiconductor chip and thermally coupled with a thermally dissipative die plate on the QFN, DFN or SON package.
28. The QFN, DFN or SON package of claim 14, wherein the QFN, DFN or SON package includes no solder balls.
29. The QFN, DFN or SON package of claim 14, further comprising additional conductive studs formed over the encapsulant.
Type: Application
Filed: Sep 30, 2022
Publication Date: Jan 25, 2024
Inventors: Robin Davis (Vancouver, WA), Paul R. Hoffman (San Diego, CA), Clifford Sandstrom (Richfield, MN), Timothy L. Olson (Phoenix, AZ)
Application Number: 17/957,936