Patents by Inventor Ta-Chun Lin

Ta-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998237
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Publication number: 20210120361
    Abstract: An audio adjusting method and an audio adjusting device are provided. The audio adjusting method includes the steps of: receiving a plurality of directional audio signals; calculating a displacement amount through a positioning module; calculating a plurality of gain values corresponding to the displacement amount through a processing module; adjusting volume levels of the plurality of directional audio signals according to the plurality of gain values; converting the plurality of directional audio signals into a two- or multi-channel audio signal according to the quantity of two or more channels of a head-mounted playback device; and playing the two-channel or multi-channel audio signal through the head-mounted playback device.
    Type: Application
    Filed: August 7, 2020
    Publication date: April 22, 2021
    Inventors: Chin-Wei Lin, Ta-Chun Wang, CHI-CHEN CHENG
  • Publication number: 20210098312
    Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first fin structure with a first composition and a second fin structure with a second composition, oxidizing the first fin structure to form a first oxide layer and oxidizing the second fin structure to form a second oxide layer, removing the second oxide layer formed on the second fin structure, oxidizing the second fin structure to form a third oxide layer over the second fin structure, and forming a first metal gate electrode layer over the first oxide layer and a second metal gate electrode layer over the third oxide layer.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Hsin-Che CHIANG, Yu-San CHIEN, Ta-Chun LIN, Chun-Sheng LIANG, Kuo-Hua PAN
  • Publication number: 20210074841
    Abstract: A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Publication number: 20210066060
    Abstract: A use of an anthranilic acid derivative as a matrix for a MALDI Mass spectrometry, comprising: preparing a matrix compound represented by the following formula: wherein X is selected from hydrogen and a hydroxyl group, and Y is selected from hydrogen, a methyl group or an acetyl group, provided that when X is hydrogen, Y is hydrogen or an acetyl group, and when X is a hydroxyl group, Y is a methyl group; applying the matrix compound and an analyte onto a sample holder; and analyzing the analyte by the MALDI mass spectrometer.
    Type: Application
    Filed: September 3, 2020
    Publication date: March 4, 2021
    Applicant: National Taiwan University
    Inventors: Cheng-Chih Hsu, Pi-Tai Chou, Chuping Lee, Penghsuan Huang, Li-En Lin, Chun-Ying Huang, Ta-Chun Lin
  • Publication number: 20210066119
    Abstract: Semiconductor structures and methods are provided. A semiconductor structure according to an embodiment includes a first cell disposed over a first well doped with a first-type dopant, a second cell disposed over the first well, and a tap cell disposed over a second well doped with a second-type dopant different from the first-type dopant. The tap cell is sandwiched between the first cell and the second cell. The first cell includes a first plurality of transistors and the second cell includes a second plurality of transistors.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 4, 2021
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Publication number: 20210057544
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers separated vertically from each other and a dummy pattern layer including dielectric material disposed over and separated vertically from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also comprises a gate structure disposed over a channel region, wherein the gate structure wraps around each of the plurality of semiconductor layers and the dummy pattern layer of the nanostructure.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Publication number: 20200411363
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first and second well regions with different conductivity types in a semiconductor substrate. A well interface is formed between the first and second well regions. The method also includes patterning the semiconductor substrate to form a first fin structure in the first well region, a second fin structure in the second well region, and a first trench between the first and second fin structures. The first trench exposes the well interface in the semiconductor substrate. The method further includes forming insulating spacers on opposite sidewalls of the first trench and etching the semiconductor substrate below the first trench using the insulating spacers as an etch mask, to form a second trench below the first trench. In addition, the method includes filling the first and second trenches with an insulating material.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Publication number: 20200343365
    Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.
    Type: Application
    Filed: November 12, 2019
    Publication date: October 29, 2020
    Inventors: Ta-Chun Lin, Jhon Jhy Liaw, Kuo-Hua Pan
  • Publication number: 20200343363
    Abstract: A semiconductor structure includes a first active region over a substrate and extending along a first direction, a gate structure over the first active region and extending along a second direction substantially perpendicular to the first direction, a gate-cut feature abutting an end of the gate structure, and a channel isolation feature extending along the second direction and between the first active region and a second active region. The gate structure includes a metal electrode in direct contact with the gate-cut feature. The channel isolation feature includes a liner on sidewalls extending along the second direction and a dielectric fill layer between the sidewalls. The gate-cut feature abuts an end of the channel isolation feature and the dielectric fill layer is in direct contact with the gate-cut feature.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Inventors: Ta-Chun Lin, Jhon Jhy Liaw, Kuo-Hua Pan
  • Patent number: 10790184
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Lin, Tien-Shao Chuang, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Publication number: 20200266271
    Abstract: Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Publication number: 20200243396
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Application
    Filed: April 20, 2020
    Publication date: July 30, 2020
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Publication number: 20200168715
    Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.
    Type: Application
    Filed: May 10, 2019
    Publication date: May 28, 2020
    Inventors: Shien-Yang Wu, Ta-Chun Lin, Kuo-Hua Pan
  • Publication number: 20200144128
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Patent number: 10629492
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Publication number: 20200105612
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun LIN, Tien-Shao CHUANG, Kuang-Cheng TAI, Chun-Hung CHEN, Chih-Hung HSIEH, Kuo-Hua PAN, Jhon-Jhy LIAW
  • Publication number: 20190334035
    Abstract: A semiconductor device includes a substrate, first and second source/drain features, and a dielectric plug. The substrate has a semiconductor fin. The first and second source/drain features are over first and second portions of the semiconductor fin, respectively. The dielectric plug is at least partially embedded in a third portion of the semiconductor fin. The third portion is in between the first and second portions of the semiconductor fin. The dielectric plug includes a first dielectric material and a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: April 25, 2018
    Publication date: October 31, 2019
    Inventors: Kuei-Ming CHANG, Ta-Chun LIN, Rei-Jay HSIEH, Yung-Chih WANG, Wen-Huei GUO, Kuo-Hua PAN, Buo-Chin HSU
  • Publication number: 20190333822
    Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.
    Type: Application
    Filed: April 27, 2018
    Publication date: October 31, 2019
    Inventors: Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw, Chih-Yung Lin
  • Patent number: 9805970
    Abstract: A method for manufacturing an image sensor with deep trench spacing isolation is provided. A trench is formed in a semiconductor substrate, around and between a plurality of pixel regions of the semiconductor substrate. A cap is formed using epitaxy to seal a gap between sidewalls of the trench. Pixel sensors corresponding to the plurality of pixel regions are formed over or within the corresponding pixel regions. An image sensor resulting from the method is also provided.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Jung-I Lin, Ta-Chun Lin, Tien-Lu Lin, Chen-Jong Wang