Patents by Inventor Ta-Chun Lin

Ta-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240203829
    Abstract: A semiconductor device includes a transistor structure disposed on a first side of a substrate and a back-side via structure disposed on a second side of the substrate opposite to the first side. The transistor structure includes a pair of epitaxial structures and a channel feature extending in a channel length direction to be disposed between the epitaxial structures. The channel feature has a width in a channel width direction transverse to the channel length direction. The back-side via structure extends through the substrate so as to be connected to a bottom surface and a sidewall surface of a lower portion of a corresponding one of the epitaxial structures. The back-side via structure has a width in the channel width direction, which is greater than the width of the channel feature.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 20, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Jhon-Jhy LIAW
  • Patent number: 11996320
    Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw
  • Publication number: 20240170537
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Kuo-Hua PAN, Jhon-Jhy LIAW, Chao-Ching CHENG, Hung-Li CHIANG, Shih-Syuan HUANG, Tzu-Chiang CHEN, I-Sheng CHEN, Sai-Hooi YEONG
  • Publication number: 20240170533
    Abstract: A semiconductor structure includes a first device unit and a second device unit, each of which includes channel features spaced apart from each other, and a dielectric wall disposed between the first and second device units. The dielectric wall includes a first part which includes a plurality of first portions that are in direct contact with the channel features of the first device unit, and a second part which includes a plurality of second portions that are in direct contact with the channel features of the second device unit. At least one of the first and second parts carries positive or negative charges.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Han TSAI, Ta-Chun LIN, Chun-Sheng LIANG, Chih-Hao CHANG
  • Patent number: 11990525
    Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Kuo-Hua Pan, Mu-Chi Chiang, Jhon Jhy Liaw
  • Publication number: 20240162308
    Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.
    Type: Application
    Filed: February 9, 2023
    Publication date: May 16, 2024
    Inventors: Pin Chun SHEN, Che Chia CHANG, Li-Ying WU, Jen-Hsiang LU, Wen-Chiang HONG, Chun-Wing YEUNG, Ta-Chun LIN, Chun-Sheng LIANG, Shih-Hsun CHANG, Chih-Hao CHANG, Yi-Hsien CHEN
  • Publication number: 20240162310
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a portion of the first contact structure is lower than a top surface of the first S/D structure. The semiconductor structure includes a second contact structure formed over a second side of the first S/D structure, and the second contact structure is in direct contact with the first contact structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: May 16, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Wen-Chiang HONG, Chih-Hao CHANG
  • Publication number: 20240162321
    Abstract: A semiconductor structure includes a substrate, a dielectric wall, and two device units. The dielectric wall has two side surfaces opposite to each other. The two device units are respectively formed at the two side surfaces of the dielectric wall. Each of the device units includes channel features, a gate feature and a dielectric filler unit. The channel features are disposed on a corresponding one of the side surfaces of the dielectric wall, and spaced apart from each other. The gate feature is formed around the channel features and disposed on the corresponding one of the side surfaces of the dielectric wall. The dielectric filler unit includes a plurality of first dielectric fillers, each of which is disposed between the dielectric wall and a corresponding one of the channel features. The first dielectric fillers have a dielectric constant greater than that of the dielectric wall.
    Type: Application
    Filed: February 22, 2023
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Chao CHANG, Ta-Chun LIN, Chun-Sheng LIANG, Jhon-Jhy LIAW
  • Patent number: 11967532
    Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Chih-Yung Lin, Jhon Jhy Liaw
  • Publication number: 20240120338
    Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Ming-Che CHEN, Yu-Hsuan LU, Chih-Hao CHANG
  • Publication number: 20240120337
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: January 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Chih-Hung HSIEH, Chun-Sheng LIANG, Wen-Chiang HONG, Chun-Wing YEUNG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240120377
    Abstract: Semiconductor structures and processes are provided that include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure may be formed on a dielectric wall from which nanostructure channel regions extend. The second gate isolation structure may be formed on a shallow trench isolation feature. The height of the first gate isolation structure is less than the height of the second gate isolation structure. The composition of the first gate isolation structure may be different than the composition of the second gate isolation structure. In some implementations, the first gate isolation structure is formed concurrently with gate spacers.
    Type: Application
    Filed: February 10, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Jhon Jhy LIAW
  • Publication number: 20240120414
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a semiconductor layer disposed over a substrate, and the semiconductor layer has a first end and a second end opposite the first end. The structure further includes an epitaxial feature disposed over the substrate, and the epitaxial feature is electrically connected to the first end of the semiconductor layer. The structure further includes a first dielectric layer disposed over the substrate, and the first dielectric layer is in contact with the second end of the semiconductor layer. The structure further includes a contact etch stop layer disposed on and in contact with the first dielectric layer and an interlayer dielectric layer disposed on and in contact with the contact etch stop layer.
    Type: Application
    Filed: January 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Chih-Hung HSIEH
  • Publication number: 20240113165
    Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Chun-Sheng Liang, Chih-Hao Chang, Jhon Jhy Liaw
  • Publication number: 20240113121
    Abstract: Semiconductor devices are provided. A semiconductor device includes a first well region having a first conductivity type, a second well region having a second conductivity type, a cell, and a pickup tap cell. The cell includes a first forksheet structure. The first forksheet structure includes a first transistor formed over the first well region, a second transistor formed over the second well region, and a first wall structure disposed on and extending along an interface between the first and second well regions. The first transistor and the second transistor are disposed on opposite sides of the first wall structure. The pickup tap cell includes a nanosheet structure. The nanosheet structure includes a pickup transistor formed over the second well region. Source/drain features of the first transistor and the pickup transistor have the second conductivity type, and source/drain features of the second transistor have the first conductivity type.
    Type: Application
    Filed: February 16, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng TSAI, Ta-Chun LIN
  • Publication number: 20240105722
    Abstract: A semiconductor device is provided. The semiconductor includes a plurality of semiconductor components and at least two dielectric walls disposed among the semiconductor components. Two of the dielectric walls, which are adjacent, extended along one direction or disposed at two sides of a device isolation, have varied wall widths or offset.
    Type: Application
    Filed: January 20, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ta-Chun LIN
  • Publication number: 20240105772
    Abstract: A device includes a substrate, a first nanostructure device, a second nanostructure device, a dielectric fin, an isolation structure, and first and second dielectric gate structures. The substrate has a first device region, a second device region, and a connecting region. The first nanostructure device is over the first device region. The second nanostructure device is over the second device region. The dielectric fin is over the first device region and the connecting region and is in contact with a gate structure of the first nanostructure device. The isolation structure is over the second device region and is in contact with the second nanostructure device and the dielectric fin. The first dielectric gate structure is over the substrate and between the first device region and the connecting region. The second dielectric gate structure is over the substrate and between the second device region and the connecting region.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ta-Chun LIN
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240088278
    Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Chun-Wing YEUNG, Chih-Hao CHANG
  • Publication number: 20240079500
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first horizontal nanostructures formed over a substrate, and a plurality of second horizontal nanostructures adjacent to the first horizontal nanostructures. The semiconductor structure includes a dielectric wall formed between the first horizontal nanostructures and the second horizontal nanostructures. The semiconductor structure also includes a vertical nanostructure between the dielectric wall and the first horizontal nanostructures, and the vertical nanostructure is connected to and in direct contact with the dielectric wall. The semiconductor structure includes a gate structure surrounding the first horizontal nanostructures, the second horizontal nanostructures and the vertical nanostructure.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Jhon-Jhy LIAW