Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a first S/D structure formed adjacent to the first gate structure. The semiconductor structure includes a second gate structure formed over the second nanostructures along the second direction, and a second S/D structure formed adjacent to the second gate structure. The semiconductor structure includes a dielectric wall structure formed along the first direction. The dielectric wall structure includes a first portion between the first S/D structure and the second S/D structure and a second portion between the first gate structure and the second gate structure.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a fin spacer layer adjacent to the S/D structure. The bottom surface of the fin spacer layer is lower than a bottom surface of the S/D structure.

Abstract: A semiconductor structure includes a first semiconductor device formed over a substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature.

Abstract: A semiconductor device includes a first channel region, a second channel region, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a contact etch stop layer, and an interlayer dielectric layer. The gate structure is across the first channel region and the second channel region. The first source/drain epitaxial structure is on a side of the first channel region. The second source/drain epitaxial structure is on a side of the second channel region. The contact etch stop layer surrounds the first source/drain epitaxial structure and the second source/drain epitaxial structure. A first portion of the contact etch stop layer over the first source/drain epitaxial structure is thicker than a second portion of the contact etch stop layer over the second source/drain epitaxial structure. The interlayer dielectric layer is over the contact etch stop layer.

Abstract: An integrated circuit and a formation method thereof are provided. The integrated circuit includes: an active structure, formed on a semiconductor substrate, and extending along a first lateral direction; first and second gate lines, extending along a second lateral direction on the semiconductor substrate, and crossing the active structure; an isolation wall, extending along the second lateral direction between the first and second gate lines, and cutting through the active structure; a first source/drain contact, extending along the second lateral direction between the first gate line and the isolation wall, and crossing the active structure; and a first source/drain via, disposed on the first source/drain contact, and laterally extending along the first direction to overlap the isolation wall.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming a first gate stack and a second gate stack wrapped around the nanostructure stack. The method includes forming a first source/drain structure in the nanostructure stack and between the first gate stack and the second gate stack. The method includes removing the second gate stack, the nanostructure stack and the fin under the second gate stack to form a trench passing through the nanostructure stack and the fin. The method includes forming a dielectric isolation structure in the trench. The method includes removing the first gate stack and the first nanostructure. The method includes forming a third gate stack wrapped around the second nanostructure. The method includes forming a first contact structure over the first source/drain structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate. The fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers and forming multiple inner spacers covering the side surfaces of the sacrificial layers. The method further includes recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed and partially removing the inner spacers so that each of the inner spacers becomes thinner. In addition, the method includes forming an epitaxial structure on the side surfaces of the semiconductor layers.

Abstract: A method for forming a semiconductor device structure includes forming fin structures over a substrate. The method also includes depositing an isolation material surrounding the fin structures. The method also includes forming a dummy gate structure across the fin structure. The method also includes growing source/drain epitaxial structures over opposite sides of the dummy gate structure. The method also includes removing the dummy gate structure. The method also includes recessing the isolation material after removing the dummy gate structure. The method also includes forming a gate structure over the isolation material.

Abstract: A semiconductor device, a semiconductor chip and manufacturing methods thereof are provided. The semiconductor device includes: channel structures, vertically spaced apart from one another; a gate structure, intersecting the channel structures and wrapping around each of the channel structures; source/drain structures, in lateral contact with the channel structures from opposite sides of the channel structures; and protection structures, separately disposed along a bottom surface of the gate structure, wherein the channel structures are located between the protection structures, and the protection structures comprise a semiconductor material.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (S/D) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an isolation structure formed over a substrate, and first nanostructures formed over an isolation structure along a first direction. The semiconductor includes second nanostructures adjacent to the first nanostructure along the first direction. The semiconductor also includes a dielectric wall between the first nanostructures and the second nanostructures, and the dielectric wall includes a low-k dielectric material. The dielectric wall is in direct contact with the first nanostructures and the second nanostructures, and a top surface of the dielectric wall is higher than a top surface of the isolation structure. The semiconductor includes a gate structure formed over the first nanostructures along a second direction, and a cutting structure formed over the dielectric wall. The gate structure is divided into two portions by the cutting structure.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples. This enables the performance of a plurality of types of electronic devices on the same semiconductor substrate to be increased.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes semiconductor nanosheets vertically stacked upon one another and disposed above a semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, and source/drain regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions, and a topmost semiconductor nanosheet most distanced from the semiconductor substrate is thinner than an underlying semiconductor nanosheet between the topmost semiconductor nanosheet and the semiconductor substrate.

Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a source/drain feature over a substrate; a metal gate structure extending lengthwise along a first direction and adjacent to the source/drain feature; a gate isolation structure extending lengthwise along a second direction substantially perpendicular to the first direction, and a source/drain contact electrically coupled to the source/drain feature and including a first portion directly above the source/drain feature and a second portion extending from the first portion along the first direction. In embodiments, the gate isolation structure divides the metal gate structure into two isolated portions. In embodiments, the first portion has a first width along the second direction and the second portion has a second width along the second direction, the first width being greater than the second width.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming, over a substrate, a stack extending along a first lateral direction, wherein the stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately arranged on top of one another; overlaying a first portion of the stack with a first gate structure, wherein the first gate structure extends along a second lateral direction perpendicular to the first lateral direction; removing a second portion of the stack through a first etching process, wherein the second portion was disposed next to the first portion along the first lateral direction; and removing a third portion of the stack through a second etching process, wherein the third portion was disposed next to a lower part of the second portion.

Abstract: A semiconductor structure includes a substrate, a vertical stack including nanostructures, and a gate structure wrapping around each of the nanostructures. The nanostructures are suspended and vertically arranged over the substrate. The gate structure includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The semiconductor structure further includes inner spacers and gate spacers. The inner spacers are formed on opposite sides of the gate structure, between the nanostructures, and separating the nanostructures from each other. The gate spacers are formed on the opposite sides of the gate structure and over a topmost one of the nanostructures. The gate dielectric layer includes a first portion formed on the nanostructures and a second portion extending from the first portion. The first portion and the second portion have a first thickness and a second thickness, respectively. The first thickness is greater than the second thickness.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and first nanostructures formed over the isolation structure along a first direction. The semiconductor device structure includes a first gate structure formed over the first nanostructures along a second direction, and a first dielectric structure formed adjacent to the first nanostructures along the first direction. The first dielectric structure is in direct contact with the first nanostructures. The semiconductor device structure includes a second gate structure formed adjacent to the first gate structure, and the second gate structure is formed directly over the first dielectric structure.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures and the second nanostructures along a second direction. Each of the first nanostructures has a first width along the second direction, each of the second nanostructures has a second width along the second direction, and the first width is smaller than the second width. The semiconductor structure includes a first base fin structure below the first nanostructures, and the first base fin structure has a first base width. The first base width is greater than the first width.