Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Abstract: A method of fabricating a semiconductor device includes providing a partially-fabricated semiconductor device including a dummy gate structure disposed over a semiconductor layer stack. In some embodiments, the method further includes removing the dummy gate structure and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench. In some examples, the method further includes forming one or more refill layers in a bottom portion of the trench and forming one or more refill layers in a top portion of the trench over the bottom portion of the trench. In some embodiments, the one or more refill layers in the top and bottom portions of the trench respectively define top and bottom portions of an isolation structure. In some examples, at least one refill layer of respective ones of the top and bottom portions of the isolation structure have a different material composition.

Abstract: A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapped around the first nanostructures. The structure also includes first source/drain epitaxial structures formed over opposite sides of the first nanostructures. The structure also includes first inner spacers formed between the first gate structure and the first source/drain epitaxial structures. The structure also includes second nanostructures formed over the first nanostructures. The structure also includes a second gate structure wrapped around the second nanostructures. The structure also includes second source/drain epitaxial structures formed over opposite sides of the second nanostructures. The structure also includes second inner spacers formed between the second gate structure and the second source/drain epitaxial structures. The first inner spacers and the second inner spacers have different widths.

Abstract: A method of forming a semiconductor structure includes forming a fin structure over a substrate; forming first and second source/drain trenches in the fin structure; forming first and second SiGe layers in the first and second source/drain trenches, respectively; and forming first and second source/drain features over the first and second SiGe layers in the first and second source/drain trenches, respectively. The method further includes forming a first interlayer dielectric (ILD) layer on a backside of the substrate; etching the first ILD layer and the substrate to form a first opening that exposes the first SiGe layer; removing the first SiGe layer to form a second opening that exposes the first source/drain feature; and depositing a conductive material in the first and second openings to form a first source/drain contact. The lateral dimensions of the first opening are greater than those of the second opening.

Abstract: A semiconductor structure includes a first transistor, a second transistor, and a gate structure. The first transistor includes first nanostructures and first source/drain features. The first nanostructures are spaced apart from each other in a Z-direction. The first source/drain features are on opposite sides of the first nanostructures in an X-direction. The second transistor includes second nanostructures and second source/drain features. The second nanostructures are spaced apart from each other in the Z-direction. The second nanostructures are over the first nanostructures. The second source/drain features are on opposite sides of the second nanostructures in the X-direction. The second source/drain features are over the first source/drain features. The gate structure wraps around the first nanostructures and the second nanostructures. A thickness of middle portions of the first nanostructures is greater than a thickness of middle portions of the second nanostructures.

Abstract: A semiconductor structure includes a first semiconductor device formed in a first device region of a substrate. The first semiconductor device includes a first gate structure comprising a first spacer layer, wherein the first spacer layer has a first thickness. The first semiconductor device also includes a first conductive feature disposed over a first source/drain feature, and the first conductive feature has a first width. The semiconductor structure further includes a second semiconductor device formed in a second device region of the substrate. The second semiconductor device includes a second gate structure comprising a second spacer layer, wherein the second spacer layer has a second thickness different than the first thickness. The second semiconductor device also includes a second conductive feature disposed over a second source/drain feature, and the second conductive feature has a second width different than the first width.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes forming a dummy gate stack extending across a portion of the fin structure and forming gate spacers over sidewalls of the dummy gate stack. The gate spacers extend across portions of the fin structure. The method further includes removing the dummy gate stack to form a trench exposing the portion of the fin structure and trimming the semiconductor layers exposed by the trench. Each of the semiconductor layers covered by the gate spacers becomes wider than each of the semiconductor layers that is trimmed. In addition, the method includes removing the sacrificial layers and forming a metal gate stack wrapped around the semiconductor layers.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a contact structure formed on the S/D structure, and a portion of the contact structure is embedded in the S/D structure, and the contact structure has a T-shaped structure.

Abstract: A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures formed over the substrate along the first direction. The semiconductor structure includes a first gate structure formed over the first nanostructures along a second direction, and a first S/D structure formed adjacent to the first gate structure. The semiconductor structure includes a second gate structure formed over the second nanostructures along the second direction, and a second S/D structure formed adjacent to the second gate structure. The semiconductor structure includes a dielectric wall structure formed along the first direction. The dielectric wall structure includes a first portion between the first S/D structure and the second S/D structure and a second portion between the first gate structure and the second gate structure.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a fin spacer layer adjacent to the S/D structure. The bottom surface of the fin spacer layer is lower than a bottom surface of the S/D structure.

Abstract: A semiconductor structure includes a first semiconductor device formed over a substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature.

Abstract: A semiconductor device includes a first channel region, a second channel region, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a contact etch stop layer, and an interlayer dielectric layer. The gate structure is across the first channel region and the second channel region. The first source/drain epitaxial structure is on a side of the first channel region. The second source/drain epitaxial structure is on a side of the second channel region. The contact etch stop layer surrounds the first source/drain epitaxial structure and the second source/drain epitaxial structure. A first portion of the contact etch stop layer over the first source/drain epitaxial structure is thicker than a second portion of the contact etch stop layer over the second source/drain epitaxial structure. The interlayer dielectric layer is over the contact etch stop layer.

Abstract: An integrated circuit and a formation method thereof are provided. The integrated circuit includes: an active structure, formed on a semiconductor substrate, and extending along a first lateral direction; first and second gate lines, extending along a second lateral direction on the semiconductor substrate, and crossing the active structure; an isolation wall, extending along the second lateral direction between the first and second gate lines, and cutting through the active structure; a first source/drain contact, extending along the second lateral direction between the first gate line and the isolation wall, and crossing the active structure; and a first source/drain via, disposed on the first source/drain contact, and laterally extending along the first direction to overlap the isolation wall.

Abstract: Transistors of different types of electronic devices on the same semiconductor substrate are configured with different transistor attributes to increase the performance of the different types of electronic devices. Fin height, shallow source drain (SSD) height, source or drain width, and/or one or more other transistor attributes may be co-optimized for the different types of electronic devices by various semiconductor manufacturing processes such as etching, lithography, process loading, and/or masking, among other examples.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming a first gate stack and a second gate stack wrapped around the nanostructure stack. The method includes forming a first source/drain structure in the nanostructure stack and between the first gate stack and the second gate stack. The method includes removing the second gate stack, the nanostructure stack and the fin under the second gate stack to form a trench passing through the nanostructure stack and the fin. The method includes forming a dielectric isolation structure in the trench. The method includes removing the first gate stack and the first nanostructure. The method includes forming a third gate stack wrapped around the second nanostructure. The method includes forming a first contact structure over the first source/drain structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a gate stack over the first fin and the second fin. The method includes forming a first spacer over gate sidewalls of the gate stack and a second spacer adjacent to the second fin. The method includes partially removing the first fin and the second fin. The method includes forming a first source/drain structure and a second source/drain structure in the first trench and the second trench respectively. A first ratio of a first height of the first merged portion to a second height of a first top surface of the first source/drain structure is greater than or equal to about 0.5.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate. The fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner. The method also includes partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers and forming multiple inner spacers covering the side surfaces of the sacrificial layers. The method further includes recessing the semiconductor layers from the side surfaces of the semiconductor layers after the inner spacers are formed and partially removing the inner spacers so that each of the inner spacers becomes thinner. In addition, the method includes forming an epitaxial structure on the side surfaces of the semiconductor layers.

Abstract: A method for forming a semiconductor device structure includes forming fin structures over a substrate. The method also includes depositing an isolation material surrounding the fin structures. The method also includes forming a dummy gate structure across the fin structure. The method also includes growing source/drain epitaxial structures over opposite sides of the dummy gate structure. The method also includes removing the dummy gate structure. The method also includes recessing the isolation material after removing the dummy gate structure. The method also includes forming a gate structure over the isolation material.