Abstract: A method for manufacturing a semiconductor structure includes forming a fin over a substrate in a Z-direction. The fin includes first semiconductor layers and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure extending in a Y-direction and over the fin, forming a first source/drain feature and a second source/drain feature on opposite sides of the dummy gate structure in an X-direction, removing the dummy gate structure and the first semiconductor layers in the fin to form a gate trench, and forming a gate structure in the gate trench. The gate structure wraps around the second semiconductor layers. The method further includes forming a via in contact with a bottom surface of the first source/drain feature. The bottom surface of the first source/drain feature is lower than a bottom surface of the second source/drain feature.

Abstract: A method of forming a semiconductor device includes the following steps. A substrate is patterned to form a fin structure. The fin structure is recessed to form a recess in the fin structure. An epitaxial source/drain region is grown from the recess. A first silicide layer is formed on the epitaxial source/drain region. A first portion of the first silicide layer is thinned, while leaving a second portion of the first silicide layer un-thinned. A metal contact is formed in contact with the thinned first portion of the first silicide layer.

Abstract: A device includes a first transistor, a second transistor, and a dielectric wall. The first transistor includes first semiconductor channel layers, a first gate structure, and first source/drain structures on opposite sides of the first gate structure. The second transistor includes second semiconductor channel layers, a second gate structure, and second source/drain structures on opposite sides of the second gate structure. The dielectric wall includes a first sidewall abutting side surfaces of the first semiconductor channel layers in a first cross-sectional view taken along a longitudinal axis of the first gate structure, the first sidewall of the dielectric wall also abutting side surfaces of second semiconductor channel layers in a second cross-sectional view taken along a longitudinal axis of the second gate structure, in which in a top view, the first sidewall of the dielectric wall has a stepped profile.

Abstract: A semiconductor device includes a dielectric wall, an isolation structure, first and second semiconductor channels, and a gate structure. The dielectric wall is on a substrate and extending along a first direction from a top view. The isolation structure is in the substrate and having a top surface lower than that of the dielectric wall. The first and second semiconductor channels are respectively on opposite first and second sides of the dielectric wall. The gate structure extends across the first and second semiconductor channels along a second direction different from the first direction from the top view. From the top view the gate structure comprises a first profile over the first semiconductor channels and a second profile over the isolation structure, the first profile has a first width at the first side of the dielectric wall, and the first width is greater than a width of the second profile.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, wherein the first device includes a first fin structure and a first S/D structure formed over the first fin structure. The semiconductor device structure includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure also includes a second S/D structure formed over the second nanostructures, and the second S/D structure is directly above or below the first S/D structure.

Abstract: A semiconductor device includes a transistor structure disposed on a first side of a substrate and a back-side via structure disposed on a second side of the substrate opposite to the first side. The transistor structure includes a pair of epitaxial structures and a channel feature extending in a channel length direction to be disposed between the epitaxial structures. The channel feature has a width in a channel width direction transverse to the channel length direction. The back-side via structure extends through the substrate so as to be connected to a bottom surface and a sidewall surface of a lower portion of a corresponding one of the epitaxial structures. The back-side via structure has a width in the channel width direction, which is greater than the width of the channel feature.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, an S/D feature disposed over the semiconductor fin, and a first dielectric fin and a second dielectric fin disposed over the substrate, where the semiconductor fin is disposed between the first dielectric fin and the second dielectric fin, where a first air gap is enclosed by a first sidewall of the epitaxial S/D feature and the first dielectric fin, and where a second air gap is enclosed by a second sidewall of the epitaxial S/D feature and the second dielectric fin.

Abstract: A semiconductor structure includes a first device unit and a second device unit, each of which includes channel features spaced apart from each other, and a dielectric wall disposed between the first and second device units. The dielectric wall includes a first part which includes a plurality of first portions that are in direct contact with the channel features of the first device unit, and a second part which includes a plurality of second portions that are in direct contact with the channel features of the second device unit. At least one of the first and second parts carries positive or negative charges.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Abstract: A first source/drain structure is disposed over a substrate. A second source/drain structure is disposed over the substrate. An isolation structure is disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and a first sidewall of the isolation structure form a first interface that is substantially linear. The second source/drain structure and a second sidewall of the isolation structure form a second interface that is substantially linear. A first source/drain contact surrounds the first source/drain structure in multiple directions. A second source/drain contact surrounds the second source/drain structure in multiple directions. The isolation structure is disposed between the first source/drain contact and the second source/drain contact.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a portion of the first contact structure is lower than a top surface of the first S/D structure. The semiconductor structure includes a second contact structure formed over a second side of the first S/D structure, and the second contact structure is in direct contact with the first contact structure.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A semiconductor structure includes a substrate, a dielectric wall, and two device units. The dielectric wall has two side surfaces opposite to each other. The two device units are respectively formed at the two side surfaces of the dielectric wall. Each of the device units includes channel features, a gate feature and a dielectric filler unit. The channel features are disposed on a corresponding one of the side surfaces of the dielectric wall, and spaced apart from each other. The gate feature is formed around the channel features and disposed on the corresponding one of the side surfaces of the dielectric wall. The dielectric filler unit includes a plurality of first dielectric fillers, each of which is disposed between the dielectric wall and a corresponding one of the channel features. The first dielectric fillers have a dielectric constant greater than that of the dielectric wall.

Abstract: Semiconductor structures and processes are provided. A semiconductor structure of the present disclosure includes a first base portion and a second base portion extending lengthwise along a first direction, a first source/drain feature disposed over the first base portion, a second source/drain feature disposed over the second base portion, a center dielectric fin sandwiched between the first source/drain feature and the second source/drain feature along a second direction perpendicular to the first direction, and a source/drain contact disposed over the first source/drain feature, the second source/drain feature and the center dielectric fin. A portion of the source/drain contact extends between the first source/drain feature and the second source/drain feature along the second direction.

Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a semiconductor layer disposed over a substrate, and the semiconductor layer has a first end and a second end opposite the first end. The structure further includes an epitaxial feature disposed over the substrate, and the epitaxial feature is electrically connected to the first end of the semiconductor layer. The structure further includes a first dielectric layer disposed over the substrate, and the first dielectric layer is in contact with the second end of the semiconductor layer. The structure further includes a contact etch stop layer disposed on and in contact with the first dielectric layer and an interlayer dielectric layer disposed on and in contact with the contact etch stop layer.

Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.

Abstract: Semiconductor structures and processes are provided that include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure may be formed on a dielectric wall from which nanostructure channel regions extend. The second gate isolation structure may be formed on a shallow trench isolation feature. The height of the first gate isolation structure is less than the height of the second gate isolation structure. The composition of the first gate isolation structure may be different than the composition of the second gate isolation structure. In some implementations, the first gate isolation structure is formed concurrently with gate spacers.

Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.