Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.

Abstract: In one example described, a data sequence generator for use in spread spectrum communications includes one or more read-only memories (ROMs) which have first and second spreading sequences stored therein. The first spreading sequence is associated with a first mode of communication, whereas the second spreading sequence is associated with a second mode of communication. The one or more ROMs have inputs to receive counter values and outputs for serially providing, responsive to the counter values, sequence data from either the first spreading sequence or the second spreading sequence depending on which mode of communication is selected. The first and the second spreading sequences may be unique to, for example, IS-95 and IS-2000 standards, respectively.

Abstract: An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode.

Abstract: A VCO modulator controller including a ROM memory storing a number of waveform maps, a counter coupled to the ROM memory and capable of developing a sequence of ROM addresses, a temporal bit generator responsive to a data stream to develop a next bit Nb, a current bit Cb, and a past bit Pb, control circuitry developing a digital waveform signal from selected waveform maps in the ROM memory using the Nb, Cb, and Pb bits and the sequence of ROM memory outputs, and a DAC that converts the digital waveform signal to an analog VCO control signal that encodes said data stream.

Abstract: A programmable device and methods for making the programmable device are provided. The programmable device includes a link metallization line with an oxide layer defined above the link metallization line. A via hole is patterned in the oxide layer which defines a path to the link metallization line. A programming metallization line is defined over the oxide layer. The programming metallization line has an overlap portion that lies over the via hole. The overlap portion is configured to melt into the via hole to define a programming link between the link metallization line and the programming metallization line. In one example, the melting is accomplished by implementing a laser that can direct laser energy toward a desired programmable device to achieve the desired programming.

Abstract: A method of generating one or more pseudorandom noise (PN) sequences for use in spread spectrum communications includes the steps of providing data at an input of memory which stores bits associated with a pseudorandom noise (PN) sequence: changing the data; and for each of a plurality of changes of the data, providing a selected PN bit of the PN sequence at an output of the memory based on the data.

Abstract: A digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. In one embodiment, the present invention relates to a digital phase shift amplification and detection system and method. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal. The detection circuit is coupled to clock signals that are out of phase with the clock signal that triggers the metastable flip flop in the phase shift amplifier.

Abstract: A method of using a gaseous environment providing improved control of CMP process. In one embodiment, the method comprises several steps. One step involves placing a semiconductor wafer onto a polishing pad of a CMP machine. A subsequent step dispenses a slurry onto the polishing pad. Another step provides a blanket of gas that displaces the ambient atmosphere surrounding the semiconductor wafer. In another step, the blanket of gas is maintained around the semiconductor wafer during the CMP operation.

Abstract: A system and method is disclosed for enhancing an optical lithography process by capturing light diffracted from a mask having features to be exposed onto a wafer. In one embodiment, a system of the present invention has in place a mask, a wafer and a reduction lens such that the reduction lens is placed between the mask and the wafer in order to direct and expose the mask's features onto the wafer. Furthermore, a reflective member is disposed proximate to the reduction lens. In order to achieve finer resolution of the mask image on the wafer, this reflective member captures diffracted light diffracting beyond the reduction lens and redirects the diffracted light to pass through the reduction lens such that the diffracted light is redirected onto the wafer. In so doing, the reflective member resolves the mask image on the wafer in more detail than is possible by an optical lithography process using no such reflective member.

Abstract: A dynamic error correction system for a digital data transmission system. A transmitter adapted to encode user data into a signal is included within the system. A receiver receives the signal and decodes the user data encoded thereon. The signal is transmitted from the transmitter to the receiver via a communications channel. A data type detector is coupled to the transmitter. The data type detector is adapted to detect a data type of the user data being coupled to the transmitter for transmission via the communications channel. A processor is coupled to the transmitter and is adapted to implement at least a first error correction process and a second error correction process for the transmitter, wherein the second error correction process is of a higher capability than the first error correction process.

Abstract: The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas. Specifically, one embodiment of the present invention utilizes a dry abrasive polishing pad to abrade the desired surface of the semiconductor wafer within a vacuum planarization chamber. As a result of abrading the surface, the abrasive polishing pad breaks the chemical bonds of a thin layer of the dielectric surface material.

Abstract: A package for a semiconductor device and a method for packaging a semiconductor device are disclosed. The semiconductor package uses a tape which allows for the production of packaged semiconductor devices having different contact patterns. The contact pattern is configured to the required pin contact pattern by varying the number and placement of balls on the bottom of the tape. In one embodiment, the tape includes bonding pads and an array of contact pads. Each bonding pad is connected to one of the contact pads, and an opening is disposed in the tape below each contact pad. A semiconductor device is connected to the tape and is electrically connected to the bonding pads. The semiconductor device is then sealed on the top and sides by a plastic top which attaches to the tape. Balls are then selectively attached to the tape such that they electrically connect to select contact pads so as to form a desired contact pattern.

Abstract: A method and system for cache replacement among configurable cache sets. In one embodiment, the present invention identifies a cache location corresponding to uncached data received from main memory and determines a data type for the uncached data. The present invention then examines the cache location in at least one of the configurable cache sets which is configured for the data type of the uncached data. Provided that the cache location of at least one of the configurable cache sets is not occupied by valid data and that the same configurable cache set is configured for the data type of the uncached data, the present invention stores the uncached data into that configurable cache set at the cache location without displacing valid data therein.

Abstract: An optimized CPU-memory high bandwidth multibus structure simultaneously supporting design reusable blocks. A system in accordance with the present invention communicatively couples the internal components (e.g., CPU, memory, etc.) and peripheral devices (e.g., display, keyboard, etc.) of a computer system by dividing the components into two logical subdivisions. One subdivision includes the memory and CPU(s) of the computer system while the other subdivision includes the remaining components. In accordance with the present invention, each subdivision of components is interconnected to the other components of its subdivision by a bus scheme. Both subdivision bus schemes are interconnected by circuitry referred to as a bridge, which enables them to intercommunicate. As such, the components connected to the separate subdivision bus schemes are able to intercommunicate.

Abstract: A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit die. The first and second interconnect elements are couple via an interconnect link. An anti-reflective layer is disposed on a surface above the interconnect link. The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link in order to fuse the interconnect link, and thereby repair the integrated circuit die.

Abstract: A method and system thereof for efficiently computing the number of dies per wafer and the corresponding number of stepper shot counts. Dimensions for a die and the size of the wafer are received. The dimensions comprise a die element size that is a function of a scribe lane width, a guard ring width, an input/output pad area, and a length and a width of the die. A die count lookup table is selected for the specified wafer size and used to determine the die count corresponding to the die element size. In a similar manner, a stepper shot count lookup table is selected for the specified wafer size and used to determine the stepper shot count corresponding to the die element size. The axes of the die count and stepper shot count lookup tables are incremented by varying amounts; for example, the increments in one portion of the lookup tables are smaller (finer), and in another portion the increments are larger (grosser).

Abstract: The present invention includes integrated circuitry, an interface circuit of an integrated circuit device, cascode circuitry, method of protecting an integrated circuit, method of operating integrated circuitry, and method of operating cascode circuitry. One aspect of the present invention provides integrated circuitry including a driver adapted to couple with a pad and internal circuitry of an integrated circuit device, the driver includes a first transistor coupled with the pad; cascode circuitry including a second transistor coupled with the pad and a third transistor coupled with ground, the cascode circuitry configured to remain in an untriggered state during the presence of stress currents at the pad; and protection circuitry intermediate the pad and ground and configured to shunt stress currents from the pad to ground.

Abstract: The present invention is a method of suppressing etchrate of quartz hardware in semiconductor processing chamber during plasma-enhanced cleaning. In one embodiment, the method of the present invention includes the steps of: (a) introducing a mixture of fluorocarbon gas, oxygen, and water vapor into the chamber; and (b) activating the mixture to form a quartz-safe plasma cleaning gas. According to the present invention, the presence of water vapor substantially suppresses etching of quartz hardware. Etchrate of the polymer contaminants, however, is substantially unaffected. In one embodiment of the invention, the fluorocarbon gas includes CF4, and, water vapor is introduced at a rate of at least 60 standard cubic centimeters per minute (SCCM).

Abstract: An interface and process for re-ordering data transactions between a master device and a target device. The present invention applies to target devices that interface to master devices such that both masters and slaves are capable of handling the re-ordering of outstanding requests. In such an interface where data transactions can be in any order, certain events may occur that force the reordering to be limited to either before or after the event. These events, also referred to as synchronizing events herein, require that transactions sampled before the event must be completed before transactions sampled after the event are completed. The present invention is capable of handling such synchronizing events while maximizing reordering to gain maximum performance benefits.