Instruction buffer organization method and system

Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format. The instruction buffer circuit prepares the variable-length instructions for decoding by converting the instruction alignment from a memory alignment to an instruction alignment on the basis of the instruction length indication. The instruction buffer circuit also assists the preparation of variable-length instructions for decoding of multiple instructions in parallel by facilitating a conversion of the instruction length indication to an instruction pointer.

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Claims

1. An apparatus for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution comprising:

an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element;
a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the predecode storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and
a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel.

2. An apparatus according to claim 1 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; and
a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length.

3. An apparatus according to claim 1 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache including a sixteen instruction byte storage for storing sixteen bytes of the variable-length instructions, and sixteen multiple-bit predecode element storage corresponding to the sixteen instruction byte storage; and
a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length and storing the instruction length in an instruction byte storage.

4. An apparatus according to claim 1 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; and
a plurality of instruction multiplexers respectively coupled to the plurality of decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment.

5. An apparatus according to claim 1 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit;
a plurality of instruction multiplexers respectively coupled to the plurality of decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment; and
a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions, the program count being combined with the predecode information indicative of instruction length to designate the first instruction byte location of a variable-length instruction.

6. An apparatus according to claim 1 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache;
a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and
an instruction lookahead logic circuit coupled to the instruction buffer, the program counter and the plurality of decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the decoders decode variable-length instructions in parallel.

7. An apparatus according to claim 1 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache;
a plurality of instruction multiplexers respectively coupled to the plurality of decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment;
a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and
an instruction lookahead logic circuit coupled to the instruction buffer, the plurality of instruction multiplexers, the program counter and the plurality of decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the decoders decode variable-length instructions in parallel.

8. An apparatus according to claim 7 wherein the instruction lookahead logic circuit further comprises:

a circuit for determining whether the predecode information is valid based on the predecode information indicative of instruction length.

9. An apparatus for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution comprising:

an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element;
a predecoder coupled to the instruction cache for accessing the variable-length instructions, assigning predecode information indicative of instruction length to the predecode storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction, and designating the variable-length instructions as first-type and second-type variable-length instructions based on the information indicative of instruction length;
a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and
a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of first type decoders and a second type decoder, the first type decoders for receiving a plurality of first-type variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of first-type variable-length instructions in parallel, the second type decoder for decoding a second-type variable length instruction.

10. An apparatus according to claim 9 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache for holding first-type and second-type variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; and
a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length.

11. An apparatus according to claim 9 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache including a sixteen instruction byte storage for storing sixteen bytes of the variable-length instructions, and sixteen multiple-bit predecode element storage corresponding to the sixteen instruction byte storage; and
a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length and storing the instruction length in an instruction byte storage.

12. An apparatus according to claim 9 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; and
a plurality of instruction multiplexers respectively coupled to the plurality of first type decoders, the instruction multiplexers for converting the first-type variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment.

13. An apparatus according to claim 12 wherein one instruction multiplexer of the plurality of instruction multiplexers is coupled to the second type decoder and coupled to one respective first type decoder.

14. An apparatus according to claim 9 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit;
a plurality of instruction multiplexers respectively coupled to the plurality of first type decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment; and
a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions, the program count being combined with the predecode information indicative of instruction length to designate the first instruction byte location of a variable-length instruction.

15. An apparatus according to claim 14 wherein one instruction multiplexer of the plurality of instruction multiplexers is coupled to the second type decoder and coupled to one respective first type decoder.

16. An apparatus according to claim 9 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache;
a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and
an instruction lookahead logic circuit coupled to the instruction buffer, the program counter and the plurality of first type decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the first type decoders decode variable-length instructions in parallel.

17. An apparatus according to claim 9 wherein the buffer circuit further comprises:

an instruction buffer coupled to the instruction cache;
a plurality of instruction multiplexers respectively coupled to the plurality of first type decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment;
a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and
an instruction lookahead logic circuit coupled to the instruction buffer, the plurality of instruction multiplexers, the program counter and the plurality of first type decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the first type decoders decode variable-length instructions in parallel.

18. An apparatus according to claim 17 wherein the instruction lookahead logic circuit further comprises:

a circuit for determining whether the predecode information is valid based on the predecode information indicative of instruction length.

19. An apparatus according to claim 9 further comprising:

a branch target buffer coupled to the instruction cache and the buffer circuit, the branch target buffer for storing a plurality of target instructions, the branch target buffer and the instruction cache alternatively supplying variable-length instructions to the buffer circuit.

20. A method of receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution, comprising the steps of:

receiving the plurality of variable-length instructions from the instruction source;
storing the variable-length instructions in a plurality of instruction storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment;
accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
storing predecode information corresponding to the variable-length instructions in a plurality of predecode storage elements corresponding to the plurality of instruction storage elements;
holding the variable-length instructions and the corresponding predecode information in a buffer;
converting the variable length instructions from the memory alignment to an instruction alignment;
designating the first instruction byte location of a variable-length instruction;
receiving the variable-length instructions in the instruction alignment at a plurality of decoders, each variable-length instruction beginning at the designated first instruction byte locations; and
decoding the plurality of variable-length instructions in parallel.

21. A method according to claim 20, further comprising the steps of:

supplying a program count representing an initial point for decoding instructions; and
deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the decoders decode variable-length instructions in parallel.

22. A method of receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution, comprising the steps of:

receiving the plurality of variable-length instructions from the instruction source;
storing the variable-length instructions in a plurality of instruction storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment;
accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
storing predecode information corresponding to the variable-length instructions in a plurality of predecode storage elements corresponding to the plurality of instruction storage elements;
holding the variable-length instructions and the corresponding predecode information in a buffer;
converting the variable length instructions from the memory alignment to an instruction alignment;
designating the first instruction byte location of a variable-length instruction;
designating the variable-length instructions as first-type and second-type variable-length instructions based on the information indicative of instruction length;
receiving the variable-length instructions in the instruction alignment at a plurality of decoders including a plurality of first type decoders and a second type decoder, the first type decoders for receiving a plurality of first-type variable-length instructions, each variable-length instruction beginning at the designated first instruction byte locations;
decoding the plurality of first-type variable-length instructions in parallel; and
decoding a second-type variable length instruction.

23. A computer system comprising:

a memory subsystem which stores data and instructions; and
a processor operably coupled to access the data and instructions stored in the memory subsystem, wherein the processor includes a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution, the circuit including:
an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element;
a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the predecode storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and
a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel.

24. The computer system of claim 23, wherein the processor and the memory subsystem are components of a motherboard.

25. The computer system of claim 24, wherein the motherboard further comprises a backplane bus operably connected to the processor, and wherein the computer system further comprises one or more devices on cards connected to the motherboard via the backplane bus.

26. The computer system of claim 23, further comprising a parallel device interface operably coupled to the processor.

27. The computer system of claim 26, further comprising a printer connected to the processor via the parallel interface.

28. The computer system of claim 23, further comprising a serial device interface operably coupled to the processor.

29. The computer system of claim 28, further comprising a modem connected to the processor via the serial interface.

30. The computer system of claim 23, further comprising a graphics adapter operably coupled to the processor.

31. The computer system of claim 30, further comprising a video display connected to the processor via the graphics adapter.

32. The computer system of claim 23, further comprising a local area network adapter operably coupled to the processor.

33. The computer system of claim 32, further comprising a network of devices connected to the processor via the network adapter.

34. The computer system of claim 23, further comprising a disk controller operably coupled to the processor.

35. The computer system of claim 34, further comprising a hard disk connected to the processor via the disk controller.

36. The computer system of claim 34, further comprising a floppy disk connected to the processor via the disk controller.

37. A network server comprising:

a superscalar processor including a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution including:
an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element;
a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the predecode storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and
a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel;
a memory;
a processor bus coupled between the memory and the superscalar processor;
a local bus and an I/O bus;
first and second bridges, respectively coupling the processor bus to the local bus and the local bus to the I/O bus; and
a LAN adapter coupled to one of the local bus and the I/O bus.

38. A network server, as recited in claim 37, further comprising:

a data storage device coupled to one of the local bus and the I/O bus.

39. A network server, as recited in claim 38, wherein the storage device comprises a hard disk.

40. A network server, as recited in claim 39, wherein the hard disk is selected from the group consisting of an IDE disk, an enhanced IDE disk, an ATA disk, an ESDI disk, and a SCSI disk.

41. A network server, as recited in claim 38, wherein the storage device comprises a tape unit.

42. A network server, as recited in claim 41, wherein the tape unit is selected from the group consisting of an IDE tape unit, an enhanced IDE tape unit, an ATA tape unit, an ESDI tape unit, and a SCSI tape unit.

43. A network server, as recited in claim 38, wherein the storage device comprises a CD-ROM.

44. A network server, as recited in claim 43, wherein the CD-ROM is selected from the group consisting of an IDE CD-ROM, an enhanced IDE CD-ROM, an ATA CD-ROM, an ESDI CD-ROM, and a SCSI CD-ROM.

45. A network server, as recited in claim 38, wherein the storage device comprises a jukebox.

46. A network server, as recited in claim 38, wherein the storage device comprises a RAID.

47. A network server, as recited in claim 38, wherein the storage device comprises a flash memory.

48. A network server, as recited in claim 37, wherein the LAN adapter is selected from the group consisting of a baseband network LAN adapter, a broadband network LAN adapter, a token passing network LAN adapter, a token ring network LAN adapter, a 10base-T network LAN adapter, and an ethernet LAN adapter.

49. A network server, as recited in claim 37, wherein the local bus comprises a VL bus.

50. A network server, as recited in claim 37, wherein the local bus comprises a PCI bus.

51. A network server, as recited in claim 37, wherein the I/O bus is selected from the group consisting of an ISA bus, an EISA bus, a Micro Channel Architecture Bus, and a local bus.

52. A network server, as recited in claim 37, further comprising:

a communications device coupled to one of the local bus and the I/O bus.

53. A network server, as recited in claim 52, wherein the communications device comprises one of a modem, a faxmodem, and an integrated telephony device.

54. A network server, as recited in claim 54, wherein the communications device further comprises a printed circuit card coupled to one of the local bus and the I/O bus via a modular connector.

55. A network server, as recited in claim 54, wherein the communications device is coupled to one of the local bus and the I/O bus via a serial interface.

56. A network server, as recited in claim 37, further comprising:

an I/O device coupled to one of the local bus and the I/O bus.

57. A network server, as recited in claim 56, wherein the I/O device is selected from the group consisting of a text display adapter, a graphics adapter, a 3-D graphics adapter, a SVGA display adapter, an XGA adapter, a display adapter supporting VESA graphics standards, a CGA adapter, an adapter supporting Hercules graphics standards.

58. A network server, as recited in claim 56, wherein the I/O device is selected from the group consisting of a pointing device, a mouse, a trackball, and a keyboard.

59. A network server comprising:

a superscalar processor including a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution including:
an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element;
a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the predecode storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and
a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel; and
a LAN adapter coupled to the superscalar processor.

60. A network server, as recited in claim 59, wherein the LAN adapter is selected from the group consisting of a baseband network LAN adapter, a broadband network LAN adapter, a token passing network LAN adapter, a token ring network LAN adapter, a 10base-T network LAN adapter, and an ethernet LAN adapter.

61. A network server, as recited in claim 59, further comprising a hard disk coupled to the superscalar processor.

62. A network server, as recited in claim 61, wherein the hard disk is selected from the group consisting of an IDE disk, an enhanced IDE disk, an ATA disk, an ESDI disk, and a SCSI disk.

63. A network server, as recited in claim 59, further comprising a tape unit coupled to the superscalar processor.

64. A network server, as recited in claim 63, wherein the tape unit is selected from the group consisting of an IDE tape unit, an enhanced IDE tape unit, an ATA tape unit, an ESDI tape unit, and a SCSI tape unit.

65. A network server, as recited in claim 59, further comprising a CD-ROM coupled to the superscalar processor.

66. A network server, as recited in claim 65, wherein the CD-ROM is selected from the group consisting of an IDE CD-ROM, an enhanced IDE CD-ROM, an ATA CD-ROM, an ESDI CD-ROM, and a SCSI CD-ROM.

67. A network server, as recited in claim 59, further comprising a jukebox coupled to the superscalar processor.

68. A network server, as recited in claim 59, further comprising a RAID coupled to the superscalar processor.

69. A network server, as recited in claim 59, further comprising a flash memory coupled to the superscalar processor.

70. A network server, as recited in claim 59, further comprising a modem coupled to the superscalar processor.

71. A network server, as recited in claim 59, further comprising a faxmodem coupled to the superscalar processor.

72. A network server, as recited in claim 59, further comprising an integrated telephony device coupled to the superscalar processor.

73. A network server, as recited in claim 59, further comprising a display adapter coupled to the superscalar processor, the display adapter selected from the group consisting of a text display adapter, a graphics adapter, a 3-D graphics adapter, a SVGA display adapter, an XGA adapter, a display adapter supporting VESA graphics standards, a CGA adapter, an adapter supporting Hercules graphics standards.

74. A network server, as recited in claim 59, further comprising an I/O device coupled to the superscalar processor, the I/O device selected from the group consisting of a pointing device, a mouse, a trackball, and a keyboard.

75. A multimedia computer system incorporating a processor including an instruction buffer system, the multimedia computer system comprising:

a multimedia performance device;
a multimedia adapter coupled to the multimedia performance device and coupled to the multimedia signal acquisition device, the multimedia adapter including a signal conversion interface for synthesizing and sampling multimedia signals;
an input/output bus coupled to the multimedia adapter for communicating transfers of multimedia data;
a superscalar processor coupled to the input/output bus for processing multimedia data and controlling communication of multimedia data between the superscalar processor and the multimedia adapter, the superscalar processor including a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution including:
an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element;
a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the predecode storage elements assuming each instruction storage element stores a first instruction byte of a variable-length instruction;
a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and
a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel.

76. A multimedia computer system according to claim 75 further comprising:

a multimedia signal acquisition device.

77. A multimedia computer system according to claim 76 wherein:

the multimedia performance device includes a motion video display selected from the group of televisions, high-definition televisions and high resolution computer monitors;
the multimedia signal acquisition device includes a video camera; and
the multimedia adapter includes a motion video adapter.

78. A multimedia computer system according to claim 77 wherein:

the multimedia performance device includes a video frame buffer.

79. A multimedia computer system according to claim 77 wherein:

the multimedia adapter performance device includes a system for video encoding and decoding in accordance with Moving Pictures Expert Group (MPEG) standards.

80. A multimedia computer system according to claim 75 wherein:

the multimedia performance device includes a video frame buffer and a graphics display selected from the group of televisions, high-definition televisions and high resolution computer monitors; and
the multimedia adapter includes a graphics adapter selected from the group of SVGA, XGA, VESA, CGA and Hercules graphic standard adapters.

81. A multimedia computer system according to claim 75 wherein:

the multimedia performance device includes an audio performance device selected from among the group of mixing consoles, signal processing devices, synthesizers, MIDI sequencers, power amplifiers and speakers; and
the multimedia adapter includes an audio adapter selected from among the group of D/A interfaces and A/D interfaces.

82. A multimedia computer system according to claim 81 further comprising:

a multimedia signal acquisition device including an audio signal acquisition device selected from among the group including microphones, signal processing devices and digital samplers.

83. A multimedia computer system according to claim 75 further comprising:

an SCSI adapter coupled to the input/output bus; and
a read/write storage media coupled to the SCSI adapter for storing and accessing data including multimedia data.

84. A multimedia computer system according to claim 83 wherein the read/write storage media include media selected from among the group of magnetic disk drives, magnetic tape drives and CD-ROM drives.

85. A multimedia computer system according to claim 75 further comprising:

a local area network (LAN) adapter coupled to the input/output bus.
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Patent History
Patent number: 5819056
Type: Grant
Filed: May 16, 1996
Date of Patent: Oct 6, 1998
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Inventor: John G. Favor (San Jose, CA)
Primary Examiner: William M. Treat
Attorney: Skjerven Morrill MacPherson Franklin & Friel, L.L.P.
Application Number: 8/649,995
Classifications
Current U.S. Class: 395/380; 395/389; 395/386; 395/388; 395/80023
International Classification: G06F 930;